diff options
| author | York Sun | 2016-10-05 13:19:08 -0700 |
|---|---|---|
| committer | York Sun | 2016-10-06 14:28:32 -0700 |
| commit | 3c6b1767c26aea37f0ee1d3c104c7feba2cea060 (patch) | |
| tree | 1f4c2befa81137da7d875692f637a5383a785c59 /drivers | |
| parent | 53d76829d517135381ee94519828128206e70db6 (diff) | |
spi: fsl_qspi: Preserve endianness of QSPI MCR
The endianness can be changed by RCW + PBI sequence. It may have
other than power on reset value.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Yuan Yao <yao.yuan@nxp.com>
CC: Peng Fan <peng.fan@nxp.com>
CC: Alison Wang <alison.wang@nxp.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/spi/fsl_qspi.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 2144fca665e..729ded9a050 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -865,6 +865,7 @@ static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave) struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { + u32 mcr_val; struct fsl_qspi *qspi; struct fsl_qspi_regs *regs; u32 total_size; @@ -896,8 +897,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, qspi->slave.max_write_size = TX_BUFFER_SIZE; + mcr_val = qspi_read32(qspi->priv.flags, ®s->mcr); qspi_write32(qspi->priv.flags, ®s->mcr, - QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK); + QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK | + (mcr_val & QSPI_MCR_END_CFD_MASK)); qspi_cfg_smpr(&qspi->priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK | @@ -975,6 +978,7 @@ static int fsl_qspi_child_pre_probe(struct udevice *dev) static int fsl_qspi_probe(struct udevice *bus) { + u32 mcr_val; u32 amba_size_per_chip; struct fsl_qspi_platdata *plat = dev_get_platdata(bus); struct fsl_qspi_priv *priv = dev_get_priv(bus); @@ -999,8 +1003,10 @@ static int fsl_qspi_probe(struct udevice *bus) priv->flash_num = plat->flash_num; priv->num_chipselect = plat->num_chipselect; + mcr_val = qspi_read32(priv->flags, &priv->regs->mcr); qspi_write32(priv->flags, &priv->regs->mcr, - QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK); + QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK | + (mcr_val & QSPI_MCR_END_CFD_MASK)); qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK | QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0); |