diff options
| author | Jonas Karlman | 2023-08-04 09:33:59 +0000 |
|---|---|---|
| committer | Kever Yang | 2023-08-12 10:35:35 +0800 |
| commit | 6da8400d7ae986ef2a8e0ddb4f39907c6c0666f1 (patch) | |
| tree | 9d3c048a08ce7d74434eedc808996281387cc564 /drivers | |
| parent | acb9812034850ae0d737a767b392b9cd097f3606 (diff) | |
clk: rockchip: rk3568: Fix mask for clk_cpll_div_25m_div
The field for clk_cpll_div_25m_div in CRU_CLKSEL_CON81 is 6 bits wide,
not 5 bits wide as currently defined in CPLL_25M_DIV_MASK.
Fix this and the assert so that CPLL_25M can be assigned a 25 MHz rate.
Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3568.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index e8e4d20e532..dab254d4d11 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -702,7 +702,10 @@ static ulong rk3568_cpll_div_set_rate(struct rk3568_clk_priv *priv, } div = DIV_ROUND_UP(priv->cpll_hz, rate); - assert(div - 1 <= 31); + if (clk_id == CPLL_25M) + assert(div - 1 <= 63); + else + assert(div - 1 <= 31); rk_clrsetreg(&cru->clksel_con[con], mask, (div - 1) << shift); return rk3568_cpll_div_get_rate(priv, clk_id); |