diff options
| author | Bin Meng | 2015-02-04 16:26:12 +0800 |
|---|---|---|
| committer | Simon Glass | 2015-02-06 12:07:45 -0700 |
| commit | 728b393f3b012ac46505151b80af1d4334786845 (patch) | |
| tree | f7a9eaa7476cad5432886ee7d121044d7adc035a /drivers | |
| parent | 38fc1cdae0fb7a429222b7b85f8cdaefbd078e21 (diff) | |
x86: Add SPI support to quark/galileo
The Quark SoC contains a legacy SPI controller in the legacy bridge
which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS
control register offset in the ICH SPI driver is wrong for the Quark
SoC too, unprotect_spi_flash() is added to enable the flash write.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/spi/ich.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index da857791e06..194e8823028 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -177,7 +177,8 @@ void spi_free_slave(struct spi_slave *slave) static int get_ich_version(uint16_t device_id) { if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC || - device_id == PCI_DEVICE_ID_INTEL_ITC_LPC) + device_id == PCI_DEVICE_ID_INTEL_ITC_LPC || + device_id == PCI_DEVICE_ID_INTEL_QRK_ILB) return 7; if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && |