diff options
author | Jim Liu | 2022-12-20 16:49:31 +0800 |
---|---|---|
committer | Tom Rini | 2023-01-10 15:39:06 -0500 |
commit | 7ee1c4d1d125a1c76ff2d5d044f3844f74941cc4 (patch) | |
tree | 2054d17f02a35489b6168004d97a3236c42c59a7 /drivers | |
parent | 92bdaecf39a1c02c49bc940f06f5ac80daf1b2ad (diff) |
pinctrl: nuvoton: add NPCM7xx/NPCM8xx reset type detect
add reset type detect and persist setting.
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c | 20 | ||||
-rw-r--r-- | drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 22 |
2 files changed, 41 insertions, 1 deletions
diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c index 31678f55379..1ad8bfbd880 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c @@ -47,6 +47,10 @@ #define WD0RST BIT(29) #define WD1RST BIT(24) #define WD2RST BIT(23) +#define SWRST1 BIT(28) +#define SWRST2 BIT(27) +#define SWRST3 BIT(26) +#define SW4RST BIT(25) #define GPIOX_MODULE_RESET 16 #define CA9C_RESET BIT(0) @@ -1374,6 +1378,14 @@ static bool is_gpio_persist(struct udevice *dev, u8 bank) regmap_read(priv->rst_regmap, NPCM7XX_RST_WD1RCR, &tmp); else if (value & WD2RST) regmap_read(priv->rst_regmap, NPCM7XX_RST_WD2RCR, &tmp); + else if (value & SWRST1) + regmap_read(priv->rst_regmap, NPCM7XX_RST_SWRSTC1, &tmp); + else if (value & SWRST2) + regmap_read(priv->rst_regmap, NPCM7XX_RST_SWRSTC2, &tmp); + else if (value & SWRST3) + regmap_read(priv->rst_regmap, NPCM7XX_RST_SWRSTC3, &tmp); + else if (value & SW4RST) + regmap_read(priv->rst_regmap, NPCM7XX_RST_SWRSTC4, &tmp); else return false; @@ -1392,11 +1404,19 @@ static int npcm7xx_gpio_reset_persist(struct udevice *dev, unsigned int banknum, regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD1RCR, BIT(num), 0); regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD2RCR, BIT(num), 0); regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_CORSTC, BIT(num), 0); + regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_SWRSTC1, BIT(num), 0); + regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_SWRSTC2, BIT(num), 0); + regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_SWRSTC3, BIT(num), 0); + regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_SWRSTC4, BIT(num), 0); } else { regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD0RCR, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET); regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD1RCR, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET); regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD2RCR, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET); regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_CORSTC, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET); + regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_SWRSTC1, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET); + regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_SWRSTC2, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET); + regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_SWRSTC3, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET); + regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_SWRSTC4, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET); } return 0; diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c index c6ffa89f77a..0ec47e9577e 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c @@ -20,7 +20,7 @@ #define SWRSTC1 0x44 #define SWRSTC2 0x48 #define SWRSTC3 0x4c -#define SWRSTC4 0x50 +#define TIPRSTC 0x50 #define CORSTC 0x5c #define FLOCKR1 0x74 #define INTCR4 0xc0 @@ -772,6 +772,10 @@ static int npcm8xx_gpio_reset_persist(struct udevice *dev, uint bank, regmap_update_bits(priv->rst_regmap, WD1RCR, BIT(offset), 0); regmap_update_bits(priv->rst_regmap, WD2RCR, BIT(offset), 0); regmap_update_bits(priv->rst_regmap, CORSTC, BIT(offset), 0); + regmap_update_bits(priv->rst_regmap, SWRSTC1, BIT(offset), 0); + regmap_update_bits(priv->rst_regmap, SWRSTC2, BIT(offset), 0); + regmap_update_bits(priv->rst_regmap, SWRSTC3, BIT(offset), 0); + regmap_update_bits(priv->rst_regmap, TIPRSTC, BIT(offset), 0); } else { regmap_update_bits(priv->rst_regmap, WD0RCR, BIT(offset), BIT(offset)); @@ -781,6 +785,14 @@ static int npcm8xx_gpio_reset_persist(struct udevice *dev, uint bank, BIT(offset)); regmap_update_bits(priv->rst_regmap, CORSTC, BIT(offset), BIT(offset)); + regmap_update_bits(priv->rst_regmap, SWRSTC1, BIT(offset), + BIT(offset)); + regmap_update_bits(priv->rst_regmap, SWRSTC2, BIT(offset), + BIT(offset)); + regmap_update_bits(priv->rst_regmap, SWRSTC3, BIT(offset), + BIT(offset)); + regmap_update_bits(priv->rst_regmap, TIPRSTC, BIT(offset), + BIT(offset)); } return 0; @@ -804,6 +816,14 @@ static bool is_gpio_persist(struct udevice *dev, uint bank) regmap_read(priv->rst_regmap, WD1RCR, &val); else if (status & WD2RST) regmap_read(priv->rst_regmap, WD2RCR, &val); + else if (status & SW1RST) + regmap_read(priv->rst_regmap, SWRSTC1, &val); + else if (status & SW2RST) + regmap_read(priv->rst_regmap, SWRSTC2, &val); + else if (status & SW3RST) + regmap_read(priv->rst_regmap, SWRSTC3, &val); + else if (status & TIPRST) + regmap_read(priv->rst_regmap, TIPRSTC, &val); else return false; |