diff options
| author | Tom Rini | 2018-02-25 15:39:10 -0500 |
|---|---|---|
| committer | Tom Rini | 2018-02-25 15:39:10 -0500 |
| commit | 85447f785ce8c0ab8e40850dc457a1fc833d224f (patch) | |
| tree | 7249f4bdabccba17f56135c4416a62b0cc50be3b /drivers | |
| parent | e12546de54fc9be818e8d39967b07fa351d9e5ba (diff) | |
| parent | 434d5a00a4578f826e7e2cef29bf2388dd760a88 (diff) | |
Merge git://git.denx.de/u-boot-rockchip
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3368.c | 19 | ||||
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3399.c | 19 |
2 files changed, 38 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c index 3ac9add527b..ea00f1fc9cc 100644 --- a/drivers/clk/rockchip/clk_rk3368.c +++ b/drivers/clk/rockchip/clk_rk3368.c @@ -568,12 +568,31 @@ static int __maybe_unused rk3368_clk_set_parent(struct clk *clk, struct clk *par return -ENOENT; } +static int rk3368_clk_enable(struct clk *clk) +{ + switch (clk->id) { + case SCLK_MAC: + case SCLK_MAC_RX: + case SCLK_MAC_TX: + case SCLK_MACREF: + case SCLK_MACREF_OUT: + case ACLK_GMAC: + case PCLK_GMAC: + /* Required to successfully probe the Designware GMAC driver */ + return 0; + } + + debug("%s: unsupported clk %ld\n", __func__, clk->id); + return -ENOENT; +} + static struct clk_ops rk3368_clk_ops = { .get_rate = rk3368_clk_get_rate, .set_rate = rk3368_clk_set_rate, #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) .set_parent = rk3368_clk_set_parent, #endif + .enable = rk3368_clk_enable, }; static int rk3368_clk_probe(struct udevice *dev) diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 42926ba323b..fb74c441ff9 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -997,6 +997,16 @@ static int rk3399_clk_enable(struct clk *clk) case HCLK_HOST1: case HCLK_HOST1_ARB: return 0; + + case SCLK_MAC: + case SCLK_MAC_RX: + case SCLK_MAC_TX: + case SCLK_MACREF: + case SCLK_MACREF_OUT: + case ACLK_GMAC: + case PCLK_GMAC: + /* Required to successfully probe the Designware GMAC driver */ + return 0; } debug("%s: unsupported clk %ld\n", __func__, clk->id); @@ -1236,6 +1246,8 @@ static ulong rk3399_pmuclk_get_rate(struct clk *clk) ulong rate = 0; switch (clk->id) { + case PLL_PPLL: + return PPLL_HZ; case PCLK_RKPWM_PMU: rate = rk3399_pwm_get_clk(priv->pmucru); break; @@ -1257,6 +1269,13 @@ static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate) ulong ret = 0; switch (clk->id) { + case PLL_PPLL: + /* + * This has already been set up and we don't want/need + * to change it here. Accept the request though, as the + * device-tree has this in an 'assigned-clocks' list. + */ + return PPLL_HZ; case SCLK_I2C0_PMU: case SCLK_I2C4_PMU: case SCLK_I2C8_PMU: |