diff options
| author | wdenk | 2003-07-14 22:13:32 +0000 |
|---|---|---|
| committer | wdenk | 2003-07-14 22:13:32 +0000 |
| commit | 8564acf936726c5568d71e4fa93a0ae9814e0d07 (patch) | |
| tree | 05fa981555adf1d333970f3d52d0683008fe3cfb /drivers | |
| parent | 5702923e23238df6c6f62d53f73863462ae62f4e (diff) | |
* Patches by Yuli Barcohen, 13 Jul 2003:
- Correct flash and JFFS2 support for MPC8260ADS
- fix PVR values and clock generation for PowerQUICC II family
(8270/8275/8280)
* Patch by Bernhard Kuhn, 08 Jul 2003:
- add support for M68K targets
* Patch by Ken Chou, 3 Jul:
- Fix PCI config table for A3000
- Fix iobase for natsemi.c
(PCI_BASE_ADDRESS_0 is the IO base register for DP83815)
* Allow to enable "slow" POST routines by key press on power-on
* Fix temperature dependend switching of LCD backlight on LWMON
* Tweak output format for LWMON
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/natsemi.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/natsemi.c b/drivers/natsemi.c index 0bed04dbbdf..1c1b9a09b80 100644 --- a/drivers/natsemi.c +++ b/drivers/natsemi.c @@ -306,8 +306,8 @@ natsemi_initialize(bd_t * bis) break; } - pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); - iobase &= ~0xF; /* Masked out the low bits that are addresses. */ + pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase); + iobase &= ~0x3; /* bit 1: unused and bit 0: I/O Space Indicator */ pci_write_config_dword(devno, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |