diff options
| author | Liu Ying | 2012-10-06 04:16:04 +0000 |
|---|---|---|
| committer | Anatolij Gustschin | 2012-11-06 22:24:11 +0100 |
| commit | 945d069fb5c8932e74aeba178c60a9dc6e9cba93 (patch) | |
| tree | 6f8361c6771812663f2654467219bd7acd9dd513 /drivers | |
| parent | 1cc619be8b73abbee2fd6faf2cd4ade27b516531 (diff) | |
ipu common: reset ipuv3 correctly
This patch checks self-clear sw_ipu_rst bit in
SCR register of SRC controller to be cleared
after setting it to high to reset IPUv3. This
makes sure that IPUv3 finishes sofware reset.
A timeout mechanism is added to stop polling
on the bit status in case the bit could not be
cleared by the hardware automatically within
10 millisecond.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/video/ipu_common.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c index 0f2d113a6f1..ad4af5283a9 100644 --- a/drivers/video/ipu_common.c +++ b/drivers/video/ipu_common.c @@ -94,6 +94,7 @@ struct ipu_ch_param { temp1; \ }) +#define IPU_SW_RST_TOUT_USEC (10000) void clk_enable(struct clk *clk) { @@ -398,11 +399,20 @@ void ipu_reset(void) { u32 *reg; u32 value; + int timeout = IPU_SW_RST_TOUT_USEC; reg = (u32 *)SRC_BASE_ADDR; value = __raw_readl(reg); value = value | SW_IPU_RST; __raw_writel(value, reg); + + while (__raw_readl(reg) & SW_IPU_RST) { + udelay(1); + if (!(timeout--)) { + printf("ipu software reset timeout\n"); + break; + } + }; } /* |