x86: broadwell: Add video support

Add a video driver for Intel's broadwell integrated graphics controller.
This uses a binary blob for most init, with the driver just performing a few
basic tasks.

This driver supports VESA as the mode-setting mechanism. Since most boards
don't support driver model yet with VESA, a special case is added to the
Kconfig for broadwell. Eventually all boards will use driver model and this
can be removed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>

4 files changed, 1174 insertions, 1 deletions

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index ff4179fcd89..8361a717e76 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -112,7 +112,7 @@ config VIDEO_VESA
 
 config FRAMEBUFFER_SET_VESA_MODE
 	bool "Set framebuffer graphics resolution"
-	depends on VIDEO_VESA
+	depends on VIDEO_VESA || VIDEO_BROADWELL_IGD
 	help
 	  Set VESA/native framebuffer mode (needed for bootsplash and graphical
 	  framebuffer console)
@@ -362,6 +362,18 @@ config DISPLAY
 	   The devices provide a simple interface to start up the display,
 	   read display information and enable it.
 
+config VIDEO_BROADWELL_IGD
+	bool "Enable Intel Broadwell integrated graphics device"
+	depends on X86
+	help
+	  This enabled support for integrated graphics on Intel broadwell
+	  devices. Initialisation is mostly performed by a VGA boot ROM, with
+	  some setup handled by U-Boot itself. The graphics adaptor works as
+	  a VESA device and supports LCD panels, eDP and LVDS outputs.
+	  Configuration of most aspects of device operation is performed using
+	  a special tool which configures the VGA ROM, but the graphics
+	  resolution can be selected in U-Boot.
+
 config VIDEO_ROCKCHIP
 	bool "Enable Rockchip video support"
 	depends on DM_VIDEO
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 9b635fc4037..2fd0891e5dd 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -19,6 +19,8 @@ obj-$(CONFIG_CONSOLE_ROTATION) += console_rotate.o
 obj-$(CONFIG_CONSOLE_TRUETYPE) += console_truetype.o fonts/
 endif
 
+obj-$(CONFIG_VIDEO_BROADWELL_IGD) += broadwell_igd.o
+
 obj-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o
 obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o
 obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
diff --git a/drivers/video/broadwell_igd.c b/drivers/video/broadwell_igd.c
new file mode 100644
index 00000000000..ce4f296d0a0
--- /dev/null
+++ b/drivers/video/broadwell_igd.c
@@ -0,0 +1,797 @@
+/*
+ * From coreboot src/soc/intel/broadwell/igd.c
+ *
+ * Copyright (C) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <bios_emul.h>
+#include <dm.h>
+#include <pci_rom.h>
+#include <vbe.h>
+#include <video.h>
+#include <video_fb.h>
+#include <asm/cpu.h>
+#include <asm/intel_regs.h>
+#include <asm/io.h>
+#include <asm/mtrr.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/iomap.h>
+#include <asm/arch/pch.h>
+#include <linux/log2.h>
+#include "i915_reg.h"
+
+struct broadwell_igd_priv {
+	GraphicDevice ctfb;
+	u8 *regs;
+};
+
+struct broadwell_igd_plat {
+	u32 dp_hotplug[3];
+
+	int port_select;
+	int power_up_delay;
+	int power_backlight_on_delay;
+	int power_down_delay;
+	int power_backlight_off_delay;
+	int power_cycle_delay;
+	int cpu_backlight;
+	int pch_backlight;
+	int cdclk;
+	int pre_graphics_delay;
+};
+
+#define GT_RETRY		1000
+#define GT_CDCLK_337		0
+#define GT_CDCLK_450		1
+#define GT_CDCLK_540		2
+#define GT_CDCLK_675		3
+
+u32 board_map_oprom_vendev(u32 vendev)
+{
+	return SA_IGD_OPROM_VENDEV;
+}
+
+static int poll32(u8 *addr, uint mask, uint value)
+{
+	ulong start;
+
+	start = get_timer(0);
+	debug("%s: addr %p = %x\n", __func__, addr, readl(addr));
+	while ((readl(addr) & mask) != value) {
+		if (get_timer(start) > GT_RETRY) {
+			debug("poll32: timeout: %x\n", readl(addr));
+			return -ETIMEDOUT;
+		}
+	}
+
+	return 0;
+}
+
+static int haswell_early_init(struct udevice *dev)
+{
+	struct broadwell_igd_priv *priv = dev_get_priv(dev);
+	u8 *regs = priv->regs;
+	int ret;
+
+	/* Enable Force Wake */
+	writel(0x00000020, regs + 0xa180);
+	writel(0x00010001, regs + 0xa188);
+	ret = poll32(regs + 0x130044, 1, 1);
+	if (ret)
+		goto err;
+
+	/* Enable Counters */
+	setbits_le32(regs + 0xa248, 0x00000016);
+
+	/* GFXPAUSE settings */
+	writel(0x00070020, regs + 0xa000);
+
+	/* ECO Settings */
+	clrsetbits_le32(regs + 0xa180, ~0xff3fffff, 0x15000000);
+
+	/* Enable DOP Clock Gating */
+	writel(0x000003fd, regs + 0x9424);
+
+	/* Enable Unit Level Clock Gating */
+	writel(0x00000080, regs + 0x9400);
+	writel(0x40401000, regs + 0x9404);
+	writel(0x00000000, regs + 0x9408);
+	writel(0x02000001, regs + 0x940c);
+
+	/*
+	 * RC6 Settings
+	 */
+
+	/* Wake Rate Limits */
+	setbits_le32(regs + 0xa090, 0x00000000);
+	setbits_le32(regs + 0xa098, 0x03e80000);
+	setbits_le32(regs + 0xa09c, 0x00280000);
+	setbits_le32(regs + 0xa0a8, 0x0001e848);
+	setbits_le32(regs + 0xa0ac, 0x00000019);
+
+	/* Render/Video/Blitter Idle Max Count */
+	writel(0x0000000a, regs + 0x02054);
+	writel(0x0000000a, regs + 0x12054);
+	writel(0x0000000a, regs + 0x22054);
+	writel(0x0000000a, regs + 0x1a054);
+
+	/* RC Sleep / RCx Thresholds */
+	setbits_le32(regs + 0xa0b0, 0x00000000);
+	setbits_le32(regs + 0xa0b4, 0x000003e8);
+	setbits_le32(regs + 0xa0b8, 0x0000c350);
+
+	/* RP Settings */
+	setbits_le32(regs + 0xa010, 0x000f4240);
+	setbits_le32(regs + 0xa014, 0x12060000);
+	setbits_le32(regs + 0xa02c, 0x0000e808);
+	setbits_le32(regs + 0xa030, 0x0003bd08);
+	setbits_le32(regs + 0xa068, 0x000101d0);
+	setbits_le32(regs + 0xa06c, 0x00055730);
+	setbits_le32(regs + 0xa070, 0x0000000a);
+
+	/* RP Control */
+	writel(0x00000b92, regs + 0xa024);
+
+	/* HW RC6 Control */
+	writel(0x88040000, regs + 0xa090);
+
+	/* Video Frequency Request */
+	writel(0x08000000, regs + 0xa00c);
+
+	/* Set RC6 VIDs */
+	ret = poll32(regs + 0x138124, (1 << 31), 0);
+	if (ret)
+		goto err;
+	writel(0, regs + 0x138128);
+	writel(0x80000004, regs + 0x138124);
+	ret = poll32(regs + 0x138124, (1 << 31), 0);
+	if (ret)
+		goto err;
+
+	/* Enable PM Interrupts */
+	writel(0x03000076, regs + 0x4402c);
+
+	/* Enable RC6 in idle */
+	writel(0x00040000, regs + 0xa094);
+
+	return 0;
+err:
+	debug("%s: ret=%d\n", __func__, ret);
+	return ret;
+};
+
+static int haswell_late_init(struct udevice *dev)
+{
+	struct broadwell_igd_priv *priv = dev_get_priv(dev);
+	u8 *regs = priv->regs;
+	int ret;
+
+	/* Lock settings */
+	setbits_le32(regs + 0x0a248, (1 << 31));
+	setbits_le32(regs + 0x0a004, (1 << 4));
+	setbits_le32(regs + 0x0a080, (1 << 2));
+	setbits_le32(regs + 0x0a180, (1 << 31));
+
+	/* Disable Force Wake */
+	writel(0x00010000, regs + 0xa188);
+	ret = poll32(regs + 0x130044, 1, 0);
+	if (ret)
+		goto err;
+	writel(0x00000001, regs + 0xa188);
+
+	/* Enable power well for DP and Audio */
+	setbits_le32(regs + 0x45400, (1 << 31));
+	ret = poll32(regs + 0x45400, 1 << 30, 1 << 30);
+	if (ret)
+		goto err;
+
+	return 0;
+err:
+	debug("%s: ret=%d\n", __func__, ret);
+	return ret;
+};
+
+static int broadwell_early_init(struct udevice *dev)
+{
+	struct broadwell_igd_priv *priv = dev_get_priv(dev);
+	u8 *regs = priv->regs;
+	int ret;
+
+	/* Enable Force Wake */
+	writel(0x00010001, regs + 0xa188);
+	ret = poll32(regs + 0x130044, 1, 1);
+	if (ret)
+		goto err;
+
+	/* Enable push bus metric control and shift */
+	writel(0x00000004, regs + 0xa248);
+	writel(0x000000ff, regs + 0xa250);
+	writel(0x00000010, regs + 0xa25c);
+
+	/* GFXPAUSE settings (set based on stepping) */
+
+	/* ECO Settings */
+	writel(0x45200000, regs + 0xa180);
+
+	/* Enable DOP Clock Gating */
+	writel(0x000000fd, regs + 0x9424);
+
+	/* Enable Unit Level Clock Gating */
+	writel(0x00000000, regs + 0x9400);
+	writel(0x40401000, regs + 0x9404);
+	writel(0x00000000, regs + 0x9408);
+	writel(0x02000001, regs + 0x940c);
+	writel(0x0000000a, regs + 0x1a054);
+
+	/* Video Frequency Request */
+	writel(0x08000000, regs + 0xa00c);
+
+	writel(0x00000009, regs + 0x138158);
+	writel(0x0000000d, regs + 0x13815c);
+
+	/*
+	 * RC6 Settings
+	 */
+
+	/* Wake Rate Limits */
+	clrsetbits_le32(regs + 0x0a090, ~0, 0);
+	setbits_le32(regs + 0x0a098, 0x03e80000);
+	setbits_le32(regs + 0x0a09c, 0x00280000);
+	setbits_le32(regs + 0x0a0a8, 0x0001e848);
+	setbits_le32(regs + 0x0a0ac, 0x00000019);
+
+	/* Render/Video/Blitter Idle Max Count */
+	writel(0x0000000a, regs + 0x02054);
+	writel(0x0000000a, regs + 0x12054);
+	writel(0x0000000a, regs + 0x22054);
+
+	/* RC Sleep / RCx Thresholds */
+	setbits_le32(regs + 0x0a0b0, 0x00000000);
+	setbits_le32(regs + 0x0a0b8, 0x00000271);
+
+	/* RP Settings */
+	setbits_le32(regs + 0x0a010, 0x000f4240);
+	setbits_le32(regs + 0x0a014, 0x12060000);
+	setbits_le32(regs + 0x0a02c, 0x0000e808);
+	setbits_le32(regs + 0x0a030, 0x0003bd08);
+	setbits_le32(regs + 0x0a068, 0x000101d0);
+	setbits_le32(regs + 0x0a06c, 0x00055730);
+	setbits_le32(regs + 0x0a070, 0x0000000a);
+	setbits_le32(regs + 0x0a168, 0x00000006);
+
+	/* RP Control */
+	writel(0x00000b92, regs + 0xa024);
+
+	/* HW RC6 Control */
+	writel(0x90040000, regs + 0xa090);
+
+	/* Set RC6 VIDs */
+	ret = poll32(regs + 0x138124, (1 << 31), 0);
+	if (ret)
+		goto err;
+	writel(0, regs + 0x138128);
+	writel(0x80000004, regs + 0x138124);
+	ret = poll32(regs + 0x138124, (1 << 31), 0);
+	if (ret)
+		goto err;
+
+	/* Enable PM Interrupts */
+	writel(0x03000076, regs + 0x4402c);
+
+	/* Enable RC6 in idle */
+	writel(0x00040000, regs + 0xa094);
+
+	return 0;
+err:
+	debug("%s: ret=%d\n", __func__, ret);
+	return ret;
+}
+
+static int broadwell_late_init(struct udevice *dev)
+{
+	struct broadwell_igd_priv *priv = dev_get_priv(dev);
+	u8 *regs = priv->regs;
+	int ret;
+
+	/* Lock settings */
+	setbits_le32(regs + 0x0a248, 1 << 31);
+	setbits_le32(regs + 0x0a000, 1 << 18);
+	setbits_le32(regs + 0x0a180, 1 << 31);
+
+	/* Disable Force Wake */
+	writel(0x00010000, regs + 0xa188);
+	ret = poll32(regs + 0x130044, 1, 0);
+	if (ret)
+		goto err;
+
+	/* Enable power well for DP and Audio */
+	setbits_le32(regs + 0x45400, 1 << 31);
+	ret = poll32(regs + 0x45400, 1 << 30, 1 << 30);
+	if (ret)
+		goto err;
+
+	return 0;
+err:
+	debug("%s: ret=%d\n", __func__, ret);
+	return ret;
+};
+
+
+static unsigned long gtt_read(struct broadwell_igd_priv *priv,
+			      unsigned long reg)
+{
+	u32 val;
+
+	val = readl(priv->regs + reg);
+	return val;
+}
+
+static void gtt_write(struct broadwell_igd_priv *priv, unsigned long reg,
+		      unsigned long data)
+{
+	writel(data, priv->regs + reg);
+}
+
+static inline void gtt_clrsetbits(struct broadwell_igd_priv *priv, u32 reg,
+				  u32 bic, u32 or)
+{
+	clrsetbits_le32(priv->regs + reg, bic, or);
+}
+
+static int gtt_poll(struct broadwell_igd_priv *priv, u32 reg, u32 mask,
+		    u32 value)
+{
+	unsigned try = GT_RETRY;
+	u32 data;
+
+	while (try--) {
+		data = gtt_read(priv, reg);
+		if ((data & mask) == value)
+			return 0;
+		udelay(10);
+	}
+
+	debug("GT init timeout\n");
+	return -ETIMEDOUT;
+}
+
+static void igd_setup_panel(struct udevice *dev)
+{
+	struct broadwell_igd_plat *plat = dev_get_platdata(dev);
+	struct broadwell_igd_priv *priv = dev_get_priv(dev);
+	u32 reg32;
+
+	/* Setup Digital Port Hotplug */
+	reg32 = (plat->dp_hotplug[0] & 0x7) << 2;
+	reg32 |= (plat->dp_hotplug[1] & 0x7) << 10;
+	reg32 |= (plat->dp_hotplug[2] & 0x7) << 18;
+	gtt_write(priv, PCH_PORT_HOTPLUG, reg32);
+
+	/* Setup Panel Power On Delays */
+	reg32 = (plat->port_select & 0x3) << 30;
+	reg32 |= (plat->power_up_delay & 0x1fff) << 16;
+	reg32 |= (plat->power_backlight_on_delay & 0x1fff);
+	gtt_write(priv, PCH_PP_ON_DELAYS, reg32);
+
+	/* Setup Panel Power Off Delays */
+	reg32 = (plat->power_down_delay & 0x1fff) << 16;
+	reg32 |= (plat->power_backlight_off_delay & 0x1fff);
+	gtt_write(priv, PCH_PP_OFF_DELAYS, reg32);
+
+	/* Setup Panel Power Cycle Delay */
+	if (plat->power_cycle_delay) {
+		reg32 = gtt_read(priv, PCH_PP_DIVISOR);
+		reg32 &= ~0xff;
+		reg32 |= plat->power_cycle_delay & 0xff;
+		gtt_write(priv, PCH_PP_DIVISOR, reg32);
+	}
+
+	/* Enable Backlight if needed */
+	if (plat->cpu_backlight) {
+		gtt_write(priv, BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE);
+		gtt_write(priv, BLC_PWM_CPU_CTL, plat->cpu_backlight);
+	}
+	if (plat->pch_backlight) {
+		gtt_write(priv, BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE);
+		gtt_write(priv, BLC_PWM_PCH_CTL2, plat->pch_backlight);
+	}
+}
+
+static int igd_cdclk_init_haswell(struct udevice *dev)
+{
+	struct broadwell_igd_plat *plat = dev_get_platdata(dev);
+	struct broadwell_igd_priv *priv = dev_get_priv(dev);
+	int cdclk = plat->cdclk;
+	u16 devid;
+	int gpu_is_ulx = 0;
+	u32 dpdiv, lpcll;
+	int ret;
+
+	dm_pci_read_config16(dev, PCI_DEVICE_ID, &devid);
+
+	/* Check for ULX GT1 or GT2 */
+	if (devid == 0x0a0e || devid == 0x0a1e)
+		gpu_is_ulx = 1;
+
+	/* 675MHz is not supported on haswell */
+	if (cdclk == GT_CDCLK_675)
+		cdclk = GT_CDCLK_337;
+
+	/* If CD clock is fixed or ULT then set to 450MHz */
+	if ((gtt_read(priv, 0x42014) & 0x1000000) || cpu_is_ult())
+		cdclk = GT_CDCLK_450;
+
+	/* 540MHz is not supported on ULX */
+	if (gpu_is_ulx && cdclk == GT_CDCLK_540)
+		cdclk = GT_CDCLK_337;
+
+	/* 337.5MHz is not supported on non-ULT/ULX */
+	if (!gpu_is_ulx && !cpu_is_ult() && cdclk == GT_CDCLK_337)
+		cdclk = GT_CDCLK_450;
+
+	/* Set variables based on CD Clock setting */
+	switch (cdclk) {
+	case GT_CDCLK_337:
+		dpdiv = 169;
+		lpcll = (1 << 26);
+		break;
+	case GT_CDCLK_450:
+		dpdiv = 225;
+		lpcll = 0;
+		break;
+	case GT_CDCLK_540:
+		dpdiv = 270;
+		lpcll = (1 << 26);
+		break;
+	default:
+		ret = -EDOM;
+		goto err;
+	}
+
+	/* Set LPCLL_CTL CD Clock Frequency Select */
+	gtt_clrsetbits(priv, 0x130040, ~0xf3ffffff, lpcll);
+
+	/* ULX: Inform power controller of selected frequency */
+	if (gpu_is_ulx) {
+		if (cdclk == GT_CDCLK_450)
+			gtt_write(priv, 0x138128, 0x00000000); /* 450MHz */
+		else
+			gtt_write(priv, 0x138128, 0x00000001); /* 337.5MHz */
+		gtt_write(priv, 0x13812c, 0x00000000);
+		gtt_write(priv, 0x138124, 0x80000017);
+	}
+
+	/* Set CPU DP AUX 2X bit clock dividers */
+	gtt_clrsetbits(priv, 0x64010, ~0xfffff800, dpdiv);
+	gtt_clrsetbits(priv, 0x64810, ~0xfffff800, dpdiv);
+
+	return 0;
+err:
+	debug("%s: ret=%d\n", __func__, ret);
+	return ret;
+}
+
+static int igd_cdclk_init_broadwell(struct udevice *dev)
+{
+	struct broadwell_igd_plat *plat = dev_get_platdata(dev);
+	struct broadwell_igd_priv *priv = dev_get_priv(dev);
+	int cdclk = plat->cdclk;
+	u32 dpdiv, lpcll, pwctl, cdset;
+	int ret;
+
+	/* Inform power controller of upcoming frequency change */
+	gtt_write(priv, 0x138128, 0);
+	gtt_write(priv, 0x13812c, 0);
+	gtt_write(priv, 0x138124, 0x80000018);
+
+	/* Poll GT driver mailbox for run/busy clear */
+	if (gtt_poll(priv, 0x138124, 1 << 31, 0 << 31))
+		cdclk = GT_CDCLK_450;
+
+	if (gtt_read(priv, 0x42014) & 0x1000000) {
+		/* If CD clock is fixed then set to 450MHz */
+		cdclk = GT_CDCLK_450;
+	} else {
+		/* Program CD clock to highest supported freq */
+		if (cpu_is_ult())
+			cdclk = GT_CDCLK_540;
+		else
+			cdclk = GT_CDCLK_675;
+	}
+
+	/* CD clock frequency 675MHz not supported on ULT */
+	if (cpu_is_ult() && cdclk == GT_CDCLK_675)
+		cdclk = GT_CDCLK_540;
+
+	/* Set variables based on CD Clock setting */
+	switch (cdclk) {
+	case GT_CDCLK_337:
+		cdset = 337;
+		lpcll = (1 << 27);
+		pwctl = 2;
+		dpdiv = 169;
+		break;
+	case GT_CDCLK_450:
+		cdset = 449;
+		lpcll = 0;
+		pwctl = 0;
+		dpdiv = 225;
+		break;
+	case GT_CDCLK_540:
+		cdset = 539;
+		lpcll = (1 << 26);
+		pwctl = 1;
+		dpdiv = 270;
+		break;
+	case GT_CDCLK_675:
+		cdset = 674;
+		lpcll = (1 << 26) | (1 << 27);
+		pwctl = 3;
+		dpdiv = 338;
+		break;
+	default:
+		ret = -EDOM;
+		goto err;
+	}
+	debug("%s: frequency = %d\n", __func__, cdclk);
+
+	/* Set LPCLL_CTL CD Clock Frequency Select */
+	gtt_clrsetbits(priv, 0x130040, ~0xf3ffffff, lpcll);
+
+	/* Inform power controller of selected frequency */
+	gtt_write(priv, 0x138128, pwctl);
+	gtt_write(priv, 0x13812c, 0);
+	gtt_write(priv, 0x138124, 0x80000017);
+
+	/* Program CD Clock Frequency */
+	gtt_clrsetbits(priv, 0x46200, ~0xfffffc00, cdset);
+
+	/* Set CPU DP AUX 2X bit clock dividers */
+	gtt_clrsetbits(priv, 0x64010, ~0xfffff800, dpdiv);
+	gtt_clrsetbits(priv, 0x64810, ~0xfffff800, dpdiv);
+
+	return 0;
+err:
+	debug("%s: ret=%d\n", __func__, ret);
+	return ret;
+}
+
+u8 systemagent_revision(struct udevice *bus)
+{
+	ulong val;
+
+	pci_bus_read_config(bus, PCI_BDF(0, 0, 0), PCI_REVISION_ID, &val,
+			    PCI_SIZE_32);
+
+	return val;
+}
+
+static int igd_pre_init(struct udevice *dev, bool is_broadwell)
+{
+	struct broadwell_igd_plat *plat = dev_get_platdata(dev);
+	struct broadwell_igd_priv *priv = dev_get_priv(dev);
+	u32 rp1_gfx_freq;
+	int ret;
+
+	mdelay(plat->pre_graphics_delay);
+
+	/* Early init steps */
+	if (is_broadwell) {
+		ret = broadwell_early_init(dev);
+		if (ret)
+			goto err;
+
+		/* Set GFXPAUSE based on stepping */
+		if (cpu_get_stepping() <= (CPUID_BROADWELL_E0 & 0xf) &&
+		    systemagent_revision(pci_get_controller(dev)) <= 9) {
+			gtt_write(priv, 0xa000, 0x300ff);
+		} else {
+			gtt_write(priv, 0xa000, 0x30020);
+		}
+	} else {
+		ret = haswell_early_init(dev);
+		if (ret)
+			goto err;
+	}
+
+	/* Set RP1 graphics frequency */
+	rp1_gfx_freq = (readl(MCHBAR_REG(0x5998)) >> 8) & 0xff;
+	gtt_write(priv, 0xa008, rp1_gfx_freq << 24);
+
+	/* Post VBIOS panel setup */
+	igd_setup_panel(dev);
+
+	return 0;
+err:
+	debug("%s: ret=%d\n", __func__, ret);
+	return ret;
+}
+
+static int igd_post_init(struct udevice *dev, bool is_broadwell)
+{
+	int ret;
+
+	/* Late init steps */
+	if (is_broadwell) {
+		ret = igd_cdclk_init_broadwell(dev);
+		if (ret)
+			return ret;
+		ret = broadwell_late_init(dev);
+		if (ret)
+			return ret;
+	} else {
+		igd_cdclk_init_haswell(dev);
+		ret = haswell_late_init(dev);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int broadwell_igd_int15_handler(void)
+{
+	int res = 0;
+
+	debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX);
+
+	switch (M.x86.R_AX) {
+	case 0x5f35:
+		/*
+		 * Boot Display Device Hook:
+		 *  bit 0 = CRT
+		 *  bit 1 = TV (eDP)
+		 *  bit 2 = EFP
+		 *  bit 3 = LFP
+		 *  bit 4 = CRT2
+		 *  bit 5 = TV2 (eDP)
+		 *  bit 6 = EFP2
+		 *  bit 7 = LFP2
+		 */
+		M.x86.R_AX = 0x005f;
+		M.x86.R_CX = 0x0000; /* Use video bios default */
+		res = 1;
+		break;
+	default:
+		debug("Unknown INT15 function %04x!\n", M.x86.R_AX);
+		break;
+	}
+
+	return res;
+}
+
+static int broadwell_igd_probe(struct udevice *dev)
+{
+	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct broadwell_igd_priv *priv = dev_get_priv(dev);
+	bool is_broadwell;
+	GraphicDevice *gdev = &priv->ctfb;
+	int bits_per_pixel;
+	int ret;
+
+	if (!ll_boot_init()) {
+		/*
+		 * If we are running from EFI or coreboot, this driver can't
+		 * work.
+		 */
+		printf("Not available (previous bootloader prevents it)\n");
+		return -EPERM;
+	}
+	is_broadwell = cpu_get_family_model() == BROADWELL_FAMILY_ULT;
+	bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
+	debug("%s: is_broadwell=%d\n", __func__, is_broadwell);
+	ret = igd_pre_init(dev, is_broadwell);
+	if (!ret) {
+		ret = dm_pci_run_vga_bios(dev, broadwell_igd_int15_handler,
+					  PCI_ROM_USE_NATIVE |
+					  PCI_ROM_ALLOW_FALLBACK);
+		if (ret) {
+			printf("failed to run video BIOS: %d\n", ret);
+			ret = -EIO;
+		}
+	}
+	if (!ret)
+		ret = igd_post_init(dev, is_broadwell);
+	bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
+	if (ret)
+		return ret;
+
+	if (vbe_get_video_info(gdev)) {
+		printf("No video mode configured\n");
+		return -ENXIO;
+	}
+
+	/* Use write-through for the graphics memory, 256MB */
+	ret = mtrr_add_request(MTRR_TYPE_WRTHROUGH, gdev->pciBase, 256 << 20);
+	if (!ret)
+		ret = mtrr_commit(true);
+	if (ret && ret != -ENOSYS) {
+		printf("Failed to add MTRR: Display will be slow (err %d)\n",
+		       ret);
+	}
+
+	bits_per_pixel = gdev->gdfBytesPP * 8;
+	sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY,
+		bits_per_pixel);
+	printf("%s\n", gdev->modeIdent);
+	uc_priv->xsize = gdev->winSizeX;
+	uc_priv->ysize = gdev->winSizeY;
+	uc_priv->bpix = ilog2(bits_per_pixel);
+	plat->base = gdev->pciBase;
+	plat->size = gdev->memSize;
+	debug("fb=%x, size %x, display size=%d %d %d\n", gdev->pciBase,
+	      gdev->memSize, uc_priv->xsize, uc_priv->ysize, uc_priv->bpix);
+
+	return 0;
+}
+
+static int broadwell_igd_ofdata_to_platdata(struct udevice *dev)
+{
+	struct broadwell_igd_plat *plat = dev_get_platdata(dev);
+	struct broadwell_igd_priv *priv = dev_get_priv(dev);
+	int node = dev->of_offset;
+	const void *blob = gd->fdt_blob;
+
+	if (fdtdec_get_int_array(blob, node, "intel,dp-hotplug",
+				 plat->dp_hotplug,
+				 ARRAY_SIZE(plat->dp_hotplug)))
+		return -EINVAL;
+	plat->port_select = fdtdec_get_int(blob, node, "intel,port-select", 0);
+	plat->power_cycle_delay = fdtdec_get_int(blob, node,
+			"intel,power-cycle-delay", 0);
+	plat->power_up_delay = fdtdec_get_int(blob, node,
+			"intel,power-up-delay", 0);
+	plat->power_down_delay = fdtdec_get_int(blob, node,
+			"intel,power-down-delay", 0);
+	plat->power_backlight_on_delay = fdtdec_get_int(blob, node,
+			"intel,power-backlight-on-delay", 0);
+	plat->power_backlight_off_delay = fdtdec_get_int(blob, node,
+			"intel,power-backlight-off-delay", 0);
+	plat->cpu_backlight = fdtdec_get_int(blob, node,
+			"intel,cpu-backlight", 0);
+	plat->pch_backlight = fdtdec_get_int(blob, node,
+			"intel,pch-backlight", 0);
+	plat->pre_graphics_delay = fdtdec_get_int(blob, node,
+			"intel,pre-graphics-delay", 0);
+	priv->regs = (u8 *)dm_pci_read_bar32(dev, 0);
+	debug("%s: regs at %p\n", __func__, priv->regs);
+	debug("dp_hotplug %d %d %d\n", plat->dp_hotplug[0], plat->dp_hotplug[1],
+	      plat->dp_hotplug[2]);
+	debug("port_select = %d\n", plat->port_select);
+	debug("power_up_delay = %d\n", plat->power_up_delay);
+	debug("power_backlight_on_delay = %d\n",
+	      plat->power_backlight_on_delay);
+	debug("power_down_delay = %d\n", plat->power_down_delay);
+	debug("power_backlight_off_delay = %d\n",
+	      plat->power_backlight_off_delay);
+	debug("power_cycle_delay = %d\n", plat->power_cycle_delay);
+	debug("cpu_backlight = %x\n", plat->cpu_backlight);
+	debug("pch_backlight = %x\n", plat->pch_backlight);
+	debug("cdclk = %d\n", plat->cdclk);
+	debug("pre_graphics_delay = %d\n", plat->pre_graphics_delay);
+
+	return 0;
+}
+
+static const struct video_ops broadwell_igd_ops = {
+};
+
+static const struct udevice_id broadwell_igd_ids[] = {
+	{ .compatible = "intel,broadwell-igd" },
+	{ }
+};
+
+U_BOOT_DRIVER(broadwell_igd) = {
+	.name	= "broadwell_igd",
+	.id	= UCLASS_VIDEO,
+	.of_match = broadwell_igd_ids,
+	.ops	= &broadwell_igd_ops,
+	.ofdata_to_platdata = broadwell_igd_ofdata_to_platdata,
+	.probe	= broadwell_igd_probe,
+	.priv_auto_alloc_size	= sizeof(struct broadwell_igd_priv),
+	.platdata_auto_alloc_size	= sizeof(struct broadwell_igd_plat),
+};
diff --git a/drivers/video/i915_reg.h b/drivers/video/i915_reg.h
new file mode 100644
index 00000000000..f540b15d6ce
--- /dev/null
+++ b/drivers/video/i915_reg.h
@@ -0,0 +1,362 @@
+/*
+ * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef _I915_REG_H_
+#define _I915_REG_H_
+
+/* Hotplug control (945+ only) */
+#define PORT_HOTPLUG_EN		0x61110
+#define   HDMIB_HOTPLUG_INT_EN			(1 << 29)
+#define   DPB_HOTPLUG_INT_EN			(1 << 29)
+#define   HDMIC_HOTPLUG_INT_EN			(1 << 28)
+#define   DPC_HOTPLUG_INT_EN			(1 << 28)
+#define   HDMID_HOTPLUG_INT_EN			(1 << 27)
+#define   DPD_HOTPLUG_INT_EN			(1 << 27)
+#define   SDVOB_HOTPLUG_INT_EN			(1 << 26)
+#define   SDVOC_HOTPLUG_INT_EN			(1 << 25)
+#define   TV_HOTPLUG_INT_EN			(1 << 18)
+#define   CRT_HOTPLUG_INT_EN			(1 << 9)
+#define   CRT_HOTPLUG_FORCE_DETECT		(1 << 3)
+#define CRT_HOTPLUG_ACTIVATION_PERIOD_32	(0 << 8)
+/* must use period 64 on GM45 according to docs */
+#define CRT_HOTPLUG_ACTIVATION_PERIOD_64	(1 << 8)
+#define CRT_HOTPLUG_DAC_ON_TIME_2M		(0 << 7)
+#define CRT_HOTPLUG_DAC_ON_TIME_4M		(1 << 7)
+#define CRT_HOTPLUG_VOLTAGE_COMPARE_40		(0 << 5)
+#define CRT_HOTPLUG_VOLTAGE_COMPARE_50		(1 << 5)
+#define CRT_HOTPLUG_VOLTAGE_COMPARE_60		(2 << 5)
+#define CRT_HOTPLUG_VOLTAGE_COMPARE_70		(3 << 5)
+#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK	(3 << 5)
+#define CRT_HOTPLUG_DETECT_DELAY_1G		(0 << 4)
+#define CRT_HOTPLUG_DETECT_DELAY_2G		(1 << 4)
+#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV	(0 << 2)
+#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV	(1 << 2)
+
+/* Backlight control */
+#define BLC_PWM_CTL2		0x61250 /* 965+ only */
+#define   BLM_PWM_ENABLE		(1 << 31)
+#define   BLM_COMBINATION_MODE		(1 << 30) /* gen4 only */
+#define   BLM_PIPE_SELECT		(1 << 29)
+#define   BLM_PIPE_SELECT_IVB		(3 << 29)
+#define   BLM_PIPE_A			(0 << 29)
+#define   BLM_PIPE_B			(1 << 29)
+#define   BLM_PIPE_C			(2 << 29) /* ivb + */
+#define   BLM_PIPE(pipe)		((pipe) << 29)
+#define   BLM_POLARITY_I965		(1 << 28) /* gen4 only */
+#define   BLM_PHASE_IN_INTERUPT_STATUS	(1 << 26)
+#define   BLM_PHASE_IN_ENABLE		(1 << 25)
+#define   BLM_PHASE_IN_INTERUPT_ENABL	(1 << 24)
+#define   BLM_PHASE_IN_TIME_BASE_SHIFT	(16)
+#define   BLM_PHASE_IN_TIME_BASE_MASK	(0xff << 16)
+#define   BLM_PHASE_IN_COUNT_SHIFT	(8)
+#define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)
+#define   BLM_PHASE_IN_INCR_SHIFT	(0)
+#define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)
+#define BLC_PWM_CTL		0x61254
+/*
+ * This is the most significant 15 bits of the number of backlight cycles in a
+ * complete cycle of the modulated backlight control.
+ *
+ * The actual value is this field multiplied by two.
+ */
+#define   BACKLIGHT_MODULATION_FREQ_SHIFT	(17)
+#define   BACKLIGHT_MODULATION_FREQ_MASK	(0x7fff << 17)
+#define   BLM_LEGACY_MODE			(1 << 16) /* gen2 only */
+/*
+ * This is the number of cycles out of the backlight modulation cycle for which
+ * the backlight is on.
+ *
+ * This field must be no greater than the number of cycles in the complete
+ * backlight modulation cycle.
+ */
+#define   BACKLIGHT_DUTY_CYCLE_SHIFT		(0)
+#define   BACKLIGHT_DUTY_CYCLE_MASK		(0xffff)
+#define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)
+#define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */
+
+#define BLC_HIST_CTL		0x61260
+
+/*
+ * New registers for PCH-split platforms. Safe where new bits show up, the
+ * register layout machtes with gen4 BLC_PWM_CTL[12]
+ */
+#define BLC_PWM_CPU_CTL2	0x48250
+#define  BLC_PWM2_ENABLE        (1<<31)
+#define BLC_PWM_CPU_CTL		0x48254
+
+#define BLM_HIST_CTL			0x48260
+#define  ENH_HIST_ENABLE		(1<<31)
+#define  ENH_MODIF_TBL_ENABLE		(1<<30)
+#define  ENH_PIPE_A_SELECT		(0<<29)
+#define  ENH_PIPE_B_SELECT		(1<<29)
+#define  ENH_PIPE(pipe) _PIPE(pipe, ENH_PIPE_A_SELECT, ENH_PIPE_B_SELECT)
+#define  HIST_MODE_YUV			(0<<24)
+#define  HIST_MODE_HSV			(1<<24)
+#define  ENH_MODE_DIRECT		(0<<13)
+#define  ENH_MODE_ADDITIVE		(1<<13)
+#define  ENH_MODE_MULTIPLICATIVE	(2<<13)
+#define  BIN_REGISTER_SET		(1<<11)
+#define  ENH_NUM_BINS			32
+
+#define BLM_HIST_ENH			0x48264
+
+#define BLM_HIST_GUARD_BAND		0x48268
+#define  BLM_HIST_INTR_ENABLE		(1<<31)
+#define  BLM_HIST_EVENT_STATUS		(1<<30)
+#define  BLM_HIST_INTR_DELAY_MASK	(0xFF<<22)
+#define  BLM_HIST_INTR_DELAY_SHIFT	22
+
+/*
+ * PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
+ * like the normal CTL from gen4 and earlier. Hooray for confusing naming.
+ */
+#define BLC_PWM_PCH_CTL1	0xc8250
+#define   BLM_PCH_PWM_ENABLE			(1 << 31)
+#define   BLM_PCH_OVERRIDE_ENABLE		(1 << 30)
+#define   BLM_PCH_POLARITY			(1 << 29)
+#define BLC_PWM_PCH_CTL2	0xc8254
+
+/* digital port hotplug */
+#define PCH_PORT_HOTPLUG        0xc4030		/* SHOTPLUG_CTL */
+#define PORTD_HOTPLUG_ENABLE            (1 << 20)
+#define PORTD_PULSE_DURATION_2ms        (0)
+#define PORTD_PULSE_DURATION_4_5ms      (1 << 18)
+#define PORTD_PULSE_DURATION_6ms        (2 << 18)
+#define PORTD_PULSE_DURATION_100ms      (3 << 18)
+#define PORTD_PULSE_DURATION_MASK	(3 << 18)
+#define PORTD_HOTPLUG_NO_DETECT         (0)
+#define PORTD_HOTPLUG_SHORT_DETECT      (1 << 16)
+#define PORTD_HOTPLUG_LONG_DETECT       (1 << 17)
+#define PORTC_HOTPLUG_ENABLE            (1 << 12)
+#define PORTC_PULSE_DURATION_2ms        (0)
+#define PORTC_PULSE_DURATION_4_5ms      (1 << 10)
+#define PORTC_PULSE_DURATION_6ms        (2 << 10)
+#define PORTC_PULSE_DURATION_100ms      (3 << 10)
+#define PORTC_PULSE_DURATION_MASK	(3 << 10)
+#define PORTC_HOTPLUG_NO_DETECT         (0)
+#define PORTC_HOTPLUG_SHORT_DETECT      (1 << 8)
+#define PORTC_HOTPLUG_LONG_DETECT       (1 << 9)
+#define PORTB_HOTPLUG_ENABLE            (1 << 4)
+#define PORTB_PULSE_DURATION_2ms        (0)
+#define PORTB_PULSE_DURATION_4_5ms      (1 << 2)
+#define PORTB_PULSE_DURATION_6ms        (2 << 2)
+#define PORTB_PULSE_DURATION_100ms      (3 << 2)
+#define PORTB_PULSE_DURATION_MASK	(3 << 2)
+#define PORTB_HOTPLUG_NO_DETECT         (0)
+#define PORTB_HOTPLUG_SHORT_DETECT      (1 << 0)
+#define PORTB_HOTPLUG_LONG_DETECT       (1 << 1)
+
+#define PCH_GPIOA               0xc5010
+#define PCH_GPIOB               0xc5014
+#define PCH_GPIOC               0xc5018
+#define PCH_GPIOD               0xc501c
+#define PCH_GPIOE               0xc5020
+#define PCH_GPIOF               0xc5024
+
+#define PCH_GMBUS0		0xc5100
+#define PCH_GMBUS1		0xc5104
+#define PCH_GMBUS2		0xc5108
+#define PCH_GMBUS3		0xc510c
+#define PCH_GMBUS4		0xc5110
+#define PCH_GMBUS5		0xc5120
+
+#define _PCH_DPLL_A              0xc6014
+#define _PCH_DPLL_B              0xc6018
+#define _PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
+
+#define _PCH_FPA0                0xc6040
+#define  FP_CB_TUNE		(0x3<<22)
+#define _PCH_FPA1                0xc6044
+#define _PCH_FPB0                0xc6048
+#define _PCH_FPB1                0xc604c
+#define _PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
+#define _PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
+
+#define PCH_DPLL_TEST           0xc606c
+
+#define PCH_DREF_CONTROL        0xC6200
+#define  DREF_CONTROL_MASK      0x7fc3
+#define  DREF_CPU_SOURCE_OUTPUT_DISABLE         (0<<13)
+#define  DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD      (2<<13)
+#define  DREF_CPU_SOURCE_OUTPUT_NONSPREAD       (3<<13)
+#define  DREF_CPU_SOURCE_OUTPUT_MASK		(3<<13)
+#define  DREF_SSC_SOURCE_DISABLE                (0<<11)
+#define  DREF_SSC_SOURCE_ENABLE                 (2<<11)
+#define  DREF_SSC_SOURCE_MASK			(3<<11)
+#define  DREF_NONSPREAD_SOURCE_DISABLE          (0<<9)
+#define  DREF_NONSPREAD_CK505_ENABLE		(1<<9)
+#define  DREF_NONSPREAD_SOURCE_ENABLE           (2<<9)
+#define  DREF_NONSPREAD_SOURCE_MASK		(3<<9)
+#define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0<<7)
+#define  DREF_SUPERSPREAD_SOURCE_ENABLE         (2<<7)
+#define  DREF_SUPERSPREAD_SOURCE_MASK		(3<<7)
+#define  DREF_SSC4_DOWNSPREAD                   (0<<6)
+#define  DREF_SSC4_CENTERSPREAD                 (1<<6)
+#define  DREF_SSC1_DISABLE                      (0<<1)
+#define  DREF_SSC1_ENABLE                       (1<<1)
+#define  DREF_SSC4_DISABLE                      (0)
+#define  DREF_SSC4_ENABLE                       (1)
+
+#define PCH_RAWCLK_FREQ         0xc6204
+#define  FDL_TP1_TIMER_SHIFT    12
+#define  FDL_TP1_TIMER_MASK     (3<<12)
+#define  FDL_TP2_TIMER_SHIFT    10
+#define  FDL_TP2_TIMER_MASK     (3<<10)
+#define  RAWCLK_FREQ_MASK       0x3ff
+
+#define PCH_DPLL_TMR_CFG        0xc6208
+
+#define PCH_SSC4_PARMS          0xc6210
+#define PCH_SSC4_AUX_PARMS      0xc6214
+
+#define PCH_DPLL_SEL		0xc7000
+#define  TRANSA_DPLL_ENABLE	(1<<3)
+#define	 TRANSA_DPLLB_SEL	(1<<0)
+#define	 TRANSA_DPLLA_SEL	0
+#define  TRANSB_DPLL_ENABLE	(1<<7)
+#define	 TRANSB_DPLLB_SEL	(1<<4)
+#define	 TRANSB_DPLLA_SEL	(0)
+#define  TRANSC_DPLL_ENABLE	(1<<11)
+#define	 TRANSC_DPLLB_SEL	(1<<8)
+#define	 TRANSC_DPLLA_SEL	(0)
+
+/* transcoder */
+
+#define _TRANS_HTOTAL_A          0xe0000
+#define  TRANS_HTOTAL_SHIFT     16
+#define  TRANS_HACTIVE_SHIFT    0
+#define _TRANS_HBLANK_A          0xe0004
+#define  TRANS_HBLANK_END_SHIFT 16
+#define  TRANS_HBLANK_START_SHIFT 0
+#define _TRANS_HSYNC_A           0xe0008
+#define  TRANS_HSYNC_END_SHIFT  16
+#define  TRANS_HSYNC_START_SHIFT 0
+#define _TRANS_VTOTAL_A          0xe000c
+#define  TRANS_VTOTAL_SHIFT     16
+#define  TRANS_VACTIVE_SHIFT    0
+#define _TRANS_VBLANK_A          0xe0010
+#define  TRANS_VBLANK_END_SHIFT 16
+#define  TRANS_VBLANK_START_SHIFT 0
+#define _TRANS_VSYNC_A           0xe0014
+#define  TRANS_VSYNC_END_SHIFT  16
+#define  TRANS_VSYNC_START_SHIFT 0
+#define _TRANS_VSYNCSHIFT_A	0xe0028
+
+#define _TRANSA_DATA_M1          0xe0030
+#define _TRANSA_DATA_N1          0xe0034
+#define _TRANSA_DATA_M2          0xe0038
+#define _TRANSA_DATA_N2          0xe003c
+#define _TRANSA_DP_LINK_M1       0xe0040
+#define _TRANSA_DP_LINK_N1       0xe0044
+#define _TRANSA_DP_LINK_M2       0xe0048
+#define _TRANSA_DP_LINK_N2       0xe004c
+
+/* Per-transcoder DIP controls */
+
+#define _VIDEO_DIP_CTL_A         0xe0200
+#define _VIDEO_DIP_DATA_A        0xe0208
+#define _VIDEO_DIP_GCP_A         0xe0210
+
+#define _VIDEO_DIP_CTL_B         0xe1200
+#define _VIDEO_DIP_DATA_B        0xe1208
+#define _VIDEO_DIP_GCP_B         0xe1210
+
+#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
+#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
+#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
+
+#define VLV_VIDEO_DIP_CTL_A		0x60200
+#define VLV_VIDEO_DIP_DATA_A		0x60208
+#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A	0x60210
+
+#define VLV_VIDEO_DIP_CTL_B		0x61170
+#define VLV_VIDEO_DIP_DATA_B		0x61174
+#define VLV_VIDEO_DIP_GDCP_PAYLOAD_B	0x61178
+
+#define VLV_TVIDEO_DIP_CTL(pipe) \
+	 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
+#define VLV_TVIDEO_DIP_DATA(pipe) \
+	 _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B)
+#define VLV_TVIDEO_DIP_GCP(pipe) \
+	_PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
+
+/* vlv has 2 sets of panel control regs. */
+#define PIPEA_PP_STATUS         0x61200
+#define PIPEA_PP_CONTROL        0x61204
+#define PIPEA_PP_ON_DELAYS      0x61208
+#define PIPEA_PP_OFF_DELAYS     0x6120c
+#define PIPEA_PP_DIVISOR        0x61210
+
+#define PIPEB_PP_STATUS         0x61300
+#define PIPEB_PP_CONTROL        0x61304
+#define PIPEB_PP_ON_DELAYS      0x61308
+#define PIPEB_PP_OFF_DELAYS     0x6130c
+#define PIPEB_PP_DIVISOR        0x61310
+
+#define PCH_PP_STATUS		0xc7200
+#define PCH_PP_CONTROL		0xc7204
+#define  PANEL_UNLOCK_REGS	(0xabcd << 16)
+#define  PANEL_UNLOCK_MASK	(0xffff << 16)
+#define  EDP_FORCE_VDD		(1 << 3)
+#define  EDP_BLC_ENABLE		(1 << 2)
+#define  PANEL_POWER_RESET	(1 << 1)
+#define  PANEL_POWER_OFF	(0 << 0)
+#define  PANEL_POWER_ON		(1 << 0)
+#define PCH_PP_ON_DELAYS	0xc7208
+#define  PANEL_PORT_SELECT_MASK	(3 << 30)
+#define  PANEL_PORT_SELECT_LVDS	(0 << 30)
+#define  PANEL_PORT_SELECT_DPA	(1 << 30)
+#define  EDP_PANEL		(1 << 30)
+#define  PANEL_PORT_SELECT_DPC	(2 << 30)
+#define  PANEL_PORT_SELECT_DPD	(3 << 30)
+#define  PANEL_POWER_UP_DELAY_MASK	(0x1fff0000)
+#define  PANEL_POWER_UP_DELAY_SHIFT	16
+#define  PANEL_LIGHT_ON_DELAY_MASK	(0x1fff)
+#define  PANEL_LIGHT_ON_DELAY_SHIFT	0
+
+#define PCH_PP_OFF_DELAYS	0xc720c
+#define  PANEL_POWER_PORT_SELECT_MASK	(0x3 << 30)
+#define  PANEL_POWER_PORT_LVDS		(0 << 30)
+#define  PANEL_POWER_PORT_DP_A		(1 << 30)
+#define  PANEL_POWER_PORT_DP_C		(2 << 30)
+#define  PANEL_POWER_PORT_DP_D		(3 << 30)
+#define  PANEL_POWER_DOWN_DELAY_MASK	(0x1fff0000)
+#define  PANEL_POWER_DOWN_DELAY_SHIFT	16
+#define  PANEL_LIGHT_OFF_DELAY_MASK	(0x1fff)
+#define  PANEL_LIGHT_OFF_DELAY_SHIFT	0
+
+#define PCH_PP_DIVISOR		0xc7210
+#define  PP_REFERENCE_DIVIDER_MASK	(0xffffff00)
+#define  PP_REFERENCE_DIVIDER_SHIFT	8
+#define  PANEL_POWER_CYCLE_DELAY_MASK	(0x1f)
+#define  PANEL_POWER_CYCLE_DELAY_SHIFT	0
+
+#define PCH_DP_B		0xe4100
+#define PCH_DPB_AUX_CH_CTL	0xe4110
+#define PCH_DPB_AUX_CH_DATA1	0xe4114
+#define PCH_DPB_AUX_CH_DATA2	0xe4118
+#define PCH_DPB_AUX_CH_DATA3	0xe411c
+#define PCH_DPB_AUX_CH_DATA4	0xe4120
+#define PCH_DPB_AUX_CH_DATA5	0xe4124
+
+#define PCH_DP_C		0xe4200
+#define PCH_DPC_AUX_CH_CTL	0xe4210
+#define PCH_DPC_AUX_CH_DATA1	0xe4214
+#define PCH_DPC_AUX_CH_DATA2	0xe4218
+#define PCH_DPC_AUX_CH_DATA3	0xe421c
+#define PCH_DPC_AUX_CH_DATA4	0xe4220
+#define PCH_DPC_AUX_CH_DATA5	0xe4224
+
+#define PCH_DP_D		0xe4300
+#define PCH_DPD_AUX_CH_CTL	0xe4310
+#define PCH_DPD_AUX_CH_DATA1	0xe4314
+#define PCH_DPD_AUX_CH_DATA2	0xe4318
+#define PCH_DPD_AUX_CH_DATA3	0xe431c
+#define PCH_DPD_AUX_CH_DATA4	0xe4320
+#define PCH_DPD_AUX_CH_DATA5	0xe4324
+
+#endif /* _I915_REG_H_ */