spi: ich: Some clean up

This cleans up the ich spi driver a little bit:
- Remove struct ich_spi_slave that is not referenced anywhere
- Remove ending period in some comments
- Move struct ich_spi_platdata and struct ich_spi_priv to ich.h
- Add #ifndef _ICH_H_ .. in ich.h

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jteki@openedev.com>

2 files changed, 47 insertions, 47 deletions

diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index e543b8f0cf4..22b5419368f 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -5,6 +5,7 @@
  *
  * This file is derived from the flashrom project.
  */
+
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
@@ -17,41 +18,12 @@
 
 #include "ich.h"
 
-#define SPI_OPCODE_WREN      0x06
-#define SPI_OPCODE_FAST_READ 0x0b
-
 #ifdef DEBUG_TRACE
 #define debug_trace(fmt, args...) debug(fmt, ##args)
 #else
 #define debug_trace(x, args...)
 #endif
 
-struct ich_spi_platdata {
-	enum pch_version ich_version;	/* Controller version, 7 or 9 */
-};
-
-struct ich_spi_priv {
-	int ichspi_lock;
-	int locked;
-	int opmenu;
-	int menubytes;
-	void *base;		/* Base of register set */
-	int preop;
-	int optype;
-	int addr;
-	int data;
-	unsigned databytes;
-	int status;
-	int control;
-	int bbar;
-	int bcr;
-	uint32_t *pr;		/* only for ich9 */
-	int speed;		/* pointer to speed control */
-	ulong max_speed;	/* Maximum bus speed in MHz */
-	ulong cur_speed;	/* Current bus speed */
-	struct spi_trans trans;	/* current transaction in progress */
-};
-
 static u8 ich_readb(struct ich_spi_priv *priv, int reg)
 {
 	u8 value = readb(priv->base + reg);
@@ -217,7 +189,7 @@ static void spi_setup_type(struct spi_trans *trans, int data_bytes)
 {
 	trans->type = 0xFF;
 
-	/* Try to guess spi type from read/write sizes. */
+	/* Try to guess spi type from read/write sizes */
 	if (trans->bytesin == 0) {
 		if (trans->bytesout + data_bytes > 4)
 			/*
@@ -301,7 +273,7 @@ static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans)
 
 static int spi_setup_offset(struct spi_trans *trans)
 {
-	/* Separate the SPI address and data. */
+	/* Separate the SPI address and data */
 	switch (trans->type) {
 	case SPI_OPCODE_TYPE_READ_NO_ADDRESS:
 	case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS:
@@ -410,7 +382,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
 	trans->in = din;
 	trans->bytesin = din ? bytes : 0;
 
-	/* There has to always at least be an opcode. */
+	/* There has to always at least be an opcode */
 	if (!trans->bytesout) {
 		debug("ICH SPI: No opcode for transfer\n");
 		return -EPROTO;
@@ -541,7 +513,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
 		/* write it */
 		ich_writew(ctlr, control, ctlr->control);
 
-		/* Wait for Cycle Done Status or Flash Cycle Error. */
+		/* Wait for Cycle Done Status or Flash Cycle Error */
 		status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
 		if (status < 0)
 			return status;
diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h
index 1419b23e119..6344e80d637 100644
--- a/drivers/spi/ich.h
+++ b/drivers/spi/ich.h
@@ -6,6 +6,9 @@
  * This file is derived from the flashrom project.
  */
 
+#ifndef _ICH_H_
+#define _ICH_H_
+
 struct ich7_spi_regs {
 	uint16_t spis;
 	uint16_t spic;
@@ -19,34 +22,34 @@ struct ich7_spi_regs {
 } __packed;
 
 struct ich9_spi_regs {
-	uint32_t bfpr;			/* 0x00 */
+	uint32_t bfpr;		/* 0x00 */
 	uint16_t hsfs;
 	uint16_t hsfc;
 	uint32_t faddr;
 	uint32_t _reserved0;
-	uint32_t fdata[16];		/* 0x10 */
-	uint32_t frap;			/* 0x50 */
+	uint32_t fdata[16];	/* 0x10 */
+	uint32_t frap;		/* 0x50 */
 	uint32_t freg[5];
 	uint32_t _reserved1[3];
-	uint32_t pr[5];			/* 0x74 */
+	uint32_t pr[5];		/* 0x74 */
 	uint32_t _reserved2[2];
-	uint8_t ssfs;			/* 0x90 */
+	uint8_t ssfs;		/* 0x90 */
 	uint8_t ssfc[3];
-	uint16_t preop;			/* 0x94 */
+	uint16_t preop;		/* 0x94 */
 	uint16_t optype;
-	uint8_t opmenu[8];		/* 0x98 */
+	uint8_t opmenu[8];	/* 0x98 */
 	uint32_t bbar;
 	uint8_t _reserved3[12];
-	uint32_t fdoc;			/* 0xb0 */
+	uint32_t fdoc;		/* 0xb0 */
 	uint32_t fdod;
 	uint8_t _reserved4[8];
-	uint32_t afc;			/* 0xc0 */
+	uint32_t afc;		/* 0xc0 */
 	uint32_t lvscc;
 	uint32_t uvscc;
 	uint8_t _reserved5[4];
-	uint32_t fpb;			/* 0xd0 */
+	uint32_t fpb;		/* 0xd0 */
 	uint8_t _reserved6[28];
-	uint32_t srdl;			/* 0xf0 */
+	uint32_t srdl;		/* 0xf0 */
 	uint32_t srdc;
 	uint32_t scs;
 	uint32_t bcr;
@@ -121,8 +124,33 @@ struct spi_trans {
 	uint32_t offset;
 };
 
-struct ich_spi_slave {
-	struct spi_slave slave;
+#define SPI_OPCODE_WREN		0x06
+#define SPI_OPCODE_FAST_READ	0x0b
+
+struct ich_spi_platdata {
+	enum pch_version ich_version;	/* Controller version, 7 or 9 */
+};
+
+struct ich_spi_priv {
+	int ichspi_lock;
+	int locked;
+	int opmenu;
+	int menubytes;
+	void *base;		/* Base of register set */
+	int preop;
+	int optype;
+	int addr;
+	int data;
+	unsigned databytes;
+	int status;
+	int control;
+	int bbar;
+	int bcr;
+	uint32_t *pr;		/* only for ich9 */
+	int speed;		/* pointer to speed control */
+	ulong max_speed;	/* Maximum bus speed in MHz */
+	ulong cur_speed;	/* Current bus speed */
 	struct spi_trans trans;	/* current transaction in progress */
-	int speed;		/* SPI speed in Hz */
 };
+
+#endif /* _ICH_H_ */