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authorStefan Roese2015-06-08 17:01:26 +0200
committerLuka Perkov2015-07-23 10:39:25 +0200
commitad6ac7aa0002915bf2a285c85a8e96a0f8c2b6aa (patch)
tree8ceed19dd62a69a713bbb152e99b40c46f52a154 /drivers
parentf1df9364459425abba75488a148ddd98fabf40d7 (diff)
arm: mvebu: a38x: Use correct PEX register access macros
Remove the incorrect PEX macros from the DDR header. And insert the correct ones in ctrl_pex.h instead. Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/ddr/marvell/a38x/ddr3_hws_hw_training_def.h5
1 files changed, 0 insertions, 5 deletions
diff --git a/drivers/ddr/marvell/a38x/ddr3_hws_hw_training_def.h b/drivers/ddr/marvell/a38x/ddr3_hws_hw_training_def.h
index 02d8c610cee..7500a72403d 100644
--- a/drivers/ddr/marvell/a38x/ddr3_hws_hw_training_def.h
+++ b/drivers/ddr/marvell/a38x/ddr3_hws_hw_training_def.h
@@ -421,11 +421,6 @@
#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS)
/* Power Management Clock Gating Control Register */
-#define MV_PEX_IF_REGS_OFFSET(pex_if) \
- (pex_if < 8 ? (0x40000 + ((pex_if) / 4) * 0x40000 + \
- ((pex_if) % 4) * 0x4000) : \
- (0x42000 + ((pex_if) % 8) * 0x40000))
-#define PEX_IF_REGS_BASE(unit) (MV_PEX_IF_REGS_OFFSET(unit))
#define POWER_MNG_CTRL_REG 0x18220
#define PEX_DEVICE_AND_VENDOR_ID 0x000
#define PEX_CFG_DIRECT_ACCESS(if, reg) (PEX_IF_REGS_BASE(if) + (reg))