diff options
| author | Marek Vasut | 2023-09-17 16:11:39 +0200 |
|---|---|---|
| committer | Marek Vasut | 2023-10-01 00:08:28 +0200 |
| commit | c94f98052494c150346790e099312dac4ff05fe7 (patch) | |
| tree | 103489cd46e37d08e84485732e6cb18349982e24 /drivers | |
| parent | 635811a106f6b0a5ffdd398d08f04377f4f88942 (diff) | |
clk: renesas: Synchronize R8A774B1 RZ/G2N clock tables with Linux 6.5.3
Synchronize R8A774B1 RZ/G2N clock tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/renesas/r8a774b1-cpg-mssr.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c b/drivers/clk/renesas/r8a774b1-cpg-mssr.c index b5927c7892c..60f4f1da519 100644 --- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c @@ -46,7 +46,7 @@ enum clk_ids { MOD_CLK_BASE }; -static const struct cpg_core_clk r8a774b1_core_clks[] = { +static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), DEF_INPUT("extalr", CLK_EXTALR), @@ -118,7 +118,7 @@ static const struct cpg_core_clk r8a774b1_core_clks[] = { DEF_BASE("r", R8A774B1_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), }; -static const struct mssr_mod_clk r8a774b1_mod_clks[] = { +static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = { DEF_MOD("tmu4", 121, R8A774B1_CLK_S0D6), DEF_MOD("tmu3", 122, R8A774B1_CLK_S3D2), DEF_MOD("tmu2", 123, R8A774B1_CLK_S3D2), @@ -272,7 +272,7 @@ static const struct mssr_mod_clk r8a774b1_mod_clks[] = { (((md) & BIT(19)) >> 18) | \ (((md) & BIT(17)) >> 17)) -static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = { +static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */ { 1, 192, 1, 192, 1, 16, }, { 1, 192, 1, 128, 1, 16, }, |