diff options
| author | Caleb Connolly | 2024-03-01 15:00:24 +0000 |
|---|---|---|
| committer | Caleb Connolly | 2024-03-01 15:08:59 +0000 |
| commit | cbf3152f6afff25c25aa69ae06488671ca0aa765 (patch) | |
| tree | 95a75f9a43aac12cef86a8972260fc27a072cb25 /drivers | |
| parent | f70ab46df3c2768002fdfc0fca9652af732cd619 (diff) | |
clk/qcom: apq8016: allow apq8016_clk_init_uart() to be called externally
When U-Boot as running as the first stage bootloader on MSM8916 devices,
early debug UART requires turning on the clocks (for some reason the
pre-loader turns them off?!).
To simplify developing for this platform, allow the
apq8016_clk_init_uart() function to be called externally. Developers can
call this from the serial_msm debug uart driver to configure the clocks
before the driver model is available.
As it is only possible to enable early debug UART in custom builds of
U-Boot, this solution at least gives developers the option.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/qcom/clock-apq8016.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index 9de0ad5ed32..e6647f7c41d 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -103,20 +103,20 @@ static const struct bcr_regs uart2_regs = { }; /* UART: 115200 */ -static int clk_init_uart(struct msm_clk_priv *priv) +int apq8016_clk_init_uart(phys_addr_t base) { /* Enable AHB clock */ - clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk); + clk_enable_vote_clk(base, &gcc_blsp1_ahb_clk); /* 7372800 uart block clock @ GPLL0 */ - clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 144, 15625, + clk_rcg_set_rate_mnd(base, &uart2_regs, 1, 144, 15625, CFG_CLK_SRC_GPLL0, 16); /* Vote for gpll0 clock */ - clk_enable_gpll0(priv->base, &gpll0_vote_clk); + clk_enable_gpll0(base, &gpll0_vote_clk); /* Enable core clk */ - clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR); + clk_enable_cbc(base + BLSP1_UART2_APPS_CBCR); return 0; } @@ -133,7 +133,7 @@ static ulong apq8016_clk_set_rate(struct clk *clk, ulong rate) return clk_init_sdc(priv, 1, rate); break; case GCC_BLSP1_UART2_APPS_CLK: /* UART2 */ - return clk_init_uart(priv); + return apq8016_clk_init_uart(priv->base); break; default: return 0; |