diff options
author | Philipp Tomsich | 2018-01-08 14:00:27 +0100 |
---|---|---|
committer | Philipp Tomsich | 2018-01-28 17:12:36 +0100 |
commit | d2f1f1abafbedd3580334f2564bfea918e49522d (patch) | |
tree | 3e771d6dcb49fc9866711f401fcfd99ce5bbab74 /drivers | |
parent | f4fcba5c5baaaa9d477d753f97124efdb8e45893 (diff) |
rockchip: clk: rk3399: accept all assigned-clocks from the 'cru'-node
The RK3399 CRU-node assigns rates to a number of clocks that are not
implemented in the RK3399 clock-driver (but which have been
sufficiently initialised from rkclk_init()): for these clocks, we
simply ignore the set_rate() operation and return 0 to signal success.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: David Wu <david.wu@rock-chips.com>
Series-changes: 2
- Fixed David's email address.
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/clk/rockchip/clk_rk3399.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index e791936dbb1..e431ec8a51d 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -883,6 +883,24 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) switch (clk->id) { case 0 ... 63: return 0; + + case ACLK_PERIHP: + case HCLK_PERIHP: + case PCLK_PERIHP: + return 0; + + case ACLK_PERILP0: + case HCLK_PERILP0: + case PCLK_PERILP0: + return 0; + + case ACLK_CCI: + return 0; + + case HCLK_PERILP1: + case PCLK_PERILP1: + return 0; + case HCLK_SDMMC: case SCLK_SDMMC: case SCLK_EMMC: |