diff options
| author | Tom Rini | 2015-04-20 17:12:45 -0400 |
|---|---|---|
| committer | Tom Rini | 2015-04-20 17:12:45 -0400 |
| commit | dd9958a3f4460681bed6a6c6dc99ba47849e3c9b (patch) | |
| tree | d1ddbee015b8b3c68d4f0df38dd927e2b283f4dc /drivers | |
| parent | 1733259d25015c28c47990ec11af99b3f62f811c (diff) | |
| parent | 221fbd229c0981feca0c6ca99fff3315197d0f86 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/ddr/fsl/ctrl_regs.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 690e73dacf6..391925751a5 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -1747,9 +1747,17 @@ static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) { unsigned int clk_adjust; /* Clock adjust */ + unsigned int ss_en = 0; /* Source synchronous enable */ +#if defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) + /* Per FSL Application Note: AN2805 */ + ss_en = 1; +#endif clk_adjust = popts->clk_adjust; - ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23; + ddr->ddr_sdram_clk_cntl = (0 + | ((ss_en & 0x1) << 31) + | ((clk_adjust & 0xF) << 23) + ); debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl); } |