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authorChris Morgan2021-08-05 11:48:47 -0500
committerKever Yang2021-10-15 20:56:09 +0800
commitef120e0b30d05ca444753e995bcfc4e4333261f1 (patch)
tree04e6941b8c5c203a35aa13bd702aedc6bbe1b7d5 /drivers
parent2d34be0a9e12cf050de39ad95375213f48e685bd (diff)
rockchip: px30: add support for setting cpll clock
Starting with commit 92f1e9a4b31c ("clk: Detect failure to set defaults") the clk driver for the PX30 for the Odroid Go Advance would no longer probe correctly, because setting the cpll and gpu clocks are not supported with the clk_px30 U-Boot driver. This adds support for setting the cpll clock to the clk_px30 driver. Another patch will update the U-Boot specific device-tree to remove the GPU clock which is not used by U-Boot. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/clk/rockchip/clk_px30.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c
index 617ce0dce5a..ea874e3f4b9 100644
--- a/drivers/clk/rockchip/clk_px30.c
+++ b/drivers/clk/rockchip/clk_px30.c
@@ -1291,6 +1291,9 @@ static ulong px30_clk_set_rate(struct clk *clk, ulong rate)
case PLL_NPLL:
ret = px30_clk_set_pll_rate(priv, NPLL, rate);
break;
+ case PLL_CPLL:
+ ret = px30_clk_set_pll_rate(priv, CPLL, rate);
+ break;
case ARMCLK:
ret = px30_armclk_set_clk(priv, rate);
break;