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author | Tom Rini | 2024-02-29 12:33:36 -0500 |
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committer | Tom Rini | 2024-02-29 12:33:36 -0500 |
commit | dbe9334e5125efcf8a825e7c5c924e2780e609e3 (patch) | |
tree | 76d7c01587afe238d2127a7562ca256fe9c87a9f /dts/upstream/Bindings/openrisc | |
parent | ea3348ebc215d2a9d6dd14f40fb7e8c86dc45e4a (diff) | |
parent | 53633a893a06bd5a0c807287d9cc29337806eaf7 (diff) |
Merge commit '53633a893a06bd5a0c807287d9cc29337806eaf7' as 'dts/upstream'
Diffstat (limited to 'dts/upstream/Bindings/openrisc')
-rw-r--r-- | dts/upstream/Bindings/openrisc/opencores/or1ksim.txt | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/dts/upstream/Bindings/openrisc/opencores/or1ksim.txt b/dts/upstream/Bindings/openrisc/opencores/or1ksim.txt new file mode 100644 index 00000000000..4950c794ecb --- /dev/null +++ b/dts/upstream/Bindings/openrisc/opencores/or1ksim.txt @@ -0,0 +1,39 @@ +OpenRISC Generic SoC +==================== + +Boards and FPGA SoC's which support the OpenRISC standard platform. The +platform essentially follows the conventions of the OpenRISC architecture +specification, however some aspects, such as the boot protocol have been defined +by the Linux port. + +Required properties +------------------- + - compatible: Must include "opencores,or1ksim" + +CPU nodes: +---------- +A "cpus" node is required. Required properties: + - #address-cells: Must be 1. + - #size-cells: Must be 0. +A CPU sub-node is also required for at least CPU 0. Since the topology may +be probed via CPS, it is not necessary to specify secondary CPUs. Required +properties: + - compatible: Must be "opencores,or1200-rtlsvn481". + - reg: CPU number. + - clock-frequency: The CPU clock frequency in Hz. +Example: + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "opencores,or1200-rtlsvn481"; + reg = <0>; + clock-frequency = <20000000>; + }; + }; + + +Boot protocol +------------- +The bootloader may pass the following arguments to the kernel: + - r3: address of a flattened device-tree blob or 0x0. |