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authorTom Rini2024-07-20 11:15:22 -0600
committerTom Rini2024-07-20 11:15:22 -0600
commit5024a96db8ea6ff2e814f4599af9e5faf09296b7 (patch)
treebc0d02e7022f796932c5d24c9d6b61b166488efa /dts/upstream/include/dt-bindings/clock/r9a07g054-cpg.h
parentd353e30ef3610c01b031dc9ada53701b13d473d4 (diff)
parent762f85bb2e36762ee4d7395002b8181905aec690 (diff)
Subtree merge tag 'v6.10-dts' of devicetree-rebasing repo [1] into dts/upstreamHEADmaster
[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/
Diffstat (limited to 'dts/upstream/include/dt-bindings/clock/r9a07g054-cpg.h')
-rw-r--r--dts/upstream/include/dt-bindings/clock/r9a07g054-cpg.h58
1 files changed, 58 insertions, 0 deletions
diff --git a/dts/upstream/include/dt-bindings/clock/r9a07g054-cpg.h b/dts/upstream/include/dt-bindings/clock/r9a07g054-cpg.h
index 43f4dbda872..2c99f89397c 100644
--- a/dts/upstream/include/dt-bindings/clock/r9a07g054-cpg.h
+++ b/dts/upstream/include/dt-bindings/clock/r9a07g054-cpg.h
@@ -226,4 +226,62 @@
#define R9A07G054_TSU_PRESETN 83
#define R9A07G054_STPAI_ARESETN 84
+/* Power domain IDs. */
+#define R9A07G054_PD_ALWAYS_ON 0
+#define R9A07G054_PD_GIC 1
+#define R9A07G054_PD_IA55 2
+#define R9A07G054_PD_MHU 3
+#define R9A07G054_PD_CORESIGHT 4
+#define R9A07G054_PD_SYC 5
+#define R9A07G054_PD_DMAC 6
+#define R9A07G054_PD_GTM0 7
+#define R9A07G054_PD_GTM1 8
+#define R9A07G054_PD_GTM2 9
+#define R9A07G054_PD_MTU 10
+#define R9A07G054_PD_POE3 11
+#define R9A07G054_PD_GPT 12
+#define R9A07G054_PD_POEGA 13
+#define R9A07G054_PD_POEGB 14
+#define R9A07G054_PD_POEGC 15
+#define R9A07G054_PD_POEGD 16
+#define R9A07G054_PD_WDT0 17
+#define R9A07G054_PD_WDT1 18
+#define R9A07G054_PD_SPI 19
+#define R9A07G054_PD_SDHI0 20
+#define R9A07G054_PD_SDHI1 21
+#define R9A07G054_PD_3DGE 22
+#define R9A07G054_PD_ISU 23
+#define R9A07G054_PD_VCPL4 24
+#define R9A07G054_PD_CRU 25
+#define R9A07G054_PD_MIPI_DSI 26
+#define R9A07G054_PD_LCDC 27
+#define R9A07G054_PD_SSI0 28
+#define R9A07G054_PD_SSI1 29
+#define R9A07G054_PD_SSI2 30
+#define R9A07G054_PD_SSI3 31
+#define R9A07G054_PD_SRC 32
+#define R9A07G054_PD_USB0 33
+#define R9A07G054_PD_USB1 34
+#define R9A07G054_PD_USB_PHY 35
+#define R9A07G054_PD_ETHER0 36
+#define R9A07G054_PD_ETHER1 37
+#define R9A07G054_PD_I2C0 38
+#define R9A07G054_PD_I2C1 39
+#define R9A07G054_PD_I2C2 40
+#define R9A07G054_PD_I2C3 41
+#define R9A07G054_PD_SCIF0 42
+#define R9A07G054_PD_SCIF1 43
+#define R9A07G054_PD_SCIF2 44
+#define R9A07G054_PD_SCIF3 45
+#define R9A07G054_PD_SCIF4 46
+#define R9A07G054_PD_SCI0 47
+#define R9A07G054_PD_SCI1 48
+#define R9A07G054_PD_IRDA 49
+#define R9A07G054_PD_RSPI0 50
+#define R9A07G054_PD_RSPI1 51
+#define R9A07G054_PD_RSPI2 52
+#define R9A07G054_PD_CANFD 53
+#define R9A07G054_PD_ADC 54
+#define R9A07G054_PD_TSU 55
+
#endif /* __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ */