diff options
| author | Tom Rini | 2024-07-20 11:15:22 -0600 |
|---|---|---|
| committer | Tom Rini | 2024-07-20 11:15:22 -0600 |
| commit | 5024a96db8ea6ff2e814f4599af9e5faf09296b7 (patch) | |
| tree | bc0d02e7022f796932c5d24c9d6b61b166488efa /dts/upstream/src/arm64/qcom/sm8450.dtsi | |
| parent | d353e30ef3610c01b031dc9ada53701b13d473d4 (diff) | |
| parent | 762f85bb2e36762ee4d7395002b8181905aec690 (diff) | |
[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/
Diffstat (limited to 'dts/upstream/src/arm64/qcom/sm8450.dtsi')
| -rw-r--r-- | dts/upstream/src/arm64/qcom/sm8450.dtsi | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/dts/upstream/src/arm64/qcom/sm8450.dtsi b/dts/upstream/src/arm64/qcom/sm8450.dtsi index 024d2653cc3..616461fcbab 100644 --- a/dts/upstream/src/arm64/qcom/sm8450.dtsi +++ b/dts/upstream/src/arm64/qcom/sm8450.dtsi @@ -1846,6 +1846,16 @@ pinctrl-0 = <&pcie0_default_state>; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -1963,6 +1973,16 @@ pinctrl-0 = <&pcie1_default_state>; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 { @@ -2355,6 +2375,7 @@ compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "sdsp"; + qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; @@ -2657,6 +2678,7 @@ compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "adsp"; + qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; @@ -2723,6 +2745,7 @@ compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "cdsp"; + qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; |