diff options
| author | Simon Glass | 2022-10-20 18:22:39 -0600 |
|---|---|---|
| committer | Tom Rini | 2022-10-31 11:01:31 -0400 |
| commit | 984639039f4cfe32ec2cc531d6ace05326ac49eb (patch) | |
| tree | 472bf7e47978335a73c5d6025d3b83b534f7192b /include/configs/T102xRDB.h | |
| parent | 6f38d91158e7e4199753b79e0a25c1a65175aba4 (diff) | |
Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASE
The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE
and this makes it imposible to use CONFIG_VAL().
Rename it to resolve this problem.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include/configs/T102xRDB.h')
| -rw-r--r-- | include/configs/T102xRDB.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index e0aa2b9598c..14f0ce60e29 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -86,7 +86,7 @@ #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) /* Set 1M boot space for PCIe boot */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc @@ -469,7 +469,7 @@ "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \ "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ "netdev=eth0\0" \ "tftpflash=tftpboot $loadaddr $uboot && " \ |