diff options
author | Sergey Lapin | 2011-06-09 05:45:31 +0000 |
---|---|---|
committer | Albert ARIBAUD | 2011-06-21 22:26:22 +0200 |
commit | 282e27c0b71a18654ae5f829f7b07d2f2f1fb4d6 (patch) | |
tree | 342f55cb0440b1bcb040715c0aa58cd81f7ac4e5 /include/configs/afeb9260.h | |
parent | 6c169c12d7782335be2f1d303622bcd0e1d00a02 (diff) |
Build fix/update of AFEB9260
Make AFEB9260 build again.
Based on fix for AT91SAM9260EK.
Signed-off-by: Sergey Lapin <slapin@ossfans.org>
Diffstat (limited to 'include/configs/afeb9260.h')
-rw-r--r-- | include/configs/afeb9260.h | 78 |
1 files changed, 41 insertions, 37 deletions
diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h index 36a2a461d16..2c2c0776d5a 100644 --- a/include/configs/afeb9260.h +++ b/include/configs/afeb9260.h @@ -25,17 +25,21 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91SAM9260 /* Atmel AT91SAM9260 SoC*/ +#include <asm/arch/hardware.h> -#define CONFIG_AT91_LEGACY +#define CONFIG_SYS_TEXT_BASE 0x21f00000 /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_MAIN_CLOCK 18429952 /* from 18.432 MHz crystal */ -#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_HZ 1000 -#define CONFIG_AT91SAM9260 1 /* It's an Atmel AT91SAM9260 SoC*/ -#define CONFIG_AFEB9260 1 /* on an AFEB9260 Board */ +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_AFEB9260 /* AFEB9260 Board */ #define CONFIG_ARCH_CPU_INIT -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 @@ -46,12 +50,14 @@ /* * Hardware drivers */ -#define CONFIG_AT91_GPIO 1 -#define CONFIG_ATMEL_USART 1 -#undef CONFIG_USART0 -#undef CONFIG_USART1 -#undef CONFIG_USART2 -#define CONFIG_USART3 1 /* USART 3 is DBGU */ +#define CONFIG_ATMEL_LEGACY +#define CONFIG_AT91_GPIO +#define CONFIG_AT91_PULLUP 1 + +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS +#define CONFIG_USART3 /* USART 3 is DBGU */ #define CONFIG_BOOTDELAY 3 @@ -74,20 +80,20 @@ #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_SOURCE -#define CONFIG_CMD_PING 1 -#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NAND 1 -#define CONFIG_CMD_USB 1 +#define CONFIG_CMD_NAND +#define CONFIG_CMD_USB /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI -#define CONFIG_HAS_DATAFLASH 1 +#define CONFIG_HAS_DATAFLASH #define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ @@ -100,8 +106,8 @@ #ifdef CONFIG_CMD_NAND #define CONFIG_NAND_ATMEL #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ @@ -112,37 +118,36 @@ #endif /* NOR flash - no real flash on this board */ -#define CONFIG_SYS_NO_FLASH 1 +#define CONFIG_SYS_NO_FLASH /* Ethernet */ -#define CONFIG_MACB 1 -#undef CONFIG_RMII /* We have full MII there */ -#define CONFIG_RESET_PHY_R 1 +#define CONFIG_MACB +#define CONFIG_RESET_PHY_R -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI #define CONFIG_NET_RETRY_COUNT 20 /* USB */ #define CONFIG_USB_ATMEL -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_USB_OHCI_NEW +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */ #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 -#define CONFIG_USB_STORAGE 1 +#define CONFIG_USB_STORAGE #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* load address */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END 0x21e00000 -#undef CONFIG_SYS_USE_DATAFLASH_CS0 -#define CONFIG_SYS_USE_DATAFLASH_CS1 1 -#undef CONFIG_SYS_USE_NANDFLASH +#define CONFIG_SYS_USE_DATAFLASH_CS1 +#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 -\ + GENERATED_GBL_DATA_SIZE) /* bootstrap + u-boot + env + linux in dataflash on CS1 */ -#define CONFIG_ENV_IS_IN_DATAFLASH 1 +#define CONFIG_ENV_IS_IN_DATAFLASH #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + 0x8400) #define CONFIG_ENV_OFFSET 0x4200 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + CONFIG_ENV_OFFSET) @@ -159,8 +164,8 @@ #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP 1 -#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING /* * Size of malloc() pool @@ -172,5 +177,4 @@ #ifdef CONFIG_USE_IRQ #error CONFIG_USE_IRQ not supported #endif - #endif |