diff options
| author | Tom Rini | 2015-05-22 17:23:15 -0400 |
|---|---|---|
| committer | Tom Rini | 2015-05-22 17:23:15 -0400 |
| commit | a84988c76d1dbca2dbe870d6b4f0ad398f287f85 (patch) | |
| tree | ac63bcd85d6cdcc73718ab1d9d6067917ed3e35d /include/configs/ls1021atwr.h | |
| parent | 133ebeabc22d9cff260c29af9783b714146121a7 (diff) | |
| parent | a88cc3bd90b05420a84ee360efa1133652dcac5c (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
Diffstat (limited to 'include/configs/ls1021atwr.h')
| -rw-r--r-- | include/configs/ls1021atwr.h | 25 |
1 files changed, 24 insertions, 1 deletions
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 729205f7129..8ea428e8982 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -35,6 +35,29 @@ #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 100000000 +#define DDR_SDRAM_CFG 0x470c0008 +#define DDR_CS0_BNDS 0x008000bf +#define DDR_CS0_CONFIG 0x80014302 +#define DDR_TIMING_CFG_0 0x50550004 +#define DDR_TIMING_CFG_1 0xbcb38c56 +#define DDR_TIMING_CFG_2 0x0040d120 +#define DDR_TIMING_CFG_3 0x010e1000 +#define DDR_TIMING_CFG_4 0x00000001 +#define DDR_TIMING_CFG_5 0x03401400 +#define DDR_SDRAM_CFG_2 0x00401010 +#define DDR_SDRAM_MODE 0x00061c60 +#define DDR_SDRAM_MODE_2 0x00180000 +#define DDR_SDRAM_INTERVAL 0x18600618 +#define DDR_DDR_WRLVL_CNTL 0x8655f605 +#define DDR_DDR_WRLVL_CNTL_2 0x05060607 +#define DDR_DDR_WRLVL_CNTL_3 0x05050505 +#define DDR_DDR_CDR1 0x80040000 +#define DDR_DDR_CDR2 0x00000001 +#define DDR_SDRAM_CLK_CNTL 0x02000000 +#define DDR_DDR_ZQ_CNTL 0x89080600 +#define DDR_CS0_CONFIG_2 0 +#define DDR_SDRAM_CFG_MEM_EN 0x80000000 + #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg #endif @@ -73,7 +96,7 @@ #endif #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0x67f80000 +#define CONFIG_SYS_TEXT_BASE 0x60100000 #endif #define CONFIG_NR_DRAM_BANKS 1 |