diff options
| author | Heiko Stuebner | 2019-07-16 22:17:13 +0200 |
|---|---|---|
| committer | Kever Yang | 2019-11-17 17:23:00 +0800 |
| commit | 46281a76bee3fdb18f75b4c71405ac5cacf1a64e (patch) | |
| tree | a69b9f27e568002947db35625b797ef5d452c59d /include/configs/px30_common.h | |
| parent | 22b7b860051d3f18cfd3bb9750b907174b3eee2b (diff) | |
rockchip: add core px30 headers
Add headers needed by the upcoming px30 support, including two
new dt-binding headers taken from the Linux kernel.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'include/configs/px30_common.h')
| -rw-r--r-- | include/configs/px30_common.h | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h new file mode 100644 index 00000000000..d6c70601dd0 --- /dev/null +++ b/include/configs/px30_common.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + */ + +#ifndef __CONFIG_PX30_COMMON_H +#define __CONFIG_PX30_COMMON_H + +#include "rockchip-common.h" + +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_ROCKCHIP_STIMER_BASE 0xff220020 +#define COUNTER_FREQUENCY 24000000 + +/* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */ +#define CONFIG_IRAM_BASE 0xff020000 + +#define CONFIG_SYS_INIT_SP_ADDR 0x00400000 +#define CONFIG_SYS_LOAD_ADDR 0x00800800 +#define CONFIG_SPL_STACK 0x00400000 +#define CONFIG_SPL_MAX_SIZE 0x20000 +#define CONFIG_SPL_BSS_START_ADDR 0x4000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x4000 +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +#define GICD_BASE 0xff131000 +#define GICC_BASE 0xff132000 + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +/* MMC/SD IP block */ +//#define CONFIG_BOUNCE_BUFFER + +#define CONFIG_SYS_SDRAM_BASE 0 +#define SDRAM_MAX_SIZE 0xff000000 +#define SDRAM_BANK_SIZE (2UL << 30) + +#ifndef CONFIG_SPL_BUILD + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00500000\0" \ + "pxefile_addr_r=0x00600000\0" \ + "fdt_addr_r=0x08300000\0" \ + "kernel_addr_r=0x00280000\0" \ + "kernel_addr_c=0x03e80000\0" \ + "ramdisk_addr_r=0x0a200000\0" + +#include <config_distro_bootcmd.h> +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "partitions=" PARTS_DEFAULT \ + ROCKCHIP_DEVICE_SETTINGS \ + BOOTENV + +#endif + +#endif |