diff options
| author | Tom Rini | 2022-11-12 17:36:51 -0500 |
|---|---|---|
| committer | Tom Rini | 2022-12-05 16:05:38 -0500 |
| commit | 4e5909450ec2acafb3d2e5b9714251ae67e0f0e0 (patch) | |
| tree | a109a38b3f6db435c193d1d0025ff32e90729ea9 /include/configs/smartweb.h | |
| parent | 0cd03259644dcb967fcd6b31c3a92984125a1fe3 (diff) | |
global: Move remaining CONFIG_SYS_NAND_* to CFG_SYS_NAND_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NAND
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include/configs/smartweb.h')
| -rw-r--r-- | include/configs/smartweb.h | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index 5460c12a17e..7c8f1676be2 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -54,11 +54,11 @@ */ /* NAND flash settings */ -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 +#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CFG_SYS_NAND_MASK_ALE (1 << 21) +#define CFG_SYS_NAND_MASK_CLE (1 << 22) +#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC13 /* serial console */ #define CONFIG_USART_BASE ATMEL_BASE_DBGU @@ -92,13 +92,13 @@ /* Defines for SPL */ -#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_SIZE SZ_512K +#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_ECCSIZE 256 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ +#define CFG_SYS_NAND_ECCSIZE 256 +#define CFG_SYS_NAND_ECCBYTES 3 +#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ 48, 49, 50, 51, 52, 53, 54, 55, \ 56, 57, 58, 59, 60, 61, 62, 63, } |