diff options
| author | Tom Rini | 2016-08-22 08:22:17 -0400 |
|---|---|---|
| committer | Tom Rini | 2016-08-26 17:04:46 -0400 |
| commit | 067716bac59716b07f1ee70d9bf6e5528289bb45 (patch) | |
| tree | 97e27955376354dbe1bbae977b02a6e323d2b54a /include/configs | |
| parent | da968c7bfa4cc1203a4f9f61a97f55c85dfbb3b6 (diff) | |
ARM: Move SYS_CACHELINE_SIZE over to Kconfig
This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all
cases we are mirroring the values used by the Linux Kernel here. Also,
so long as (and in this case, it is true) we implement flushes in hunks
that are no larger than the smallest implementation (and given that we
mirror the Linux Kernel, again we are fine) it is OK to align higher.
The biggest changes here are that we always use 64 bytes for CPU_V7 even
if for example the underlying core is only 32 bytes (this mirrors
Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the
Linux Kernel) as we do not need multi-platform support (to this degree)
and only the Cavium ThunderX 88xx series has a use for such large
alignment.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Stefan Roese <sr@denx.de>
Cc: Nagendra T S <nagendra@mistralsolutions.com>
Cc: Vaibhav Hiremath <hvaibhav@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Steve Rae <steve.rae@raedomain.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Heiko Schocher <hs@denx.de>
Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Cc: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Paul Kocialkowski <contact@paulk.fr>
Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: "Pali Rohár" <pali.rohar@gmail.com>
Cc: Adam Ford <aford173@gmail.com>
Cc: Steve Sakoman <sakoman@gmail.com>
Cc: Grazvydas Ignotas <notasas@gmail.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Robert Baldyga <r.baldyga@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Thomas Weber <weber@corscience.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: David Feng <fenghua@phytium.com.cn>
Cc: Alison Wang <b18965@freescale.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: York Sun <york.sun@nxp.com>
Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Cc: Mingkai Hu <mingkai.hu@nxp.com>
Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Cc: Aneesh Bansal <aneesh.bansal@freescale.com>
Cc: Saksham Jain <saksham.jain@nxp.com>
Cc: Qianyu Gong <qianyu.gong@nxp.com>
Cc: Wang Dongsheng <dongsheng.wang@nxp.com>
Cc: Alex Porosanu <alexandru.porosanu@freescale.com>
Cc: Hongbo Zhang <hongbo.zhang@nxp.com>
Cc: tang yuantian <Yuantian.Tang@freescale.com>
Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Cc: Josh Wu <josh.wu@atmel.com>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Hannes Schmelzer <oe5hpm@oevsv.at>
Cc: Thomas Chou <thomas@wytron.com.tw>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Sam Protsenko <semen.protsenko@linaro.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Christophe Ricard <christophe-h.ricard@st.com>
Cc: Anand Moon <linux.amoon@gmail.com>
Cc: Beniamino Galvani <b.galvani@gmail.com>
Cc: Carlo Caione <carlo@endlessm.com>
Cc: huang lin <hl@rock-chips.com>
Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Cc: Xu Ziyuan <xzy.xu@rock-chips.com>
Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com>
Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Samuel Egli <samuel.egli@siemens.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Andre Przywara <andre.przywara@arm.com>
Cc: Bernhard Nortmann <bernhard.nortmann@web.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Ben Whitten <ben.whitten@gmail.com>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Vitaly Andrianov <vitalya@ti.com>
Cc: "Andrew F. Davis" <afd@ti.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Carlos Hernandez <ceh@ti.com>
Cc: Ladislav Michl <ladis@linux-mips.org>
Cc: Ash Charles <ashcharles@gmail.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Daniel Allred <d-allred@ti.com>
Cc: Gong Qianyu <Qianyu.Gong@freescale.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Chin Liang See <clsee@altera.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Paul Kocialkowski <contact@paulk.fr>
Diffstat (limited to 'include/configs')
66 files changed, 0 insertions, 136 deletions
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index a65d1a884b0..30c42781caf 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -13,8 +13,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* * High Level Configuration Options */ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 4d88aac6375..ef4a8baf43c 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -18,8 +18,6 @@ #define CONFIG_OMAP #define CONFIG_OMAP_COMMON -#define CONFIG_SYS_CACHELINE_SIZE 64 - #define CONFIG_SYS_NO_FLASH #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 0467953566c..518b904807b 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -11,7 +11,6 @@ #define CONFIG_BOARD_LATE_INIT #define CONFIG_ARCH_CPU_INIT -#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ @@ -49,7 +48,6 @@ /* Enabling L2 Cache */ #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE 0x48242000 -#define CONFIG_SYS_CACHELINE_SIZE 32 /* * Since SPL did pll and ddr initialization for us, diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h index 9257c5f0292..051186d4bbb 100644 --- a/include/configs/at91-sama5_common.h +++ b/include/configs/at91-sama5_common.h @@ -12,8 +12,6 @@ #include <asm/hardware.h> -#define CONFIG_SYS_CACHELINE_SIZE 32 - #define CONFIG_SYS_TEXT_BASE 0x26f00000 /* ARM asynchronous clock */ diff --git a/include/configs/bcm23550_w1d.h b/include/configs/bcm23550_w1d.h index 770dd872f97..b9688014cd2 100644 --- a/include/configs/bcm23550_w1d.h +++ b/include/configs/bcm23550_w1d.h @@ -127,7 +127,6 @@ /* Commands */ #define CONFIG_FAT_WRITE -#define CONFIG_SYS_CACHELINE_SIZE 64 #undef CONFIG_USB_GADGET_VBUS_DRAW #define CONFIG_USB_GADGET_VBUS_DRAW 0 #define CONFIG_USBID_ADDR 0x34052c46 diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h index df0b2bac39d..f38f0813556 100644 --- a/include/configs/bcm28155_ap.h +++ b/include/configs/bcm28155_ap.h @@ -126,7 +126,6 @@ /* Commands */ #define CONFIG_FAT_WRITE -#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_USBID_ADDR 0x34052c46 #endif /* __BCM28155_AP_H */ diff --git a/include/configs/bcm_ep_board.h b/include/configs/bcm_ep_board.h index 50cd7430b59..b5e50292178 100644 --- a/include/configs/bcm_ep_board.h +++ b/include/configs/bcm_ep_board.h @@ -11,8 +11,6 @@ #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* * Memory configuration * (these must be defined elsewhere) diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index a94b1e27115..04da877db5f 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -15,7 +15,6 @@ #define CONFIG_AM33XX #define CONFIG_OMAP #define CONFIG_OMAP_COMMON -#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ /* Timer information */ diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h index ea9983bc7d4..a89ccb73b17 100644 --- a/include/configs/cm_t3517.h +++ b/include/configs/cm_t3517.h @@ -10,8 +10,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* * High Level Configuration Options */ @@ -30,7 +28,6 @@ * Although the default iss 64, we still define it * to be on the safe side once the default is changed. */ -#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index 5d94f133cba..b896d4d79a4 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -79,7 +79,6 @@ /* Enabling L2 Cache */ #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE 0x48242000 -#define CONFIG_SYS_CACHELINE_SIZE 32 /* * Since SPL did pll and ddr initialization for us, diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 58925952ddd..fb68e598b23 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -12,8 +12,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_CACHELINE_SIZE 32 - #include <asm/arch/imx-regs.h> #define CONFIG_VF610 @@ -207,8 +205,6 @@ #define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_CACHELINE_SIZE 32 - /* USB Host Support */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_VF diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 28ea15b596a..746475d45fe 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -118,7 +118,6 @@ #define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M) #define DFU_MANIFEST_POLL_TIMEOUT 25000 -#define CONFIG_SYS_CACHELINE_SIZE SZ_8K #define CONFIG_SYS_LOAD_ADDR ATMEL_BASE_CS6 /* bootstrap + u-boot + env in nandflash */ diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h index 1dbe2194f86..cc7ab8365d1 100644 --- a/include/configs/dragonboard410c.h +++ b/include/configs/dragonboard410c.h @@ -27,8 +27,6 @@ #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000) #define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16MB max kernel size */ -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* UART */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h index fbe0fa969d6..fdbaf027ac4 100644 --- a/include/configs/exynos4-common.h +++ b/include/configs/exynos4-common.h @@ -15,7 +15,6 @@ #define CONFIG_BOARD_COMMON -#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_REVISION_TAG /* SD/MMC configuration */ diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index f2ed7982b45..153878732b8 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -13,7 +13,6 @@ #include "exynos-common.h" -#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_EXYNOS_SPL #ifdef FTRACE diff --git a/include/configs/flea3.h b/include/configs/flea3.h index 824aca45b64..e84803dfb2b 100644 --- a/include/configs/flea3.h +++ b/include/configs/flea3.h @@ -19,7 +19,6 @@ #define CONFIG_MX35 #define CONFIG_SYS_DCACHE_OFF -#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_DISPLAY_CPUINFO diff --git a/include/configs/hikey.h b/include/configs/hikey.h index ffcc4d26307..9cbccd9dc9e 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -21,9 +21,6 @@ #define CONFIG_SUPPORT_RAW_INITRD -/* MMU Definitions */ -#define CONFIG_SYS_CACHELINE_SIZE 64 - #define CONFIG_IDENT_STRING "hikey" #define CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/kc1.h b/include/configs/kc1.h index b08cf2161db..8b957996a7b 100644 --- a/include/configs/kc1.h +++ b/include/configs/kc1.h @@ -24,7 +24,6 @@ #define CONFIG_SYS_L2_PL310 1 #define CONFIG_SYS_PL310_BASE 0x48242000 -#define CONFIG_SYS_CACHELINE_SIZE 32 /* * Platform diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index 94f35161594..a4b296ab8ff 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -10,8 +10,6 @@ #undef DEBUG -#define CONFIG_SYS_CACHELINE_SIZE 32 - #define CONFIG_SH73A0 #define CONFIG_KZM_A9_GT #define CONFIG_ARCH_RMOBILE_BOARD_STRING "KMC KZM-A9-GT" diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 0c6e1117d4f..8387f1920d3 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -25,8 +25,6 @@ #define CONFIG_MACH_TYPE MACH_TYPE_MCX #define CONFIG_BOARD_LATE_INIT -#define CONFIG_SYS_CACHELINE_SIZE 64 - #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ #include <asm/arch/cpu.h> /* get chip and board defs */ diff --git a/include/configs/meson-gxbb-common.h b/include/configs/meson-gxbb-common.h index eaf6a9c08a4..3bba2e6658c 100644 --- a/include/configs/meson-gxbb-common.h +++ b/include/configs/meson-gxbb-common.h @@ -10,7 +10,6 @@ #define CONFIG_CPU_ARMV8 #define CONFIG_REMAKE_ELF -#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_SYS_NO_FLASH #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_ENV_IS_NOWHERE 1 diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index cd154a4bbb3..cdae5442534 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -19,8 +19,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* * High Level Configuration Options */ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 4dbe2b62d14..fc5de034fe3 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -275,8 +275,6 @@ #define CONFIG_OMAP3_SPI -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* Defines for SPL */ #define CONFIG_SPL_OMAP3_ID_NAND diff --git a/include/configs/omap3_cairo.h b/include/configs/omap3_cairo.h index 82e0d5000ca..4310bada485 100644 --- a/include/configs/omap3_cairo.h +++ b/include/configs/omap3_cairo.h @@ -192,8 +192,6 @@ #define CONFIG_OMAP3_SPI -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* Defines for SPL */ #define CONFIG_SPL_OMAP3_ID_NAND diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 52a24d37b88..e87b4c0118b 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -340,8 +340,6 @@ /* Uncomment to define the board revision statically */ /* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */ -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* Defines for SPL */ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x40200800 diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 49a8b3f5ef4..05a43610e52 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -82,7 +82,6 @@ #define CONFIG_ANDROID_BOOT_IMAGE #define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR #define CONFIG_FASTBOOT_BUF_SIZE 0x07000000 -#define CONFIG_SYS_CACHELINE_SIZE 64 /* TWL4030 */ #define CONFIG_TWL4030_PWM diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index fbd0c2a0708..618a546dedb 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -215,7 +215,6 @@ /* Initial RAM setup */ #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_CACHELINE_SIZE 64 /* NAND boot config */ #define CONFIG_SYS_NAND_BUSWIDTH_16BIT diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 380ec129cda..9e7bd88adb0 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -119,6 +119,4 @@ #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET -#define CONFIG_SYS_CACHELINE_SIZE 64 - #endif /* __CONFIG_H */ diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index 99d9fc3b256..63970519481 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -176,8 +176,6 @@ #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET -#define CONFIG_SYS_CACHELINE_SIZE 64 - #ifdef CONFIG_CMD_NET /* Ethernet (LAN9211 from SMSC9118 family) */ #define CONFIG_SMC911X diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index 74e22db1512..57a76306e24 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -9,8 +9,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_CACHELINE_SIZE 32 - #include <asm/arch/imx-regs.h> #define CONFIG_VF610 diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index 80313fc8c57..8f91e8e0012 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -9,8 +9,6 @@ #ifndef __RCAR_GEN2_COMMON_H #define __RCAR_GEN2_COMMON_H -#define CONFIG_SYS_CACHELINE_SIZE 64 - #include <asm/arch/rmobile.h> #define CONFIG_CMD_DFL diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index 21d468354be..101a3ed5bd7 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -6,8 +6,6 @@ #ifndef __CONFIG_RK3036_COMMON_H #define __CONFIG_RK3036_COMMON_H -#define CONFIG_SYS_CACHELINE_SIZE 64 - #include <asm/arch/hardware.h> #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index d3d4c680e99..601186c5c1e 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -7,8 +7,6 @@ #ifndef __CONFIG_RK3288_COMMON_H #define __CONFIG_RK3288_COMMON_H -#define CONFIG_SYS_CACHELINE_SIZE 64 - #include <asm/arch/hardware.h> #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 6875308e11b..e9626a5e398 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -7,8 +7,6 @@ #ifndef __CONFIG_RK3399_COMMON_H #define __CONFIG_RK3399_COMMON_H -#define CONFIG_SYS_CACHELINE_SIZE 64 - #define CONFIG_SYS_NO_FLASH #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_ENV_SIZE 0x2000 diff --git a/include/configs/rpi.h b/include/configs/rpi.h index dbbb81efa99..752cc319fce 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -14,12 +14,6 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #endif -#ifdef CONFIG_BCM2835 -#define CONFIG_SYS_CACHELINE_SIZE 32 -#else -#define CONFIG_SYS_CACHELINE_SIZE 64 -#endif - /* Architecture, CPU, etc.*/ #define CONFIG_ARCH_CPU_INIT diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 87e51d0aa9a..61c5663c408 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -17,8 +17,6 @@ #define CONFIG_S5PC110 1 /* which is in a S5PC110 */ #define CONFIG_MACH_GONI 1 /* working with Goni */ -#define CONFIG_SYS_CACHELINE_SIZE 64 - #include <linux/sizes.h> #include <asm/arch/cpu.h> /* get chip and board defs */ @@ -236,8 +234,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) -#define CONFIG_SYS_CACHELINE_SIZE 64 - #define CONFIG_POWER #define CONFIG_POWER_I2C #define CONFIG_POWER_MAX8998 diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index eab665c2866..3d25e3db3e6 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -36,8 +36,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* commands to include */ #define CONFIG_ENV_VARS_UBOOT_CONFIG diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index 076a5ce2992..8ad8f24cc91 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -170,8 +170,6 @@ #define CONFIG_DFU_NAND #define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_1M #define DFU_MANIFEST_POLL_TIMEOUT 25000 - -#define CONFIG_SYS_CACHELINE_SIZE 0x2000 #endif /* General Boot Parameter */ diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index 84a188af3a6..9d52689b80f 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -12,8 +12,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* * High Level Configuration Options * (easy to change) diff --git a/include/configs/sniper.h b/include/configs/sniper.h index fb348a5cd26..e2f5e60b2aa 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -16,8 +16,6 @@ * CPU */ -#define CONFIG_SYS_CACHELINE_SIZE 64 - #define CONFIG_ARM_ARCH_CP15_ERRATA #define CONFIG_ARM_ERRATA_454179 #define CONFIG_ARM_ERRATA_430973 diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index f654f945bc1..ce5781b8065 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -75,7 +75,6 @@ /* * Cache */ -#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index b9aa62b2af6..f64edd4b0fe 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -55,7 +55,6 @@ /* CPU */ #define CONFIG_DISPLAY_CPUINFO -#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_TIMER_CLK_FREQ 24000000 /* diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 73ff416aed2..52130650959 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -23,8 +23,6 @@ #define CONFIG_SYS_TEXT_BASE 0x80008000 -#define CONFIG_SYS_CACHELINE_SIZE 64 - #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ #include <asm/arch/cpu.h> /* get chip and board defs */ diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 6616d7396e7..52bd8370a03 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -13,8 +13,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* * High Level Configuration Options */ diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 2d091db07d9..513e6552548 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -133,8 +133,6 @@ #define CONFIG_DFU_NAND #define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M) #define DFU_MANIFEST_POLL_TIMEOUT 25000 - -#define CONFIG_SYS_CACHELINE_SIZE SZ_8K #endif /* SPI EEPROM */ diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index 21454d47cb5..107a0f88033 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -8,9 +8,6 @@ #define _TEGRA114_COMMON_H_ #include "tegra-common.h" -/* Cortex-A15 uses a cache line size of 64 bytes */ -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* * NS16550 Configuration */ diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h index 39e74f023fd..8cf9bac1568 100644 --- a/include/configs/tegra124-common.h +++ b/include/configs/tegra124-common.h @@ -10,9 +10,6 @@ #include "tegra-common.h" -/* Cortex-A15 uses a cache line size of 64 bytes */ -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* * NS16550 Configuration */ diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h index aa7b9d038a7..98e4fc2d252 100644 --- a/include/configs/tegra186-common.h +++ b/include/configs/tegra186-common.h @@ -9,9 +9,6 @@ #include "tegra-common.h" -/* Cortex-A57 uses a cache line size of 64 bytes */ -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* * NS16550 Configuration */ diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 00e85c48c41..793310ff473 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -9,9 +9,6 @@ #define _TEGRA20_COMMON_H_ #include "tegra-common.h" -/* Cortex-A9 uses a cache line size of 32 bytes */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - /* * Errata configuration */ diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h index 8f35a7bf3dc..874fe34d4f4 100644 --- a/include/configs/tegra210-common.h +++ b/include/configs/tegra210-common.h @@ -10,9 +10,6 @@ #include "tegra-common.h" -/* Cortex-A57 uses a cache line size of 64 bytes */ -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* * NS16550 Configuration */ diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index 9afd86484bb..baf3d00f34b 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -9,9 +9,6 @@ #define _TEGRA30_COMMON_H_ #include "tegra-common.h" -/* Cortex-A9 uses a cache line size of 32 bytes */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - /* * Errata configuration */ diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 3c058832e17..732854eb306 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -16,8 +16,6 @@ #ifndef __CONFIG_TI814X_EVM_H #define __CONFIG_TI814X_EVM_H -#define CONFIG_SYS_CACHELINE_SIZE 64 - #define CONFIG_TI81XX #define CONFIG_TI814X #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index 05fd00fd5d2..17f12a898a8 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -10,8 +10,6 @@ #ifndef __CONFIG_TI816X_EVM_H #define __CONFIG_TI816X_EVM_H -#define CONFIG_SYS_CACHELINE_SIZE 64 - #define CONFIG_TI81XX #define CONFIG_TI816X #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index bcd56fc08dc..a9b10d05329 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -14,7 +14,6 @@ #define CONFIG_AM33XX #define CONFIG_ARCH_CPU_INIT -#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ #define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 4aa262e1a87..c830c0c0bf6 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -200,7 +200,6 @@ #define CONFIG_USB_STORAGE #define CONFIG_EFI_PARTITION #define CONFIG_FS_FAT -#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_USB_SS_BASE KS2_USB_SS_BASE #define CONFIG_USB_HOST_XHCI_BASE KS2_USB_HOST_XHCI_BASE #define CONFIG_DEV_USB_PHY_BASE KS2_DEV_USB_PHY_BASE diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index 32877d1964d..c54b7b55c4f 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -18,8 +18,6 @@ * High Level Configuration Options */ -#define CONFIG_SYS_CACHELINE_SIZE 64 - #include <asm/arch/cpu.h> #include <asm/arch/omap.h> diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 5fad3c1242c..e6e88c52825 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -26,7 +26,6 @@ #define CONFIG_SYS_L2_PL310 1 #define CONFIG_SYS_PL310_BASE 0x48242000 #endif -#define CONFIG_SYS_CACHELINE_SIZE 32 /* Get CPU defs */ #include <asm/arch/cpu.h> diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 3589cdc3a88..e42c88e3b92 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -23,8 +23,6 @@ /* Common ARM Erratas */ #define CONFIG_ARM_ERRATA_798870 -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* Use General purpose timer 1 */ #define CONFIG_SYS_TIMERBASE GPT2_BASE diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 127a9689482..ae0e89c5945 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -16,8 +16,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* High Level Configuration Options */ #define CONFIG_SYS_THUMB_BUILD #define CONFIG_OMAP /* in a TI OMAP core */ diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 0f5b20ff48c..f41a0b1cad6 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -30,12 +30,6 @@ /* #define CONFIG_SYS_ICACHE_OFF */ /* #define CONFIG_SYS_DCACHE_OFF */ -#ifdef CONFIG_CACHE_UNIPHIER -#define CONFIG_SYS_CACHELINE_SIZE 128 -#else -#define CONFIG_SYS_CACHELINE_SIZE 32 -#endif - #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_MISC_INIT_F diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 9aca3936fb1..71c4a1f08d6 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -19,9 +19,6 @@ #define CONFIG_SUPPORT_RAW_INITRD -/* MMU Definitions */ -#define CONFIG_SYS_CACHELINE_SIZE 64 - #define CONFIG_IDENT_STRING " vexpress_aemv8a" /* Link Definitions */ diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index 51898e623cb..a8eba314e30 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -118,8 +118,6 @@ #define CONFIG_SYS_MEMTEST_START V2M_BASE #define CONFIG_SYS_MEMTEST_END 0x20000000 -#define CONFIG_SYS_CACHELINE_SIZE 64 - #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_SYS_L2CACHE_OFF 1 diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index c4a1fd091ab..33f966ac6e4 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -9,8 +9,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_CACHELINE_SIZE 32 - #include <asm/arch/imx-regs.h> #define CONFIG_VF610 diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h index 153466a623f..de6b1838d76 100644 --- a/include/configs/woodburn_common.h +++ b/include/configs/woodburn_common.h @@ -19,7 +19,6 @@ #define CONFIG_SYS_FSL_CLK #define CONFIG_SYS_DCACHE_OFF -#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_DISPLAY_CPUINFO diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index ca60e5d3d9c..02f0e4c9a9a 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -34,9 +34,6 @@ /* Have release address at the end of 256MB for now */ #define CPU_RELEASE_ADDR 0xFFFFFF0 -/* Cache Definitions */ -#define CONFIG_SYS_CACHELINE_SIZE 64 - #if !defined(CONFIG_IDENT_STRING) # define CONFIG_IDENT_STRING " Xilinx ZynqMP" #endif diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index e59e412d58a..5f7fefde3d5 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -16,8 +16,6 @@ #endif /* Cache options */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - #define CONFIG_SYS_L2CACHE_OFF #ifndef CONFIG_SYS_L2CACHE_OFF # define CONFIG_SYS_L2_PL310 |