Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxx

17 files changed, 16 insertions, 5956 deletions

diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h
deleted file mode 100644
index 304a12bea9c..00000000000
--- a/include/configs/CPCI750.h
+++ /dev/null
@@ -1,609 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-/*************************************************************************
- * (c) 2004 esd gmbh Hannover
- *
- *
- * from db64360.h file
- * by Reinhard Arlt reinhard.arlt@esd-electronics.com
- *
-  ************************************************************************/
-
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* This define must be before the core.h include */
-#define CONFIG_CPCI750		1	/* this is an CPCI750 board	*/
-
-#ifndef __ASSEMBLY__
-#include <../board/Marvell/include/core.h>
-#endif
-/*-----------------------------------------------------*/
-
-#include "../board/esd/cpci750/local.h"
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_750FX			/* we have a 750FX (override local.h) */
-
-#define CONFIG_CPCI750		1	/* this is an CPCI750 board	*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xfff00000
-
-#define CONFIG_BAUDRATE		9600	/* console baudrate = 9600	*/
-
-#define CONFIG_MV64360_ECC		/* enable ECC support */
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-/* which initialization functions to call for this board */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_BOARD_PRE_INIT
-#define CONFIG_BOARD_EARLY_INIT_F 1
-
-#define CONFIG_SYS_BOARD_NAME		"CPCI750"
-#define CONFIG_IDENT_STRING	"Marvell 64360 + IBM750FX"
-
-/*#define CONFIG_SYS_HUSH_PARSER*/
-#define CONFIG_SYS_HUSH_PARSER
-
-
-#define CONFIG_CMDLINE_EDITING		/* add command line history	*/
-#define CONFIG_AUTO_COMPLETE		/* add autocompletion support	*/
-
-/* Define which ETH port will be used for connecting the network */
-#define CONFIG_SYS_ETH_PORT		ETH_0
-
-/*
- * The following defines let you select what serial you want to use
- * for your console driver.
- *
- * what to do:
- * to use the DUART, undef CONFIG_MPSC.	 If you have hacked a serial
- * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
- * to 0 below.
- *
- * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
- * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
- */
-#define CONFIG_MPSC
-#define CONFIG_MPSC_PORT	0
-
-/* to change the default ethernet port, use this define (options: 0, 1, 2) */
-#define MV_ETH_DEVS		1
-#define CONFIG_ETHER_PORT	0
-
-#undef CONFIG_ETHER_PORT_MII	/* use RMII */
-
-#define CONFIG_BOOTDELAY	5	/* autoboot disabled		*/
-
-#define CONFIG_RTC_M48T35A	1	/* ST Electronics M48 timekeeper */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-
-#undef	CONFIG_BOOTARGS
-
-/* -----------------------------------------------------------------------------
- * New bootcommands for Marvell CPCI750 c 2002 Ingo Assmus
- */
-
-#define CONFIG_IPADDR		"192.168.0.185"
-
-#define CONFIG_SERIAL		"AA000001"
-#define CONFIG_SERVERIP		"10.0.0.79"
-#define CONFIG_ROOTPATH		"/export/nfs_cpci750/%s"
-
-#define CONFIG_TESTDRAMDATA	y
-#define CONFIG_TESTDRAMADDRESS	n
-#define CONFIG_TESETDRAMWALK	n
-
-/* ----------------------------------------------------------------------------- */
-
-
-#define CONFIG_LOADS_ECHO	0	/* echo off for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-#undef	CONFIG_ALTIVEC			/* undef to disable		*/
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-
-
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_USE_CPCIDVI
-
-#ifdef	CONFIG_USE_CPCIDVI
-#define CONFIG_VIDEO
-#define CONFIG_VIDEO_CT69000
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_I8042_KBD
-#define CONFIG_SYS_ISA_IO 0
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
-#define CONFIG_SYS_I2C_SPEED	80000		/* I2C speed default */
-
-#define CONFIG_PRAM 0
-
-#define CONFIG_SYS_GT_DUAL_CPU			/* also for JTAG even with one cpu */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-/*#define CONFIG_SYS_MEMTEST_START	0x00400000*/	/* memtest works on	*/
-/*#define CONFIG_SYS_MEMTEST_END		0x00C00000*/	/* 4 ... 12 MB in DRAM	*/
-/*#define CONFIG_SYS_MEMTEST_END		0x07c00000*/	/* 4 ... 124 MB in DRAM */
-
-/*
-#define CONFIG_SYS_DRAM_TEST
- * DRAM tests
- *   CONFIG_SYS_DRAM_TEST - enables the following tests.
- *
- *   CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines
- *			  Environment variable 'test_dram_data' must be
- *			  set to 'y'.
- *   CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
- *			  addressable. Environment variable
- *			  'test_dram_address' must be set to 'y'.
- *   CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
- *			  This test takes about 6 minutes to test 64 MB.
- *			  Environment variable 'test_dram_walk' must be
- *			  set to 'y'.
- */
-#define CONFIG_SYS_DRAM_TEST
-#if defined(CONFIG_SYS_DRAM_TEST)
-#define CONFIG_SYS_MEMTEST_START		0x00400000	/* memtest works on	*/
-/*#define CONFIG_SYS_MEMTEST_END		0x00C00000*/	/* 4 ... 12 MB in DRAM	*/
-#define CONFIG_SYS_MEMTEST_END		0x07c00000	/* 4 ... 124 MB in DRAM */
-#define CONFIG_SYS_DRAM_TEST_DATA
-#define CONFIG_SYS_DRAM_TEST_ADDRESS
-#define CONFIG_SYS_DRAM_TEST_WALK
-#endif /* CONFIG_SYS_DRAM_TEST */
-
-#define CONFIG_DISPLAY_MEMMAP		/* at the end of the bootprocess show the memory map */
-#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT	/* show SPD content during boot */
-
-#define CONFIG_SYS_LOAD_ADDR		0x00300000	/* default load address */
-
-#define CONFIG_SYS_BUS_CLK		133000000	/* 133 MHz (CPU = 5*Bus = 666MHz)		*/
-
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_SYS_TCLK		133000000
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-
- /*
- * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
- * To an unused memory region. The stack will remain in cache until RAM
- * is initialized
-*/
-#undef	  CONFIG_SYS_INIT_RAM_LOCK
-/* #define CONFIG_SYS_INIT_RAM_ADDR	0x40000000*/ /* unused memory region */
-/* #define CONFIG_SYS_INIT_RAM_ADDR	0xfba00000*/ /* unused memory region */
-#define CONFIG_SYS_INIT_RAM_ADDR	0xf1080000 /* unused memory region */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-#define RELOCATE_INTERNAL_RAM_ADDR
-#ifdef RELOCATE_INTERNAL_RAM_ADDR
-/*#define CONFIG_SYS_INTERNAL_RAM_ADDR 0xfba00000*/
-#define CONFIG_SYS_INTERNAL_RAM_ADDR	0xf1080000
-#endif
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-/* Dummies for BAT 4-7 */
-#define CONFIG_SYS_SDRAM1_BASE		0x10000000	/* each 256 MByte */
-#define CONFIG_SYS_SDRAM2_BASE		0x20000000
-#define CONFIG_SYS_SDRAM3_BASE		0x30000000
-#define CONFIG_SYS_SDRAM4_BASE		0x40000000
-#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE	0xfff00000
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 256 kB for malloc */
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI		1	   /* Flash is CFI conformant		*/
-#define CONFIG_SYS_FLASH_PROTECTION	1	   /* use hardware protection		*/
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	   /* use buffered writes (20x faster)	*/
-#define CONFIG_SYS_FLASH_BASE		0xfc000000 /* start of flash banks		*/
-#define CONFIG_SYS_MAX_FLASH_BANKS	4	   /* max number of memory banks	*/
-#define CONFIG_SYS_FLASH_INCREMENT	0x01000000 /* size of  flash bank		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	128	   /* max number of sectors on one chip */
-#define CONFIG_SYS_FLASH_BANKS_LIST  { CONFIG_SYS_FLASH_BASE,				   \
-				CONFIG_SYS_FLASH_BASE + 1*CONFIG_SYS_FLASH_INCREMENT,	   \
-				CONFIG_SYS_FLASH_BASE + 2*CONFIG_SYS_FLASH_INCREMENT,	   \
-				CONFIG_SYS_FLASH_BASE + 3*CONFIG_SYS_FLASH_INCREMENT }
-#define CONFIG_SYS_FLASH_EMPTY_INFO	1	   /* show if bank is empty		*/
-
-/* areas to map different things with the GT in physical space */
-#define CONFIG_SYS_DRAM_BANKS		4
-
-/* What to put in the bats. */
-#define CONFIG_SYS_MISC_REGION_BASE	0xf0000000
-
-/* Peripheral Device section */
-
-/*******************************************************/
-/* We have on the cpci750 Board :		       */
-/* GT-Chipset Register Area			       */
-/* GT-Chipset internal SRAM 256k		       */
-/* SRAM on external device module		       */
-/* Real time clock on external device module	       */
-/* dobble UART on external device module	       */
-/* Data flash on external device module		       */
-/* Boot flash on external device module		       */
-/*******************************************************/
-#define CONFIG_SYS_DFL_GT_REGS		0x14000000				/* boot time GT_REGS */
-#define	 CONFIG_SYS_CPCI750_RESET_ADDR 0x14000000				/* After power on Reset the CPCI750 is here */
-
-#undef	MARVEL_STANDARD_CFG
-#ifndef		MARVEL_STANDARD_CFG
-/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-#define CONFIG_SYS_GT_REGS		0xf1000000				/* GT Registers will be mapped here */
-/*#define CONFIG_SYS_DEV_BASE		0xfc000000*/				/* GT Devices CS start here */
-#define CONFIG_SYS_INT_SRAM_BASE	0xf1080000				/* GT offers 256k internal fast SRAM */
-
-#define CONFIG_SYS_BOOT_SPACE		0xff000000				/* BOOT_CS0 flash 0    */
-#define CONFIG_SYS_DEV0_SPACE		0xfc000000				/* DEV_CS0 flash 1     */
-#define CONFIG_SYS_DEV1_SPACE		0xfd000000				/* DEV_CS1 flash 2     */
-#define CONFIG_SYS_DEV2_SPACE		0xfe000000				/* DEV_CS2 flash 3     */
-#define CONFIG_SYS_DEV3_SPACE		0xf0000000				/* DEV_CS3 nvram/can   */
-
-#define CONFIG_SYS_BOOT_SIZE		_16M					/* cpci750 flash 0     */
-#define CONFIG_SYS_DEV0_SIZE		_16M					/* cpci750 flash 1     */
-#define CONFIG_SYS_DEV1_SIZE		_16M					/* cpci750 flash 2     */
-#define CONFIG_SYS_DEV2_SIZE		_16M					/* cpci750 flash 3     */
-#define CONFIG_SYS_DEV3_SIZE		_16M					/* cpci750 nvram/can   */
-
-/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-#endif
-
-/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
-#define CONFIG_SYS_DEV0_PAR		0x8FDFFFFF				/* 16 bit flash */
-#define CONFIG_SYS_DEV1_PAR		0x8FDFFFFF				/* 16 bit flash */
-#define CONFIG_SYS_DEV2_PAR		0x8FDFFFFF				/* 16 bit flash */
-#define CONFIG_SYS_DEV3_PAR		0x8FCFFFFF				/* nvram/can	*/
-#define CONFIG_SYS_BOOT_PAR		0x8FDFFFFF				/* 16 bit flash */
-
-	/*   c	  4    a      8	    2	  4    1      c		*/
-	/* 33 22|2222|22 22|111 1|11 11|1 1  |	  |		*/
-	/* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210	*/
-	/* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100	*/
-	/*  3| 0|.... ..| 2| 4 |  0 |  4 |  8  |  3  | 4	*/
-
-
-/* MPP Control MV64360 Appendix P P. 632*/
-#define CONFIG_SYS_MPP_CONTROL_0	0x00002222	/*				     */
-#define CONFIG_SYS_MPP_CONTROL_1	0x11110000	/*				     */
-#define CONFIG_SYS_MPP_CONTROL_2	0x11111111	/*				     */
-#define CONFIG_SYS_MPP_CONTROL_3	0x00001111	/*				     */
-/* #define CONFIG_SYS_SERIAL_PORT_MUX	0x00000102*/	/*				     */
-
-
-#define CONFIG_SYS_GPP_LEVEL_CONTROL	0xffffffff	/* 1111 1111 1111 1111 1111 1111 1111 1111*/
-
-/* setup new config_value for MV64360 DDR-RAM To_do !! */
-/*# define CONFIG_SYS_SDRAM_CONFIG	0xd8e18200*/	/* 0x448 */
-/*# define CONFIG_SYS_SDRAM_CONFIG	0xd8e14400*/	/* 0x1400 */
-				/* GB has high prio.
-				   idma has low prio
-				   MPSC has low prio
-				   pci has low prio 1 and 2
-				   cpu has high prio
-				   Data DQS pins == eight (DQS[7:0] foe x8 and x16 devices
-				   ECC disable
-				   non registered DRAM */
-				/* 31:26   25:22  21:20 19 18 17 16 */
-				/* 100001 0000	 010   0   0   0  0 */
-				/* refresh_count=0x400
-				   phisical interleaving disable
-				   virtual interleaving enable */
-				/* 15 14 13:0 */
-				/* 0  1	 0x400 */
-# define CONFIG_SYS_SDRAM_CONFIG	0x58200400	/* 0x1400  copied from Dink32 bzw. VxWorks*/
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-
-#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
-#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-#define CONFIG_PCI_SCAN_SHOW		/* show devices on bus		*/
-
-/* PCI MEMORY MAP section */
-#define CONFIG_SYS_PCI0_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI0_MEM_SIZE	_128M
-#define CONFIG_SYS_PCI1_MEM_BASE	0x88000000
-#define CONFIG_SYS_PCI1_MEM_SIZE	_128M
-
-#define CONFIG_SYS_PCI0_0_MEM_SPACE	(CONFIG_SYS_PCI0_MEM_BASE)
-#define CONFIG_SYS_PCI1_0_MEM_SPACE	(CONFIG_SYS_PCI1_MEM_BASE)
-
-/* PCI I/O MAP section */
-#define CONFIG_SYS_PCI0_IO_BASE	0xfa000000
-#define CONFIG_SYS_PCI0_IO_SIZE	_16M
-#define CONFIG_SYS_PCI1_IO_BASE	0xfb000000
-#define CONFIG_SYS_PCI1_IO_SIZE	_16M
-
-#define CONFIG_SYS_PCI0_IO_SPACE	(CONFIG_SYS_PCI0_IO_BASE)
-#define CONFIG_SYS_PCI0_IO_SPACE_PCI	0x00000000
-#define CONFIG_SYS_PCI1_IO_SPACE	(CONFIG_SYS_PCI1_IO_BASE)
-#define CONFIG_SYS_PCI1_IO_SPACE_PCI	0x00000000
-
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI0_IO_BASE)
-
-#if defined (CONFIG_750CX)
-#define CONFIG_SYS_PCI_IDSEL 0x0
-#else
-#define CONFIG_SYS_PCI_IDSEL 0x30
-#endif
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
-#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
-#define CONFIG_IDE_RESET		/* no reset for ide supported	*/
-#define CONFIG_IDE_PREINIT		/* check for units		*/
-
-#define CONFIG_SYS_IDE_MAXBUS		2		/* max. 1 IDE busses	*/
-#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_BASE_ADDR	0
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0
-#define CONFIG_SYS_ATA_IDE1_OFFSET	0
-
-#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
-#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
-#ifndef __ASSEMBLY__
-int ata_device(int dev);
-#endif
-#define ATA_DEVICE(dev)                 ata_device(dev)
-#define CONFIG_ATAPI                    1
-
-/*----------------------------------------------------------------------
- * Initial BAT mappings
- */
-
-/* NOTES:
- * 1) GUARDED and WRITE_THRU not allowed in IBATS
- * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
- */
-
-/* SDRAM */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* init ram */
-#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
-
-/* PCI0, PCI1 in one BAT */
-#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
-#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* GT regs, bootrom, all the devices, PCI I/O */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/*
- * 750FX IBAT and DBAT pairs (To_do: define regins for I(D)BAT4 - I(D)BAT7)
- * IBAT4 and DBAT4
- * FIXME: ingo disable BATs for Linux Kernel
- */
-/* #undef SETUP_HIGH_BATS_FX750	*/	/* don't initialize BATS 4-7 */
-#define SETUP_HIGH_BATS_FX750		/* initialize BATS 4-7 */
-
-#ifdef SETUP_HIGH_BATS_FX750
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-/* IBAT5 and DBAT5 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_SDRAM2_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT5L (CONFIG_SYS_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-
-/* IBAT6 and DBAT6 */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_SDRAM3_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT6L (CONFIG_SYS_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-
-/* IBAT7 and DBAT7 */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
-#else		/* set em out of range for Linux !!!!!!!!!!! */
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-/* IBAT5 and DBAT5 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT5L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT4U
-
-/* IBAT6 and DBAT6 */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT6L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT4U
-
-/* IBAT7 and DBAT7 */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT4U
-
-#endif
-/* FIXME: ingo end: disable BATs for Linux Kernel */
-
-/* I2C addresses for the two DIMM SPD chips */
-#define DIMM0_I2C_ADDR	0x51
-#define DIMM1_I2C_ADDR	0x52
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8<<20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_BOOT_FLASH_WIDTH	2	/* 16 bit */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT	500	/* Timeout for Flash Lock (in ms) */
-
-#if 0
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE	0x10000
-#define CONFIG_ENV_ADDR		0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
-/* #define CONFIG_ENV_ADDR	   (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */
-#endif
-
-#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x050
-#define CONFIG_ENV_OFFSET		0x200	/* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE		0x600	/* 2048 bytes may be used for env vars*/
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0000000		/* NVRAM base address	*/
-#define CONFIG_SYS_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
-#define CONFIG_SYS_VXWORKS_MAC_PTR	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-0x40)
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * L2CR setup -- make sure this is right for your board!
- * look in include/mpc74xx.h for the defines used here
- */
-
-/*#define CONFIG_SYS_L2*/
-#undef CONFIG_SYS_L2
-
-/*    #ifdef CONFIG_750CX*/
-#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
-#define L2_INIT 0
-#else
-#define L2_INIT		(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
-			L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
-#endif
-
-#define L2_ENABLE	(L2_INIT | L2CR_L2E)
-
-#define CONFIG_SYS_BOARD_ASM_INIT	1
-
-#define CPCI750_SLAVE_TEST	(((in8(0xf0300000) & 0x80) == 0) ? 0 : 1)
-#define CPCI750_ECC_TEST	(((in8(0xf0300000) & 0x02) == 0) ? 1 : 0)
-#define CONFIG_SYS_PLD_VER	0xf0e00000
-
-#define CONFIG_OF_LIBFDT 1
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/DB64360.h b/include/configs/DB64360.h
deleted file mode 100644
index b77c8b28943..00000000000
--- a/include/configs/DB64360.h
+++ /dev/null
@@ -1,579 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-/*************************************************************************
- * (c) 2002 Datentechnik AG - Project: Dino
- *
- *
- * $Id: DB64360.h,v 1.3 2003/04/26 04:58:13 brad Exp $
- *
-  ************************************************************************/
-
-/*************************************************************************
- *
- * History:
- *
- *	$Log: DB64360.h,v $
- *	Revision 1.3  2003/04/26 04:58:13  brad
- *	Cosmetic changes and compiler warning cleanups
- *
- *	Revision 1.2  2003/04/23 15:48:15  ingo
- *	mem. map output added
- *
- *	Revision 1.1  2003/04/17 09:31:42  ias
- *	keymile changes 17_04_2003
- *
- *	Revision 1.10  2003/03/06 12:25:04  ias
- *	750 FX CPU HID settings updated
- *
- *	Revision 1.9  2003/03/03 16:14:36  ias
- *	cleanup compiler warnings of printf fuctions
- *
- *	Revision 1.8  2003/03/03 15:11:44  ias
- *	Marvell MPSC-UART is working
- *
- *	Revision 1.7  2003/02/26 12:15:45  ssu
- *	adapted default parameters to new board flash address
- *
- *	Revision 1.6  2003/02/25 14:55:42  ssu
- *	changed default environment parameters
- *
- *	Revision 1.5  2003/02/21 17:14:23  ias
- *	added extended SPD handling
- *
- *	Revision 1.4  2003/01/14 09:16:08  ias
- *	PPCBoot for Marvel Beta 0.9
- *
- *	Revision 1.3  2002/12/03 13:56:26  ias
- *	Environment in flash support added
- *
- *	Revision 1.2  2002/11/29 16:53:29  ias
- *	Flash support for STM added
- *
- *	Revision 1.1  2002/11/29 13:36:31  ias
- *	Revision 0.1 of PPCBOOT (1.1.5) for Marvell DB64360 IBM750FX Board
- *	- working DDRRAM (only 32MByte of 128MB Modul)
- *	- working I2C Driver for SPD EEPROM read
- *	- working DUART 16650 for Serial Console
- *	- working "console"
- *
- *
- *
- ************************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* This define must be before the core.h include */
-#define CONFIG_DB64360		1	/* this is an DB64360 board	*/
-
-#ifndef __ASSEMBLY__
-#include "../board/Marvell/include/core.h"
-#endif
-
-/*-----------------------------------------------------*/
-/*    #include "../board/db64360/local.h"	      */
-#ifndef __LOCAL_H
-#define __LOCAL_H
-
-/* first ethernet */
-#define CONFIG_ETHADDR		64:36:00:00:00:01
-											     /* next two ethernet hwaddrs */
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR		64:36:00:00:00:02
-/* in the atlantis 64360 we have only 2 ETH port on the board,
-if we use PCI it has its own MAC addr */
-
-#define CONFIG_ENV_OVERWRITE
-#endif	/* __CONFIG_H */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_74xx			/* we have a 750FX (override local.h) */
-
-#define CONFIG_DB64360		1	/* this is an DB64360 board	*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xfff00000
-
-#define CONFIG_BAUDRATE		115200	/* console baudrate = 115000	*/
-/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the
-	DRAM for ECC in the phase we are relocating to it, which isn't so sufficient.
-	so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase,
-	see sdram_init.c   */
-#undef CONFIG_ECC	 /* enable ECC support */
-#define CONFIG_MV64360_ECC
-
-/* which initialization functions to call for this board */
-#define CONFIG_MISC_INIT_R     /* initialize the icache L1 */
-#define CONFIG_BOARD_EARLY_INIT_F
-
-#define CONFIG_SYS_BOARD_NAME		"DB64360"
-#define CONFIG_IDENT_STRING	"Marvell DB64360 (1.1)"
-
-/*#define CONFIG_SYS_HUSH_PARSER */
-#undef CONFIG_SYS_HUSH_PARSER
-
-
-/*
- * The following defines let you select what serial you want to use
- * for your console driver.
- *
- * what to do:
- * to use the DUART, undef CONFIG_MPSC.	 If you have hacked a serial
- * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
- * to 0 below.
- *
- * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
- * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
- */
-
-#define CONFIG_MPSC_PORT	0
-
-/* to change the default ethernet port, use this define (options: 0, 1, 2) */
-#define MV_ETH_DEVS 2
-
-/* #undef CONFIG_ETHER_PORT_MII	 */
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds	*/
-#endif
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-
-#undef	CONFIG_BOOTARGS
-/*#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */
-
-/* ronen - autoboot using tftp */
-#if (CONFIG_BOOTDELAY >= 0)
-#define CONFIG_BOOTCOMMAND	"tftpboot 0x400000 uImage;\
- setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \
- ip=${ipaddr}:${serverip}${bootargs_end};  bootm 0x400000; "
-
-#define CONFIG_BOOTARGS "console=ttyS0,115200"
-
-#endif
-
-/* ronen - the u-boot.bin should be ~0x30000 bytes */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-     "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \
-cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \
-      "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \
-cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \
-      "bootargs_root=root=/dev/nfs rw\0" \
-      "bootargs_end=:::DB64360:eth0:none \0"\
-      "ethprime=mv_enet0\0"\
-      "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \
-ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
-
-/* --------------------------------------------------------------------------------------------------------------- */
-/* New bootcommands for Marvell DB64360 c 2002 Ingo Assmus */
-
-#define CONFIG_IPADDR		10.2.40.90
-
-#define CONFIG_SERIAL		"No. 1"
-#define CONFIG_SERVERIP		10.2.1.126
-#define CONFIG_ROOTPATH		"/mnt/yellow_dog_mini"
-
-
-#define CONFIG_TESTDRAMDATA	y
-#define CONFIG_TESTDRAMADDRESS	n
-#define CONFIG_TESETDRAMWALK	n
-
-/* --------------------------------------------------------------------------------------------------------------- */
-
-#define CONFIG_LOADS_ECHO	0	/* echo off for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-#undef	CONFIG_ALTIVEC			/* undef to disable		*/
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV		"nor1"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-
-/* Use first bank for JFFS2, second bank contains U-Boot.
- *
- * Note: fake mtd_id's used, no linux mtd map file.
- */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT		"nor1=db64360-1"
-#define MTDPARTS_DEFAULT	"mtdparts=db64360-1:-(jffs2)"
-*/
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_NET
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
-#define CONFIG_SYS_I2C_SPEED	40000		/* I2C speed default */
-
-/* #define CONFIG_SYS_GT_DUAL_CPU	 also for JTAG even with one cpu */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-/*#define CONFIG_SYS_MEMTEST_START	0x00400000	 memtest works on	*/
-/*#define CONFIG_SYS_MEMTEST_END		0x00C00000	 4 ... 12 MB in DRAM	*/
-/*#define CONFIG_SYS_MEMTEST_END		0x07c00000	 4 ... 124 MB in DRAM	*/
-
-/*
-#define CONFIG_SYS_DRAM_TEST
- * DRAM tests
- *   CONFIG_SYS_DRAM_TEST - enables the following tests.
- *
- *   CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines
- *			  Environment variable 'test_dram_data' must be
- *			  set to 'y'.
- *   CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
- *			  addressable. Environment variable
- *			  'test_dram_address' must be set to 'y'.
- *   CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
- *			  This test takes about 6 minutes to test 64 MB.
- *			  Environment variable 'test_dram_walk' must be
- *			  set to 'y'.
- */
-#define CONFIG_SYS_DRAM_TEST
-#if defined(CONFIG_SYS_DRAM_TEST)
-#define CONFIG_SYS_MEMTEST_START		0x00400000	/* memtest works on	*/
-/* #define CONFIG_SYS_MEMTEST_END		0x00C00000	 4 ... 12 MB in DRAM	*/
-#define CONFIG_SYS_MEMTEST_END		0x07c00000	/* 4 ... 124 MB in DRAM */
-#define CONFIG_SYS_DRAM_TEST_DATA
-#define CONFIG_SYS_DRAM_TEST_ADDRESS
-#define CONFIG_SYS_DRAM_TEST_WALK
-#endif /* CONFIG_SYS_DRAM_TEST */
-
-#undef CONFIG_DISPLAY_MEMMAP		/* at the end of the bootprocess show the memory map */
-#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT	/* show SPD content during boot */
-
-#define CONFIG_SYS_LOAD_ADDR		0x00400000	/* default load address */
-
-/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */
-#define CONFIG_SYS_BUS_CLK		133000000	/* 133 MHz (CPU = 5*Bus = 666MHz)		*/
-
-#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */
-#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 400MHZ -> 5.0 ns, for 133MHZ -> 7.50 ns */
-
-/*ronen - this is the Tclk (MV64360 core) */
-#define CONFIG_SYS_TCLK		133000000
-
-
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_SYS_750FX_HID0		0x8000c084
-#define CONFIG_SYS_750FX_HID1		0x54800000
-#define CONFIG_SYS_750FX_HID2		0x00000000
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-
-/*
- * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
- * To an unused memory region. The stack will remain in cache until RAM
- * is initialized
-*/
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000 /* unused memory region */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-#define RELOCATE_INTERNAL_RAM_ADDR
-#ifdef RELOCATE_INTERNAL_RAM_ADDR
-	#define CONFIG_SYS_INTERNAL_RAM_ADDR	0xf8000000
-#endif
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-/* Dummies for BAT 4-7 */
-#define CONFIG_SYS_SDRAM1_BASE		0x10000000	/* each 256 MByte */
-#define CONFIG_SYS_SDRAM2_BASE		0x20000000
-#define CONFIG_SYS_SDRAM3_BASE		0x30000000
-#define CONFIG_SYS_SDRAM4_BASE		0x40000000
-#define CONFIG_SYS_FLASH_BASE			0xfff00000
-
-#define CONFIG_SYS_DFL_BOOTCS_BASE	0xff800000
-#define CONFIG_VERY_BIG_RAM		/* we will use up to 256M memory for cause we are short of BATS*/
-
-#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */
-#define UART_BASE_BOOTM	      0xfbb00000 /* in order to be sync with the kernel parameters. */
-#define PCI0_IO_BASE_BOOTM    0xfd000000
-
-#define CONFIG_SYS_RESET_ADDRESS		0xfff00100
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
-
-/* areas to map different things with the GT in physical space */
-#define CONFIG_SYS_DRAM_BANKS		4
-
-/* What to put in the bats. */
-#define CONFIG_SYS_MISC_REGION_BASE	0xf0000000
-
-/* Peripheral Device section */
-
-/*******************************************************/
-/* We have on the db64360 Board :		   */
-/* GT-Chipset Register Area				*/
-/* GT-Chipset internal SRAM 256k		    */
-/* SRAM on external device module		   */
-/* Real time clock on external device module	  */
-/* dobble UART on external device module	 */
-/* Data flash on external device module		    */
-/* Boot flash on external device module		    */
-/*******************************************************/
-#define CONFIG_SYS_DFL_GT_REGS		0x14000000				/* boot time GT_REGS */
-#define	 CONFIG_SYS_DB64360_RESET_ADDR 0x14000000				/* After power on Reset the DB64360 is here */
-
-/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-#define CONFIG_SYS_GT_REGS		0xf1000000				/* GT Registers will be mapped here */
-#define CONFIG_SYS_DEV_BASE		0xfc000000				/* GT Devices CS start here */
-
-#define CONFIG_SYS_DEV0_SPACE		CONFIG_SYS_DEV_BASE				/* DEV_CS0 device modul sram */
-#define CONFIG_SYS_DEV1_SPACE		(CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)	/* DEV_CS1 device modul real time clock (rtc) */
-#define CONFIG_SYS_DEV2_SPACE		(CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)	/* DEV_CS2 device modul doubel uart (duart) */
-#define CONFIG_SYS_DEV3_SPACE		(CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)	/* DEV_CS3 device modul large flash */
-
-#define CONFIG_SYS_DEV0_SIZE		 _8M					/* db64360 sram	 @ 0xfc00.0000 */
-#define CONFIG_SYS_DEV1_SIZE		 _8M					/* db64360 rtc	 @ 0xfc80.0000 */
-#define CONFIG_SYS_DEV2_SIZE		_16M					/* db64360 duart @ 0xfd00.0000 */
-#define CONFIG_SYS_DEV3_SIZE		_16M					/* db64360 flash @ 0xfe00.0000 */
-/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-
-/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
-#define CONFIG_SYS_DEV0_PAR		0x8FEFFFFF				/* 32Bit  sram */
-#define CONFIG_SYS_DEV1_PAR		0x8FCFFFFF				/* 8Bit	 rtc */
-#define CONFIG_SYS_DEV2_PAR		0x8FCFFFFF				/* 8Bit duart */
-#define CONFIG_SYS_8BIT_BOOT_PAR	0x8FCFFFFF				/* 8Bit flash */
-#define CONFIG_SYS_32BIT_BOOT_PAR	0x8FEFFFFF				/* 32Bit flash */
-
-	/*   c	  4    a      8	    2	  4    1      c		*/
-	/* 33 22|2222|22 22|111 1|11 11|1 1  |	  |		*/
-	/* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210	*/
-	/* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100	*/
-	/*  3| 0|.... ..| 2| 4 |  0 |  4 |  8  |  3  | 4	*/
-
-
-/* ronen - update MPP Control MV64360*/
-#define CONFIG_SYS_MPP_CONTROL_0	0x02222222
-#define CONFIG_SYS_MPP_CONTROL_1	0x11333011
-#define CONFIG_SYS_MPP_CONTROL_2	0x40431111
-#define CONFIG_SYS_MPP_CONTROL_3	0x00000044
-
-/*# define CONFIG_SYS_SERIAL_PORT_MUX	0x00000102	 0=hiZ	1=MPSC0 2=ETH 0 and 2 RMII */
-
-
-# define CONFIG_SYS_GPP_LEVEL_CONTROL	0x2c600000	/* 1111 1001 0000 1111 1100 0000 0000 0000*/
-							/* gpp[31]		gpp[30]		gpp[29]		gpp[28] */
-				/* gpp[27]			gpp[24]*/
-							/* gpp[19:14] */
-
-/* setup new config_value for MV64360 DDR-RAM !! */
-# define CONFIG_SYS_SDRAM_CONFIG	0x58200400	/* 0x1400  copied from Dink32 bzw. VxWorks*/
-
-#define CONFIG_SYS_DUART_IO		CONFIG_SYS_DEV2_SPACE
-#define CONFIG_SYS_DUART_CHAN		1		/* channel to use for console */
-#define CONFIG_SYS_INIT_CHAN1
-#define CONFIG_SYS_INIT_CHAN2
-
-#define SRAM_BASE		CONFIG_SYS_DEV0_SPACE
-#define SRAM_SIZE		0x00100000		/* 1 MB of sram */
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-
-#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
-#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-#define CONFIG_EEPRO100			/* ronen - Support for Intel 82557/82559/82559ER chips */
-
-/* PCI MEMORY MAP section */
-#define CONFIG_SYS_PCI0_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI0_MEM_SIZE	_128M
-#define CONFIG_SYS_PCI1_MEM_BASE	0x88000000
-#define CONFIG_SYS_PCI1_MEM_SIZE	_128M
-
-#define CONFIG_SYS_PCI0_0_MEM_SPACE	(CONFIG_SYS_PCI0_MEM_BASE)
-#define CONFIG_SYS_PCI1_0_MEM_SPACE	(CONFIG_SYS_PCI1_MEM_BASE)
-
-/* PCI I/O MAP section */
-#define CONFIG_SYS_PCI0_IO_BASE	0xfa000000
-#define CONFIG_SYS_PCI0_IO_SIZE	_16M
-#define CONFIG_SYS_PCI1_IO_BASE	0xfb000000
-#define CONFIG_SYS_PCI1_IO_SIZE	_16M
-
-#define CONFIG_SYS_PCI0_IO_SPACE	(CONFIG_SYS_PCI0_IO_BASE)
-#define CONFIG_SYS_PCI0_IO_SPACE_PCI	(CONFIG_SYS_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */
-#define CONFIG_SYS_PCI1_IO_SPACE	(CONFIG_SYS_PCI1_IO_BASE)
-#define CONFIG_SYS_PCI1_IO_SPACE_PCI	(CONFIG_SYS_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */
-
-#if defined (CONFIG_750CX)
-#define CONFIG_SYS_PCI_IDSEL 0x0
-#else
-#define CONFIG_SYS_PCI_IDSEL 0x30
-#endif
-/*----------------------------------------------------------------------
- * Initial BAT mappings
- */
-
-/* NOTES:
- * 1) GUARDED and WRITE_THRU not allowed in IBATS
- * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
- */
-
-/* SDRAM */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* init ram */
-#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
-
-/* PCI0, PCI1 in one BAT */
-#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
-#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* GT regs, bootrom, all the devices, PCI I/O */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/* I2C addresses for the two DIMM SPD chips */
-#define DIMM0_I2C_ADDR	0x56
-#define DIMM1_I2C_ADDR	0x54
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8<<20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
-#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip */
-
-#define CONFIG_SYS_EXTRA_FLASH_DEVICE	DEVICE3 /* extra flash at device 3 */
-#define CONFIG_SYS_EXTRA_FLASH_WIDTH	4	/* 32 bit */
-#define CONFIG_SYS_BOOT_FLASH_WIDTH	1	/* 8 bit */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT	500	/* Timeout for Flash Lock (in ms) */
-#define CONFIG_SYS_FLASH_CFI		1
-
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE	0x10000
-#define CONFIG_ENV_ADDR	      0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
-/* #define CONFIG_ENV_ADDR	   (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * L2CR setup -- make sure this is right for your board!
- * look in include/mpc74xx.h for the defines used here
- */
-
-#define CONFIG_SYS_L2
-
-
-#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
-#define L2_INIT 0
-#else
-
-#define L2_INIT		0
-/*
-#define L2_INIT		(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
-			L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
-*/
-#endif
-
-#define L2_ENABLE	(L2_INIT | L2CR_L2E)
-
-#define CONFIG_SYS_BOARD_ASM_INIT	1
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/DB64460.h b/include/configs/DB64460.h
deleted file mode 100644
index abc443499c2..00000000000
--- a/include/configs/DB64460.h
+++ /dev/null
@@ -1,517 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* This define must be before the core.h include */
-#define CONFIG_DB64460		1	/* this is an DB64460 board	*/
-
-#ifndef __ASSEMBLY__
-#include "../board/Marvell/include/core.h"
-#endif
-
-/*-----------------------------------------------------*/
-/*    #include "../board/db64460/local.h"	      */
-#ifndef __LOCAL_H
-#define __LOCAL_H
-
-#define CONFIG_ETHADDR		64:46:00:00:00:01
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR		64:46:00:00:00:02
-#define CONFIG_HAS_ETH2
-#define CONFIG_ETH2ADDR		64:46:00:00:00:03
-
-#define CONFIG_ENV_OVERWRITE
-#endif	/* __CONFIG_H */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_74xx			/* we have a 750FX (override local.h) */
-
-#define CONFIG_DB64460		1	/* this is an DB64460 board	*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xfff00000
-
-#define CONFIG_BAUDRATE		115200	/* console baudrate = 115000	*/
-/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the
-	DRAM for ECC in the phase we are relocating to it, which isn't so sufficient.
-	so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase,
-	see sdram_init.c   */
-#undef CONFIG_ECC	 /* enable ECC support */
-#define CONFIG_MV64460_ECC
-
-/* which initialization functions to call for this board */
-#define CONFIG_MISC_INIT_R     /* initialize the icache L1 */
-#define CONFIG_BOARD_EARLY_INIT_F
-
-#define CONFIG_SYS_BOARD_NAME		"DB64460"
-#define CONFIG_IDENT_STRING	"Marvell DB64460 (1.0)"
-
-/*#define CONFIG_SYS_HUSH_PARSER */
-#undef CONFIG_SYS_HUSH_PARSER
-
-
-/*
- * The following defines let you select what serial you want to use
- * for your console driver.
- *
- * what to do:
- * to use the DUART, undef CONFIG_MPSC.	 If you have hacked a serial
- * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
- * to 0 below.
- *
- * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
- * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
- */
-
-#define CONFIG_MPSC_PORT	0
-
-/* to change the default ethernet port, use this define (options: 0, 1, 2) */
-#define MV_ETH_DEVS 3
-
-/* #undef CONFIG_ETHER_PORT_MII	 */
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds	*/
-#endif
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-
-#undef	CONFIG_BOOTARGS
-/*#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */
-
-/* ronen - autoboot using tftp */
-#if (CONFIG_BOOTDELAY >= 0)
-#define CONFIG_BOOTCOMMAND	"tftpboot 0x400000 uImage;\
- setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \
- ip=${ipaddr}:${serverip}${bootargs_end};  bootm 0x400000; "
-
-#define CONFIG_BOOTARGS "console=ttyS0,115200"
-
-#endif
-
-/* ronen - the u-boot.bin should be ~0x30000 bytes */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-     "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \
-cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \
-      "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \
-cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \
-      "bootargs_root=root=/dev/nfs rw\0" \
-      "bootargs_end=:::DB64460:eth0:none \0"\
-      "ethprime=mv_enet0\0"\
-      "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \
-ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
-
-/* --------------------------------------------------------------------------------------------------------------- */
-/* New bootcommands for Marvell DB64460 c 2002 Ingo Assmus */
-
-#define CONFIG_IPADDR		10.2.40.90
-
-#define CONFIG_SERIAL		"No. 1"
-#define CONFIG_SERVERIP		10.2.1.126
-#define CONFIG_ROOTPATH		"/mnt/yellow_dog_mini"
-
-
-#define CONFIG_TESTDRAMDATA	y
-#define CONFIG_TESTDRAMADDRESS	n
-#define CONFIG_TESETDRAMWALK	n
-
-/* --------------------------------------------------------------------------------------------------------------- */
-
-#define CONFIG_LOADS_ECHO	0	/* echo off for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-#undef	CONFIG_ALTIVEC			/* undef to disable		*/
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV		"nor1"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-
-/* Use first bank for JFFS2, second bank contains U-Boot.
- *
- * Note: fake mtd_id's used, no linux mtd map file.
- */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT		"nor1=db64460-1"
-#define MTDPARTS_DEFAULT	"mtdparts=db64460-1:-(jffs2)"
-*/
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_NET
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
-#define CONFIG_SYS_I2C_SPEED	40000		/* I2C speed default */
-
-/* #define CONFIG_SYS_GT_DUAL_CPU	 also for JTAG even with one cpu */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-/*#define CONFIG_SYS_MEMTEST_START	0x00400000	 memtest works on	*/
-/*#define CONFIG_SYS_MEMTEST_END		0x00C00000	 4 ... 12 MB in DRAM	*/
-/*#define CONFIG_SYS_MEMTEST_END		0x07c00000	 4 ... 124 MB in DRAM	*/
-
-/*
-#define CONFIG_SYS_DRAM_TEST
- * DRAM tests
- *   CONFIG_SYS_DRAM_TEST - enables the following tests.
- *
- *   CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines
- *			  Environment variable 'test_dram_data' must be
- *			  set to 'y'.
- *   CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
- *			  addressable. Environment variable
- *			  'test_dram_address' must be set to 'y'.
- *   CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
- *			  This test takes about 6 minutes to test 64 MB.
- *			  Environment variable 'test_dram_walk' must be
- *			  set to 'y'.
- */
-#define CONFIG_SYS_DRAM_TEST
-#if defined(CONFIG_SYS_DRAM_TEST)
-#define CONFIG_SYS_MEMTEST_START		0x00400000	/* memtest works on	*/
-/* #define CONFIG_SYS_MEMTEST_END		0x00C00000	 4 ... 12 MB in DRAM	*/
-#define CONFIG_SYS_MEMTEST_END		0x07c00000	/* 4 ... 124 MB in DRAM */
-#define CONFIG_SYS_DRAM_TEST_DATA
-#define CONFIG_SYS_DRAM_TEST_ADDRESS
-#define CONFIG_SYS_DRAM_TEST_WALK
-#endif /* CONFIG_SYS_DRAM_TEST */
-
-#undef CONFIG_DISPLAY_MEMMAP		/* at the end of the bootprocess show the memory map */
-#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT	/* show SPD content during boot */
-
-#define CONFIG_SYS_LOAD_ADDR		0x00400000	/* default load address */
-
-/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */
-#define CONFIG_SYS_BUS_CLK		133000000	/* 133 MHz (CPU = 5*Bus = 666MHz)		*/
-
-#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */
-#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 200MHZ -> 5.0 ns, 166MHZ -> 6.0, 133MHZ -> 7.50 ns */
-
-/*ronen - this is the Tclk (MV64460 core) */
-#define CONFIG_SYS_TCLK		133000000
-
-
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_SYS_750FX_HID0		0x8000c084
-#define CONFIG_SYS_750FX_HID1		0x54800000
-#define CONFIG_SYS_750FX_HID2		0x00000000
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-
-/*
- * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
- * To an unused memory region. The stack will remain in cache until RAM
- * is initialized
-*/
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000 /* unused memory region */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-#define RELOCATE_INTERNAL_RAM_ADDR
-#ifdef RELOCATE_INTERNAL_RAM_ADDR
-	#define CONFIG_SYS_INTERNAL_RAM_ADDR	0xf8000000
-#endif
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-/* Dummies for BAT 4-7 */
-#define CONFIG_SYS_SDRAM1_BASE		0x10000000	/* each 256 MByte */
-#define CONFIG_SYS_SDRAM2_BASE		0x20000000
-#define CONFIG_SYS_SDRAM3_BASE		0x30000000
-#define CONFIG_SYS_SDRAM4_BASE		0x40000000
-#define CONFIG_SYS_FLASH_BASE			0xfff00000
-
-#define CONFIG_SYS_DFL_BOOTCS_BASE	0xff800000
-#define CONFIG_VERY_BIG_RAM		/* we will use up to 256M memory for cause we are short of BATS*/
-
-#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */
-#define UART_BASE_BOOTM	      0xfbb00000 /* in order to be sync with the kernel parameters. */
-#define PCI0_IO_BASE_BOOTM    0xfd000000
-
-#define CONFIG_SYS_RESET_ADDRESS		0xfff00100
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
-
-/* areas to map different things with the GT in physical space */
-#define CONFIG_SYS_DRAM_BANKS		4
-
-/* What to put in the bats. */
-#define CONFIG_SYS_MISC_REGION_BASE	0xf0000000
-
-/* Peripheral Device section */
-
-/*******************************************************/
-/* We have on the db64460 Board :		   */
-/* GT-Chipset Register Area				*/
-/* GT-Chipset internal SRAM 256k		    */
-/* SRAM on external device module		   */
-/* Real time clock on external device module	  */
-/* dobble UART on external device module	 */
-/* Data flash on external device module		    */
-/* Boot flash on external device module		    */
-/*******************************************************/
-#define CONFIG_SYS_DFL_GT_REGS		0x14000000				/* boot time GT_REGS */
-#define	 CONFIG_SYS_DB64460_RESET_ADDR 0x14000000				/* After power on Reset the DB64460 is here */
-
-/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-#define CONFIG_SYS_GT_REGS		0xf1000000				/* GT Registers will be mapped here */
-#define CONFIG_SYS_DEV_BASE		0xfc000000				/* GT Devices CS start here */
-
-#define CONFIG_SYS_DEV0_SPACE		CONFIG_SYS_DEV_BASE				/* DEV_CS0 device modul sram */
-#define CONFIG_SYS_DEV1_SPACE		(CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)	/* DEV_CS1 device modul real time clock (rtc) */
-#define CONFIG_SYS_DEV2_SPACE		(CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)	/* DEV_CS2 device modul doubel uart (duart) */
-#define CONFIG_SYS_DEV3_SPACE		(CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)	/* DEV_CS3 device modul large flash */
-
-#define CONFIG_SYS_DEV0_SIZE		 _8M					/* db64460 sram	 @ 0xfc00.0000 */
-#define CONFIG_SYS_DEV1_SIZE		 _8M					/* db64460 rtc	 @ 0xfc80.0000 */
-#define CONFIG_SYS_DEV2_SIZE		_16M					/* db64460 duart @ 0xfd00.0000 */
-#define CONFIG_SYS_DEV3_SIZE		_16M					/* db64460 flash @ 0xfe00.0000 */
-/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-
-/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
-#define CONFIG_SYS_DEV0_PAR		0x8FEFFFFF				/* 32Bit  sram */
-#define CONFIG_SYS_DEV1_PAR		0x8FCFFFFF				/* 8Bit	 rtc */
-#define CONFIG_SYS_DEV2_PAR		0x8FCFFFFF				/* 8Bit duart */
-#define CONFIG_SYS_8BIT_BOOT_PAR	0x8FCFFFFF				/* 8Bit flash */
-#define CONFIG_SYS_32BIT_BOOT_PAR	0x8FEFFFFF				/* 32Bit flash */
-
-	/*   c	  4    a      8	    2	  4    1      c		*/
-	/* 33 22|2222|22 22|111 1|11 11|1 1  |	  |		*/
-	/* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210	*/
-	/* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100	*/
-	/*  3| 0|.... ..| 2| 4 |  0 |  4 |  8  |  3  | 4	*/
-
-
-/* ronen - update MPP Control MV64460*/
-#define CONFIG_SYS_MPP_CONTROL_0	0x02222222
-#define CONFIG_SYS_MPP_CONTROL_1	0x11333011
-#define CONFIG_SYS_MPP_CONTROL_2	0x40431111
-#define CONFIG_SYS_MPP_CONTROL_3	0x00000044
-
-/*# define CONFIG_SYS_SERIAL_PORT_MUX	0x00000102	 0=hiZ	1=MPSC0 2=ETH 0 and 2 RMII */
-
-
-# define CONFIG_SYS_GPP_LEVEL_CONTROL	0x2c600000	/* 1111 1001 0000 1111 1100 0000 0000 0000*/
-							/* gpp[31]		gpp[30]		gpp[29]		gpp[28] */
-				/* gpp[27]			gpp[24]*/
-							/* gpp[19:14] */
-
-/* setup new config_value for MV64460 DDR-RAM !! */
-# define CONFIG_SYS_SDRAM_CONFIG	0x58200400	/* 0x1400  copied from Dink32 bzw. VxWorks*/
-
-#define CONFIG_SYS_DUART_IO		CONFIG_SYS_DEV2_SPACE
-#define CONFIG_SYS_DUART_CHAN		1		/* channel to use for console */
-#define CONFIG_SYS_INIT_CHAN1
-#define CONFIG_SYS_INIT_CHAN2
-
-#define SRAM_BASE		CONFIG_SYS_DEV0_SPACE
-#define SRAM_SIZE		0x00100000		/* 1 MB of sram */
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-
-#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
-#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-#define CONFIG_EEPRO100			/* ronen - Support for Intel 82557/82559/82559ER chips */
-
-/* PCI MEMORY MAP section */
-#define CONFIG_SYS_PCI0_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI0_MEM_SIZE	_128M
-#define CONFIG_SYS_PCI1_MEM_BASE	0x88000000
-#define CONFIG_SYS_PCI1_MEM_SIZE	_128M
-
-#define CONFIG_SYS_PCI0_0_MEM_SPACE	(CONFIG_SYS_PCI0_MEM_BASE)
-#define CONFIG_SYS_PCI1_0_MEM_SPACE	(CONFIG_SYS_PCI1_MEM_BASE)
-
-/* PCI I/O MAP section */
-#define CONFIG_SYS_PCI0_IO_BASE	0xfa000000
-#define CONFIG_SYS_PCI0_IO_SIZE	_16M
-#define CONFIG_SYS_PCI1_IO_BASE	0xfb000000
-#define CONFIG_SYS_PCI1_IO_SIZE	_16M
-
-#define CONFIG_SYS_PCI0_IO_SPACE	(CONFIG_SYS_PCI0_IO_BASE)
-#define CONFIG_SYS_PCI0_IO_SPACE_PCI	(CONFIG_SYS_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */
-#define CONFIG_SYS_PCI1_IO_SPACE	(CONFIG_SYS_PCI1_IO_BASE)
-#define CONFIG_SYS_PCI1_IO_SPACE_PCI	(CONFIG_SYS_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */
-
-#if defined (CONFIG_750CX)
-#define CONFIG_SYS_PCI_IDSEL 0x0
-#else
-#define CONFIG_SYS_PCI_IDSEL 0x30
-#endif
-/*----------------------------------------------------------------------
- * Initial BAT mappings
- */
-
-/* NOTES:
- * 1) GUARDED and WRITE_THRU not allowed in IBATS
- * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
- */
-
-/* SDRAM */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* init ram */
-#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
-
-/* PCI0, PCI1 in one BAT */
-#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
-#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* GT regs, bootrom, all the devices, PCI I/O */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/* I2C addresses for the two DIMM SPD chips */
-#define DIMM0_I2C_ADDR	0x56
-#define DIMM1_I2C_ADDR	0x54
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8<<20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
-#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip */
-
-#define CONFIG_SYS_EXTRA_FLASH_DEVICE	DEVICE3 /* extra flash at device 3 */
-#define CONFIG_SYS_EXTRA_FLASH_WIDTH	4	/* 32 bit */
-#define CONFIG_SYS_BOOT_FLASH_WIDTH	1	/* 8 bit */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT	500	/* Timeout for Flash Lock (in ms) */
-#define CONFIG_SYS_FLASH_CFI		1
-
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE	0x10000
-#define CONFIG_ENV_ADDR	      0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
-/* #define CONFIG_ENV_ADDR	   (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * L2CR setup -- make sure this is right for your board!
- * look in include/mpc74xx.h for the defines used here
- */
-
-#define CONFIG_SYS_L2
-
-
-#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
-#define L2_INIT 0
-#else
-
-#define L2_INIT		0
-/*
-#define L2_INIT		(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
-			L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
-*/
-#endif
-
-#define L2_ENABLE	(L2_INIT | L2CR_L2E)
-
-#define CONFIG_SYS_BOARD_ASM_INIT	1
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/HWW1U1A.h b/include/configs/HWW1U1A.h
deleted file mode 100644
index 6a3a11cb7f4..00000000000
--- a/include/configs/HWW1U1A.h
+++ /dev/null
@@ -1,460 +0,0 @@
-/*
- * Copyright 2009-2010 eXMeritus, A Boeing Company
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * HardwareWall HWW-1U-1A airborne unit configuration file
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* High-level system configuration options */
-#define CONFIG_BOOKE		/* Power/PowerPC Book-E			*/
-#define CONFIG_E500		/* e500 (Power ISA v2.03 with SPE)	*/
-#define CONFIG_FSL_ELBC		/* FreeScale Enhanced LocalBus Cntlr	*/
-#define CONFIG_FSL_LAW		/* FreeScale Local Access Window	*/
-#define CONFIG_P2020		/* FreeScale P2020			*/
-#define CONFIG_HWW1U1A		/* eXMeritus HardwareWall HWW-1U-1A	*/
-#define CONFIG_MP		/* Multiprocessing support		*/
-#define CONFIG_HWCONFIG		/* Use hwconfig from environment	*/
-
-#define CONFIG_L2_CACHE			/* L2 cache enabled		*/
-#define CONFIG_BTB			/* Branch predition enabled	*/
-
-#define CONFIG_PANIC_HANG		/* No board reset on panic	*/
-#define CONFIG_BOARD_EARLY_INIT_R	/* Call board_early_init_r()	*/
-#define CONFIG_CMD_REGINFO		/* Dump various CPU regs	*/
-
-/*
- * Allow the use of 36-bit physical addresses.  Device-trees with 64-bit
- * addresses have known compatibility issues with some existing kernels.
- */
-#define CONFIG_ENABLE_36BIT_PHYS
-#define CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* Number of entries in TLB1 */
-
-/* Reserve plenty of RAM for malloc (we have 2GB+) */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
-
-/* How much L2 cache do we map so we can use it as RAM */
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-/* This is our temporary global data area just above the stack */
-#define CONFIG_SYS_GBL_DATA_OFFSET \
-	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/* The stack grows down from the global data area */
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/* Enable IRQs and watchdog with a 1000Hz system decrementer */
-#define CONFIG_CMD_IRQ
-
-/* -------------------------------------------------------------------- */
-
-/*
- * Clock crystal configuration:
- *  (1) SYS: 66.666MHz +/- 50ppm (drives CPU/PCI/DDR)
- *  (2) CCB: Multiplier from SYS_CLK
- *  (3) RTC: 25.000MHz +/- 50ppm (sampled against CCB clock)
- */
-#define CONFIG_SYS_CLK_FREQ 66666000/*Hz*/
-#define CONFIG_DDR_CLK_FREQ 66666000/*Hz*/
-
-
-/* -------------------------------------------------------------------- */
-
-/*
- * Memory map
- *
- * 0x0000_0000  0x7fff_ffff    2G  DDR2 ECC SDRAM
- * 0x8000_0000  0x9fff_ffff  512M  PCI-E Bus 1
- * 0xa000_0000  0xbfff_ffff  512M  PCI-E Bus 2 (unused)
- * 0xc000_0000  0xdfff_ffff  512M  PCI-E Bus 3
- * 0xe000_0000  0xe7ff_ffff  128M  Spansion FLASH
- * 0xe800_0000  0xefff_ffff  128M  Spansion FLASH
- * 0xffd0_0000  0xffd0_3fff   16K  L1 boot stack (TLB0)
- * 0xffe0_0000  0xffef_ffff    1M  CCSR
- * 0xffe0_5000  0xffe0_5fff    4K    Enhanced LocalBus Controller
- */
-
-/* Virtual Memory Map */
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_PCIE3_MEM_VIRT	0x80000000
-#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
-#define CONFIG_SYS_FLASH_BASE		0xe0000000
-#define CONFIG_SYS_PCIE3_IO_VIRT	0xffc00000
-#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
-#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
-#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000
-#define CONFIG_SYS_CCSRBAR		0xffe00000 /* CCSRBAR @ runtime */
-
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000 /* 64k */
-
-/* Physical Memory Map */
-#define CONFIG_SYS_PCIE3_MEM_PHYS     0xc00000000ull
-#define CONFIG_SYS_PCIE2_MEM_PHYS     0xc20000000ull
-#define CONFIG_SYS_PCIE1_MEM_PHYS     0xc40000000ull
-#define CONFIG_SYS_FLASH_BASE_PHYS    0xfe0000000ull
-#define CONFIG_SYS_PCIE3_IO_PHYS      0xfffc00000ull
-#define CONFIG_SYS_PCIE2_IO_PHYS      0xfffc10000ull
-#define CONFIG_SYS_PCIE1_IO_PHYS      0xfffc20000ull
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfffd00000ull
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf		/* for ASM code */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW  0xffd00000	/* for ASM code */
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH       0xf		/* for ASM code */
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW        0xffe00000	/* for ASM code */
-
-
-/* -------------------------------------------------------------------- */
-
-/* U-Boot image (MONITOR_BASE == TEXT_BASE) */
-#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc /* Top address in flash */
-#define CONFIG_SYS_TEXT_BASE		0xeff80000 /* Start of U-Boot image */
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		0x80000 /* 512kB (4 flash sectors) */
-
-/*
- * U-Boot Environment Image:  The two sectors immediately below U-Boot
- * form the U-Boot environment (regular and redundant).
- */
-#define CONFIG_ENV_IS_IN_FLASH	/* The environment image is stored in FLASH */
-#define CONFIG_ENV_OVERWRITE	/* Allow "protected" variables to be erased */
-#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128kB (1 flash sector) */
-#define CONFIG_ENV_ADDR        (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR         - CONFIG_ENV_SECT_SIZE)
-
-/* Only use 8kB of each environment sector for data */
-#define CONFIG_ENV_SIZE		0x2000 /* 8kB */
-#define CONFIG_ENV_SIZE_REDUND	0x2000 /* 8kB */
-
-
-/* -------------------------------------------------------------------- */
-
-/* Serial Console Configuration */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
-
-/* Echo back characters received during a serial download */
-#define CONFIG_LOADS_ECHO
-
-/* Allow a serial-download to temporarily change baud */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE
-
-
-/* -------------------------------------------------------------------- */
-
-/* PCI and PCI-Express Support */
-#define CONFIG_PCI		/* Enable PCI/PCIE			*/
-#define CONFIG_PCI_PNP		/* Scan PCI busses			*/
-#define CONFIG_CMD_PCI		/* Enable the "pci" command		*/
-#define CONFIG_FSL_PCI_INIT	/* Common FreeScale PCI initialization	*/
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET	/* We have PCI-E reset errata		*/
-#define CONFIG_SYS_PCI_64BIT	/* PCI resources are 64-bit		*/
-#define CONFIG_PCI_SCAN_SHOW	/* Display PCI scan during boot		*/
-
-/* Enable 2 of the 3 PCI-E controllers */
-#define CONFIG_PCIE3
-#undef  CONFIG_PCIE2
-#define CONFIG_PCIE1
-
-/* Display human-readable names when initializing */
-#define CONFIG_SYS_PCIE3_NAME "Intel 82571EB"
-#define CONFIG_SYS_PCIE2_NAME "Unused"
-#define CONFIG_SYS_PCIE1_NAME "Silicon Image SIL3531"
-
-/*
- * PCI bus addresses
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-#define CONFIG_SYS_PCIE3_IO_BUS  0x00000000
-#define CONFIG_SYS_PCIE2_IO_BUS  0x00000000
-#define CONFIG_SYS_PCIE1_IO_BUS  0x00000000
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-
-
-/* -------------------------------------------------------------------- */
-
-/* Generic FreeScale hardware I2C support */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	400000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED	400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
-#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
-#define CONFIG_CMD_I2C
-
-/* DDR2 SO-RDIMM SPD EEPROM is at I2C0-0x51 */
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define SPD_EEPROM_ADDRESS 0x51
-
-/* DS1339 RTC is at I2C0-0x68 (I know it says "DS1337", it's a DS1339) */
-#define CONFIG_CMD_DATE
-#define CONFIG_RTC_DS1337
-#define CONFIG_SYS_RTC_BUS_NUM 0
-#define CONFIG_SYS_I2C_RTC_ADDR	0x68
-/* Turn off RTC square-wave output to save battery */
-#define CONFIG_SYS_RTC_DS1337_NOOSC
-
-/*
- * AT24C128N EEPROM at I2C0-0x53.
- *
- * That Atmel EEPROM has 128kbit of memory (16kByte) divided into 256 pages
- * of 64 bytes per page.  The chip uses 2-byte addresses and has a max write
- * cycle time of 20ms according to the datasheet.
- *
- * NOTE: Our environment is stored on regular direct-attached FLASH, this
- * chip is only used as a write-protected backup for certain key settings
- * such as the serial# and macaddr values.  (EG: "env import")
- */
-#define CONFIG_CMD_EEPROM
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 1 << 6 == 64 byte pages */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 21
-
-/*
- * PCA9554 is at I2C1-0x3f (I know it says "PCA953X", it's a PCA9554).  You
- * must first select the I2C1 bus with "i2c dev 1" or the "pca953x" command
- * will not be able to access the chip.
- */
-#define CONFIG_PCA953X
-#define CONFIG_CMD_PCA953X
-#define CONFIG_CMD_PCA953X_INFO
-#define CONFIG_SYS_I2C_PCA953X_ADDR 0x3f
-
-
-/* -------------------------------------------------------------------- */
-
-/* FreeScale DDR2/3 SDRAM Controller */
-#define CONFIG_SYS_FSL_DDR2		/* Our SDRAM slot is DDR2		*/
-#define CONFIG_DDR_ECC		/* Enable ECC by default		*/
-#define CONFIG_DDR_SPD		/* Detect DDR config from SPD EEPROM	*/
-#define CONFIG_SPD_EEPROM	/* ...why 2 config variables for this?	*/
-#define CONFIG_VERY_BIG_RAM	/* Allow 2GB+ of RAM			*/
-#define CONFIG_CMD_SDRAM
-
-/* Standard P2020 DDR controller parameters */
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 2
-
-/* Make sure to tell the DDR controller to preinitialze all of RAM */
-#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-
-
-/* -------------------------------------------------------------------- */
-
-/* FLASH Memory Configuration (2x 128MB SPANSION FLASH) */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
-
-/* Flash banks (2x 128MB) */
-#define FLASH0_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000ull)
-#define FLASH1_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x0000000ull)
-#define CONFIG_SYS_MAX_FLASH_BANKS 2
-#define CONFIG_SYS_MAX_FLASH_SECT 1024
-#define CONFIG_SYS_FLASH_BANKS_LIST { FLASH0_PHYS, FLASH1_PHYS }
-
-/*
- * Flash access modes and timings (values are the defaults after a RESET).
- *
- * NOTE: These could probably be optimized but are more than sufficient for
- * this particular system for the moment.
- */
-#define FLASH_BRx (BR_PS_16 | BR_MS_GPCM | BR_V)
-#define FLASH_ORx (OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \
-		| OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
-
-/* Configure both flash banks */
-#define CONFIG_SYS_BR0_PRELIM (FLASH_BRx | BR_PHYS_ADDR(FLASH0_PHYS))
-#define CONFIG_SYS_BR1_PRELIM (FLASH_BRx | BR_PHYS_ADDR(FLASH1_PHYS))
-#define CONFIG_SYS_OR0_PRELIM (FLASH_ORx | OR_AM_128MB)
-#define CONFIG_SYS_OR1_PRELIM (FLASH_ORx | OR_AM_128MB)
-
-/* Flash timeouts (in ms) */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000UL /* Erase (60s)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT   500UL /* Write (0.5s)	*/
-
-/* Quiet flash testing */
-#define CONFIG_SYS_FLASH_QUIET_TEST
-
-/* Make program/erase count down from 45/5 (9....8....7....) */
-#define CONFIG_FLASH_SHOW_PROGRESS 45
-
-
-/* -------------------------------------------------------------------- */
-
-/* Ethernet Device Support */
-#define CONFIG_MII			/* Enable MII PHY code		*/
-#define CONFIG_MII_DEFAULT_TSEC		/* ??? Copied from P2020DS	*/
-#define CONFIG_PHY_GIGE			/* Support Gigabit PHYs		*/
-#define CONFIG_ETHPRIME "e1000#0"	/* Default to external ports	*/
-
-/* Turn on various helpful networking commands */
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-
-/* On-chip FreeScale P2020 "tsec" Ethernet (oneway fibers and peer) */
-#define CONFIG_TSEC_ENET
-#define CONFIG_TSEC1
-#define CONFIG_TSEC2
-#define CONFIG_TSEC3
-#define CONFIG_TSEC1_NAME "owt0"
-#define CONFIG_TSEC2_NAME "owt1"
-#define CONFIG_TSEC3_NAME "peer"
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC3_PHYIDX 0
-#define TSEC1_PHY_ADDR      2
-#define TSEC2_PHY_ADDR      3
-#define TSEC3_PHY_ADDR      4
-#define TSEC3_PHY_ADDR_CPUA 4
-#define TSEC3_PHY_ADDR_CPUB 5
-
-/* PCI-E dual-port E1000 (external ethernet ports) */
-#define CONFIG_E1000
-#define CONFIG_E1000_SPI
-#define CONFIG_E1000_SPI_GENERIC
-#define CONFIG_CMD_E1000
-
-/* We need the SPI infrastructure to poke the E1000's EEPROM */
-#define CONFIG_SPI
-#define CONFIG_SPI_X
-#define CONFIG_CMD_SPI
-#define MAX_SPI_BYTES 32
-
-
-/* -------------------------------------------------------------------- */
-
-/* USB Thumbdrive Device Support */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_USB_STORAGE
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_CMD_USB
-
-/* Partition and Filesystem support */
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-#define CONFIG_ISO_PARTITION
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-
-
-/* -------------------------------------------------------------------- */
-
-/* Command line configuration. */
-#define CONFIG_CMDLINE_EDITING		/* Enable command editing	*/
-#define CONFIG_COMMAND_HISTORY		/* Enable command history	*/
-#define CONFIG_AUTO_COMPLETE		/* Enable command completion	*/
-#define CONFIG_SYS_LONGHELP		/* Enable detailed command help	*/
-#define CONFIG_SYS_MAXARGS 128		/* Up to 128 command-line args	*/
-#define CONFIG_SYS_PBSIZE 8192		/* Allow up to 8k printed lines	*/
-#define CONFIG_SYS_CBSIZE 4096		/* Allow up to 4k command lines	*/
-#define CONFIG_SYS_BARGSIZE 4096	/* Allow up to 4k boot args	*/
-#define CONFIG_SYS_HUSH_PARSER		/* Enable a fancier shell	*/
-
-/* A little extra magic here for the prompt */
-#define CONFIG_SYS_PROMPT hww1u1a_get_ps1()
-#ifndef __ASSEMBLY__
-const char *hww1u1a_get_ps1(void);
-#endif
-
-/* Include a bunch of default commands we probably want */
-#include <config_cmd_default.h>
-
-/* Other helpful shell-like commands */
-#define CONFIG_MD5
-#define CONFIG_SHA1
-#define CONFIG_CMD_MD5SUM
-#define CONFIG_CMD_SHA1SUM
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_SETEXPR
-
-
-/* -------------------------------------------------------------------- */
-
-/* Image manipulation and booting */
-
-/* We use the OpenFirmware-esque "Flattened Device Tree" */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_CMD_ELF
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20)	/* Maximum kernel memory map	*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20)	/* Maximum kernel size of 64MB	*/
-
-/* This is the default address for commands with an optional address arg */
-#define CONFIG_LOADADDR		  100000
-#define CONFIG_SYS_LOAD_ADDR	0x100000
-
-/* Test memory starting from the default load address to just below 2GB */
-#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_LOAD_ADDR
-#define CONFIG_SYS_MEMTEST_END		0x7f000000
-
-#define CONFIG_BOOTDELAY 20
-#define CONFIG_BOOTCOMMAND "echo Not yet flashed"
-#define CONFIG_BOOTARGS ""
-#define CONFIG_BOOTARGS_DYNAMIC "console=ttyS0,${baudrate}n1"
-
-/* Extra environment parameters */
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"ethprime=e1000#0\0"						\
-	"ethrotate=no\0"						\
-	"setbootargs=setenv bootargs "					\
-			"\"${bootargs} "CONFIG_BOOTARGS_DYNAMIC"\"\0"	\
-	"perf_mode=performance\0"					\
-	"hwconfig="	"fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;"	\
-			"usb1:dr_mode=host,phy_type=ulpi\0"		\
-	"flkernel=0xe8000000\0"						\
-	"flinitramfs=0xe8800000\0"					\
-	"fldevicetree=0xeff20000\0"					\
-	"flbootm=bootm ${flkernel} ${flinitramfs} ${fldevicetree}\0"	\
-	"flboot=run preboot; run flbootm\0"				\
-	"restore_eeprom=i2c dev 0 && "					\
-			"eeprom read $loadaddr 0x0000 0x2000 && "	\
-			"env import -c $loadaddr 0x2000\0"
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/ICU862.h b/include/configs/ICU862.h
deleted file mode 100644
index 16af4bbcadf..00000000000
--- a/include/configs/ICU862.h
+++ /dev/null
@@ -1,443 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <mpc8xx_irq.h>
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC860		1
-#define CONFIG_MPC860T		1
-#define CONFIG_ICU862		1
-#define CONFIG_MPC862		1
-
-#define	CONFIG_SYS_TEXT_BASE	0x40F00000
-
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-
-#ifdef CONFIG_100MHz
-#define MPC8XX_FACT		24		/* Multiply by 24	*/
-#define MPC8XX_XIN		4165000		/* 4.165 MHz in		*/
-#define CONFIG_8xx_GCLK_FREQ	(MPC8XX_FACT * MPC8XX_XIN)
-				    /* define if cant' use get_gclk_freq */
-#else
-#if 1				/* for 50MHz version of processor	*/
-#define MPC8XX_FACT		12		/* Multiply by 12	*/
-#define MPC8XX_XIN		4000000		/* 4 MHz in		*/
-#define CONFIG_8xx_GCLK_FREQ	48000000 /* define if cant use get_gclk_freq */
-#else				/* for 80MHz version of processor	*/
-#define MPC8XX_FACT		20		/* Multiply by 20	*/
-#define MPC8XX_XIN		4000000		/* 4 MHz in		*/
-#define CONFIG_8xx_GCLK_FREQ    80000000 /* define if cant use get_gclk_freq */
-#endif
-#endif
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND							\
-	"bootp;"								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
-	"bootm"
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#undef	CONFIG_SCC1_ENET		/* disable SCC1 ethernet */
-#define	CONFIG_FEC_ENET		1	/* use FEC ethernet  */
-#define	CONFIG_MII		1
-#if 1
-#define CONFIG_SYS_DISCOVER_PHY	1
-#else
-#undef	CONFIG_SYS_DISCOVER_PHY
-#endif
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-/* enable I2C and select the hardware/software driver */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED	50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PB_SCL		0x00000020	/* PB 26 */
-#define PB_SDA		0x00000010	/* PB 27 */
-
-#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
-#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
-#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
-#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
-			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
-			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-
-#define CONFIG_SYS_EEPROM_X40430		/* Use a Xicor X40430 EEPROM	*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS  4	/* 16 bytes page write mode	*/
-
-#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#if defined(CONFIG_CMD_KGDB)
-#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0100000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0x00100000
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR		0xF0000000
-#define CONFIG_SYS_IMMR_SIZE		((uint)(64 * 1024))
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define	CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0x40000000
-#define CONFIG_SYS_FLASH_SIZE		((uint)(16 * 1024 * 1024))	/* max 16Mbyte */
-
-#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
-
-#if 0
-#if defined(DEBUG)
-#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#else
-#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#endif
-#else
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#endif
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#define	CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms)	*/
-
-
-#define	CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_OFFSET		0x00F40000
-
-#define CONFIG_ENV_SECT_SIZE	0x40000	/* Total Size of Environment sector	*/
-#define	CONFIG_ENV_SIZE		0x4000	/* Used Size of Environment Sector	*/
-#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control					11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration					11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control					11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
- *-----------------------------------------------------------------------
- * set the PLL, the low-power modes and the reset control (15-29)
- */
-#define CONFIG_SYS_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
-				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#ifdef CONFIG_100MHz	/* for 100 MHz, external bus is half CPU clock */
-#define SCCR_MASK	0
-#define CONFIG_SYS_SCCR	(SCCR_TBS	| SCCR_COM00	| SCCR_DFSYNC00	| \
-			 SCCR_DFBRG00	| SCCR_DFNL000	| SCCR_DFNH000	| \
-			 SCCR_DFLCD000	|SCCR_DFALCD00	| SCCR_EBDF01)
-#else			/* up to 50 MHz we use a 1:1 clock */
-#define SCCR_MASK	SCCR_EBDF11
-#define CONFIG_SYS_SCCR	(SCCR_TBS	| SCCR_COM00	| SCCR_DFSYNC00	| \
-			 SCCR_DFBRG00	| SCCR_DFNL000	| SCCR_DFNH000	| \
-			 SCCR_DFLCD000	|SCCR_DFALCD00	)
-#endif	/* CONFIG_100MHz */
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration Register		19-4
- *-----------------------------------------------------------------------
- */
-/* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */
-#define CONFIG_SYS_RCCR 0x0020
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * PCMCIA Power Switch
- *
- * The ICU862 uses a TPS2205 PC-Card Power-Interface Switch to
- * control the voltages on the PCMCIA slot which is connected to Port B
- *-----------------------------------------------------------------------
- */
-			/* Output pins */
-#define TPS2205_VCC5	0x00008000	/* PB.16:  5V Voltage Control	*/
-#define TPS2205_VCC3	0x00004000	/* PB.17:  3V Voltage Control	*/
-#define TPS2205_VPP_PGM	0x00002000	/* PB.18: PGM Voltage Control	*/
-#define TPS2205_VPP_VCC	0x00001000	/* PB.19: VPP Voltage Control	*/
-#define TPS2205_SHDN	0x00000200	/* PB.22: Shutdown		*/
-#define TPS2205_OUTPUTS ( TPS2205_VCC5    | TPS2205_VCC3    | \
-			  TPS2205_VPP_PGM | TPS2205_VPP_VCC | \
-			  TPS2205_SHDN)
-
-			/* Input pins */
-#define TPS2205_OC	0x00000100	/* PB.23: Over-Current		*/
-#define TPS2205_INPUTS	( TPS2205_OC )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
-#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
-
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
-#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
-
-#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O			*/
-#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses	*/
-#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers	*/
-#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
-
-
- /*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER		0
-
-/* Because of the way the 860 starts up and assigns CS0 the
-* entire address space, we have to set the memory controller
-* differently.  Normally, you write the option register
-* first, and then enable the chip select by writing the
-* base register.  For CS0, you must write the base register
-* first, followed by the option register.
-*/
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0x0		/* FLASH bank #1	*/
-
-#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
-
-/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
-#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
-
-#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
-
-#define CONFIG_SYS_OR0_PRELIM	0xFF000954		/* Real values for the board */
-#define CONFIG_SYS_BR0_PRELIM	0x40000001		/* Real values for the board */
-
-/*
- * BR1 and OR1 (SDRAM)
- */
-#define SDRAM_BASE1_PRELIM	0x00000000	/* SDRAM bank		*/
-#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
-
-#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000800	/* BIH is not set	*/
-
-#define CONFIG_SYS_OR1_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM)
-#define CONFIG_SYS_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA		97	/* start with divider for 100 MHz	*/
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-
-#define CONFIG_SYS_MAMR		0x13a01114
-
-#ifdef CONFIG_MPC860T
-
-/* Interrupt level assignments.
-*/
-#define FEC_INTERRUPT	SIU_LEVEL1	/* FEC interrupt */
-
-#endif /* CONFIG_MPC860T */
-
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h
deleted file mode 100644
index 8ccb0ff9d89..00000000000
--- a/include/configs/IDS8247.h
+++ /dev/null
@@ -1,462 +0,0 @@
-/*
- * (C) Copyright 2005
- * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8272_FAMILY	1
-#define CONFIG_IDS8247		1
-#define CPU_ID_STR		"MPC8247"
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-#define	CONFIG_SYS_TEXT_BASE	0xfff00000
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define	CONFIG_BOOTCOUNT_LIMIT
-
-#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw "			\
-	"console=ttyS0,115200\0"					\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"flash_nfs=run nfsargs addip;"					\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip;"					\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
-	"rootpath=/opt/eldk/ppc_82xx\0"					\
-	"bootfile=/tftpboot/IDS8247/uImage\0"				\
-	"kernel_addr=ff800000\0"					\
-	"ramdisk_addr=ffa00000\0"					\
-	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#define CONFIG_MISC_INIT_R	1
-
-/* enable I2C and select the hardware/software driver */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED	400000
-#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
-/*
- * Software (bit-bang) I2C driver configuration
- */
-
-#define I2C_PORT	0		/* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE	(iop->pdir |=  0x00000080)
-#define I2C_TRISTATE	(iop->pdir &= ~0x00000080)
-#define I2C_READ	((iop->pdat & 0x00000080) != 0)
-#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00000080; \
-			else    iop->pdat &= ~0x00000080
-#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00000100; \
-			else    iop->pdat &= ~0x00000100
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-
-#if 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
-
-#define CONFIG_I2C_X
-#endif
-
-/*
- * select serial console configuration
- * use the extern UART for the console
- */
-#define	CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		115200
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-
-#define CONFIG_SYS_NS16550_REG_SIZE    1
-
-#define CONFIG_SYS_NS16550_CLK         14745600
-
-#define	CONFIG_SYS_UART_BASE	0xE0000000
-#define CONFIG_SYS_UART_SIZE	0x10000
-
-#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_UART_BASE + 0x8000)
-
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
-#define OF_TBCLK	(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH	"/soc@f0000000/serial8250@e0008000"
-
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
-#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
-#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
-#define	CONFIG_ETHER_INDEX	1	/* which SCC/FCC channel for ethernet */
-#define CONFIG_ETHER_ON_FCC1
-#define FCC_ENET
-
-/*
- * - Rx-CLK is CLK10
- * - Tx-CLK is CLK9
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK1	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9)
-# define CONFIG_SYS_CPMFCR_RAMTYPE	0
-# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#define CONFIG_8260_CLKIN	66666666	/* in Hz */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#define CONFIG_RTC_PCF8563
-#define CONFIG_SYS_I2C_RTC_ADDR		0x51
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_SNTP
-
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#if defined(CONFIG_CMD_KGDB)
-#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define	CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address	*/
-
-#define	CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
-
-#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible  */
-#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver        */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ 0xFF800000 }
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks	      */
-/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ids8247/config.mk
- * The main FLASH is whichever is connected to *CS0.
- */
-#define CONFIG_SYS_FLASH0_BASE 0xFFF00000
-#define CONFIG_SYS_FLASH0_SIZE 8
-
-/* Flash bank size (for preliminary settings)
- */
-#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-
-/* Environment in flash */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+0x60000)
-#define CONFIG_ENV_SIZE		0x20000
-#define CONFIG_ENV_SECT_SIZE	0x20000
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-#if defined(CONFIG_CMD_NAND)
-
-#define CONFIG_SYS_NAND0_BASE 0xE1000000
-#define CONFIG_SYS_MAX_NAND_DEVICE     1       /* Max number of NAND devices           */
-
-#endif /* CONFIG_CMD_NAND */
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
- */
-#define CONFIG_SYS_HRCW_MASTER	(HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000)
-
-/* no slaves so just fill with zeros */
-#define CONFIG_SYS_HRCW_SLAVE1		0
-#define CONFIG_SYS_HRCW_SLAVE2		0
-#define CONFIG_SYS_HRCW_SLAVE3		0
-#define CONFIG_SYS_HRCW_SLAVE4		0
-#define CONFIG_SYS_HRCW_SLAVE5		0
-#define CONFIG_SYS_HRCW_SLAVE6		0
-#define CONFIG_SYS_HRCW_SLAVE7		0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR		0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE	0x2000  /* Size of used area in DPRAM    */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- *
- * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers                    2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-
-#define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI)
-#define CONFIG_SYS_HID0_FINAL  0
-#define CONFIG_SYS_HID2        0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register                                     5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CONFIG_SYS_RMR         0
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration                                       4-25
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_BCR		0
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration                             4-31
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SIUMCR      (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01)
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control                             4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control                     4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control                 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control                                   9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CONFIG_SYS_SCCR        (0x00000028 | SCCR_DFBRG01)
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration                         13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR        0
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus     Machine PortSz  Device
- * ---- ---     ------- ------  ------
- *  0   60x     GPCM    16 bit  FLASH
- *  1   60x     GPCM     8 bit  NAND
- *  2   60x     SDRAM   32 bit  SDRAM
- *  3   60x     GPCM     8 bit  UART
- *
- */
-
-#define SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
-
-/* Minimum mask to separate preliminary
- * address ranges for CS[0:2]
- */
-#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT	(32<<20)	/* less than 32 MB */
-
-#define CONFIG_SYS_MPTPR       0x6600
-
-/*-----------------------------------------------------------------------------
- * Address for Mode Register Set (MRS) command
- *-----------------------------------------------------------------------------
- */
-#define CONFIG_SYS_MRS_OFFS	0x00000110
-
-
-/* Bank 0 - FLASH
- */
-#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
-			 BRx_PS_8                       |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
-			 ORxG_SCY_6_CLK                 )
-
-#if defined(CONFIG_CMD_NAND)
-/* Bank 1 - NAND Flash
-*/
-#define	CONFIG_SYS_NAND_BASE		CONFIG_SYS_NAND0_BASE
-#define	CONFIG_SYS_NAND_SIZE		0x8000
-
-#define CONFIG_SYS_OR_TIMING_NAND	0x000036
-
-#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V  )
-#define CONFIG_SYS_OR1_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | CONFIG_SYS_OR_TIMING_NAND )
-#endif
-
-/* Bank 2 - 60x bus SDRAM
- */
-#define CONFIG_SYS_PSRT        0x20
-#define CONFIG_SYS_LSRT        0x20
-
-#define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
-			 BRx_PS_32                      |\
-			 BRx_MS_SDRAM_P                 |\
-			 BRx_V)
-
-#define CONFIG_SYS_OR2_PRELIM	CONFIG_SYS_OR2
-
-
-/* SDRAM initialization values
-*/
-#define CONFIG_SYS_OR2    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI0_A9		|\
-			 ORxS_NUMR_12)
-
-#define CONFIG_SYS_PSDMR  (PSDMR_SDAM_A14_IS_A5 |\
-			 PSDMR_BSMA_A15_A17           |\
-			 PSDMR_SDA10_PBI0_A10		|\
-			 PSDMR_RFRC_5_CLK               |\
-			 PSDMR_PRETOACT_2W              |\
-			 PSDMR_ACTTORW_2W               |\
-			 PSDMR_BL                       |\
-			 PSDMR_LDOTOPRE_2C              |\
-			 PSDMR_WRC_3C                   |\
-			 PSDMR_CL_3)
-
-/* Bank 3 - UART
-*/
-
-#define CONFIG_SYS_BR3_PRELIM  ((CONFIG_SYS_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V  )
-#define CONFIG_SYS_OR3_PRELIM  (((-CONFIG_SYS_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX )
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/MHPC.h b/include/configs/MHPC.h
deleted file mode 100644
index d45be0f609a..00000000000
--- a/include/configs/MHPC.h
+++ /dev/null
@@ -1,369 +0,0 @@
-/*
- * (C) Copyright 2001
- * Frank Gottschling, ELTEC Elektronik AG, fgottschling@eltec.de
- *
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Configuation settings for the miniHiPerCam.
- *
- * -----------------------------------------------------------------
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
-#define CONFIG_MHPC		1	/* on a miniHiPerCam		*/
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* do special hardware init.	*/
-#define CONFIG_MISC_INIT_R	1
-
-#define	CONFIG_SYS_TEXT_BASE	0xfe000000
-
-#define CONFIG_8xx_GCLK_FREQ	MPC8XX_SPEED
-#undef	CONFIG_8xx_CONS_SMC1
-#define CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-
-#define CONFIG_ENV_OVERWRITE	1
-#define CONFIG_ETHADDR		00:00:5b:ee:de:ad
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND	\
-	"bootp;"								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
-	"bootm"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-#define CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
-
-#undef	CONFIG_UCODE_PATCH
-
-/* enable I2C and select the hardware/software driver */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED	50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PB_SCL		0x00000020	/* PB 26 */
-#define PB_SDA		0x00000010	/* PB 27 */
-
-#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
-#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
-#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
-#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
-			else	immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
-			else	immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* EEPROM X24C04		*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1	/* bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
-
-#define LCD_VIDEO_ADDR		(SDRAM_MAX_SIZE-SDRAM_RES_SIZE)
-#define LCD_VIDEO_SIZE		SDRAM_RES_SIZE	/* 2MB */
-#define LCD_VIDEO_COLS		640
-#define LCD_VIDEO_ROWS		480
-#define LCD_VIDEO_FG		255
-#define LCD_VIDEO_BG		0
-
-#undef	CONFIG_VIDEO				/* test only ! s.a devices.c and 8xx */
-#define CONFIG_CFB_CONSOLE			/* framebuffer console with std input */
-#define CONFIG_VIDEO_LOGO
-
-#define VIDEO_KBD_INIT_FCT	0		/* no KBD dev on MHPC - use serial */
-#define VIDEO_TSTC_FCT		serial_stub_tstc
-#define VIDEO_GETC_FCT		serial_stub_getc
-
-#define CONFIG_BR0_WORKAROUND	1
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_REGINFO
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0x300000	/* default load address */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Physical memory map
- */
-#define CONFIG_SYS_IMMR		0xFFF00000 /* Internal Memory Mapped Register*/
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0xfe000000
-
-#define CONFIG_SYS_MONITOR_LEN		0x40000		/* Reserve 256 kB for Monitor	*/
-#undef	CONFIG_SYS_MONITOR_BASE		    /* to run U-Boot from RAM */
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT		"nor0=mhpc-0"
-#define MTDPARTS_DEFAULT	"mtdparts=mhpc-0:-(jffs2)"
-*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map- for Linux	*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_OFFSET		CONFIG_SYS_MONITOR_LEN /* Offset of Environment */
-#define CONFIG_ENV_SIZE		0x20000 /* Total Size of Environment	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR	(SIUMCR_SEME)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		12-18
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit - leave PLL multiplication factor unchanged !
- */
-#define MPC8XX_SPEED	50000000L
-#define MPC8XX_XIN	5000000L      /* ref clk */
-#define MPC8XX_FACT	(MPC8XX_SPEED/MPC8XX_XIN)
-#define CONFIG_SYS_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
-			PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-
-#define SCCR_MASK	(SCCR_RTDIV | SCCR_RTSEL)     /* SCCR_EBDF11 */
-#define CONFIG_SYS_SCCR	(SCCR_TBS | SCCR_DFLCD001)
-
-
-/*-----------------------------------------------------------------------
- * MAMR settings for SDRAM	- 16-14
- * => 0xC080200F
- *-----------------------------------------------------------------------
- * periodic timer for refresh
- */
-#define CONFIG_SYS_MAMR_PTA	0xC0
-#define CONFIG_SYS_MAMR	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_G0CLA_A11 | MAMR_TLFA_MSK)
-
-/*
- * BR0 and OR0 (FLASH) used to re-map FLASH
- */
-
-/* allow for max 8 MB of Flash */
-#define FLASH_BASE		0xFE000000	/* FLASH bank #0*/
-#define FLASH_BASE0_PRELIM	0xFE000000	/* FLASH bank #0*/
-#define CONFIG_SYS_REMAP_OR_AM		0xFF800000	/* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
-
-#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK) /* (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)*/
-
-#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V )
-
-/*
- * BR1 and OR1 (SDRAM)
- */
-#define SDRAM_BASE1_PRELIM	0x00000000	/* SDRAM bank #0	*/
-#define SDRAM_MAX_SIZE		0x01000000	/* max 16 MB		*/
-#define SDRAM_RES_SIZE		0x00200000	/* 2 MB for framebuffer */
-
-/* SDRAM timing: drive GPL5 high on first cycle */
-#define CONFIG_SYS_OR_TIMING_SDRAM	(OR_G5LS)
-
-#define CONFIG_SYS_OR1_PRELIM	((~(SDRAM_MAX_SIZE)+1)| CONFIG_SYS_OR_TIMING_SDRAM )
-#define CONFIG_SYS_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/*
- * BR2/OR2 - DIMM
- */
-#define CONFIG_SYS_OR2		(OR_ACS_DIV4)
-#define CONFIG_SYS_BR2		(BR_MS_UPMA)
-
-/*
- * BR3/OR3 - DIMM
- */
-#define CONFIG_SYS_OR3		(OR_ACS_DIV4)
-#define CONFIG_SYS_BR3		(BR_MS_UPMA)
-
-/*
- * BR4/OR4
- */
-#define CONFIG_SYS_OR4		0
-#define CONFIG_SYS_BR4		0
-
-/*
- * BR5/OR5
- */
-#define CONFIG_SYS_OR5		0
-#define CONFIG_SYS_BR5		0
-
-/*
- * BR6/OR6
- */
-#define CONFIG_SYS_OR6		0
-#define CONFIG_SYS_BR6		0
-
-/*
- * BR7/OR7
- */
-#define CONFIG_SYS_OR7		0
-#define CONFIG_SYS_BR7		0
-
-
-/*-----------------------------------------------------------------------
- * Debug Entry Mode
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h
deleted file mode 100644
index 7fd12d3fbc6..00000000000
--- a/include/configs/TQM8260.h
+++ /dev/null
@@ -1,620 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Imported from global configuration:
- *	CONFIG_MPC8255
- *	CONFIG_MPC8265
- *	CONFIG_200MHz
- *	CONFIG_266MHz
- *	CONFIG_300MHz
- *	CONFIG_L2_CACHE
- *	CONFIG_BUSMODE_60x
- */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define	CONFIG_SYS_TEXT_BASE	0x40000000
-
-
-#if 0
-#define CONFIG_TQM8260		100	/* ...on a TQM8260 module Rev.100	*/
-#else
-#define CONFIG_TQM8260		200	/* ...on a TQM8260 module Rev.200	*/
-#endif
-
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-#define CONFIG_82xx_CONS_SMC1	1	/* console on SMC1			*/
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define	CONFIG_BOOTCOUNT_LIMIT
-
-#define CONFIG_BAUDRATE		115200
-
-#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"flash_nfs=run nfsargs addip;"					\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip;"					\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
-	"rootpath=/opt/eldk/ppc_6xx\0"					\
-	"bootfile=tqm8260/uImage\0"				\
-	"kernel_addr=400C0000\0"					\
-	"ramdisk_addr=40240000\0"					\
-	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-/* enable I2C and select the hardware/software driver */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED	400000
-#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-
-/* TQM8260 Rev.100 has the clock and data pins swapped (!!!) on EEPROM */
-#if (CONFIG_TQM8260 <= 100)
-
-#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE	(iop->pdir |=  0x00020000)
-#define I2C_TRISTATE	(iop->pdir &= ~0x00020000)
-#define I2C_READ	((iop->pdat & 0x00020000) != 0)
-#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00020000; \
-			else    iop->pdat &= ~0x00020000
-#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00010000; \
-			else    iop->pdat &= ~0x00010000
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-
-#else
-
-#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
-#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
-#define I2C_READ	((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
-			else    iop->pdat &= ~0x00010000
-#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
-			else    iop->pdat &= ~0x00020000
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-#endif
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
-
-#define CONFIG_I2C_X
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#define CONFIG_CONS_ON_SMC		/* define if console on SMC */
-#undef  CONFIG_CONS_ON_SCC		/* define if console on SCC */
-#undef  CONFIG_CONS_NONE		/* define if console on something else*/
-#ifdef CONFIG_82xx_CONS_SMC1
-#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
-#endif
-#ifdef CONFIG_82xx_CONS_SMC2
-#define CONFIG_CONS_INDEX	2	/* which serial channel for console */
-#endif
-
-#undef  CONFIG_CONS_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
-#define CONFIG_CONS_EXTC_RATE	3686400	/* SMC/SCC ext clk rate in Hz */
-#define CONFIG_CONS_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9 */
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- *
- * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
- * X.29 connector, and FCC2 is hardwired to the X.1 connector)
- */
-#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
-#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
-#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
-#define	CONFIG_ETHER_INDEX    2		/* which SCC/FCC channel for ethernet */
-
-#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
-
-/*
- *  - RX clk is CLK11
- *  - TX clk is CLK12
- */
-# define CONFIG_SYS_CMXSCR_VALUE1	(CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
-
-#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
-
-/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CONFIG_SYS_CPMFCR_RAMTYPE	0
-# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
-
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265)
-#  define CONFIG_8260_CLKIN	66666666	/* in Hz */
-#else	/* !CONFIG_MPC8255 && !CONFIG_MPC8265 */
-# ifndef CONFIG_300MHz
-#  define CONFIG_8260_CLKIN	66666666	/* in Hz */
-# else
-#  define CONFIG_8260_CLKIN	83333000	/* in Hz */
-# endif
-#endif	/* CONFIG_MPC8255 */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
-
-#if defined(CONFIG_CMD_KGDB)
-#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define	CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address	*/
-
-#define	CONFIG_SYS_RESET_ADDRESS 0xFFFFFFFC	/* "bad" address		*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
-
-
-/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8260/config.mk
- * The main FLASH is whichever is connected to *CS0.
- */
-#define CONFIG_SYS_FLASH0_BASE 0x40000000
-#define CONFIG_SYS_FLASH1_BASE 0x60000000
-#define CONFIG_SYS_FLASH0_SIZE 32
-#define CONFIG_SYS_FLASH1_SIZE 32
-
-/* Flash bank size (for preliminary settings)
- */
-#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-
-/* use CFI flash driver */
-#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER		1	/* Use the common driver */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_FLASH_EMPTY_INFO	1
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
-#define CONFIG_ENV_SIZE		0x08000
-#define CONFIG_ENV_SECT_SIZE	0x40000
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
-
-/*-----------------------------------------------------------------------
- * Hardware Information Block
- */
-#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
- */
-#define	__HRCW__ALL__		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
-
-#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265)
-#  define CONFIG_SYS_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0111)
-#else	/* ! MPC8255 && !MPC8265 */
-# if defined(CONFIG_266MHz)
-#  define CONFIG_SYS_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0111)
-# elif defined(CONFIG_300MHz)
-#  define CONFIG_SYS_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0110)
-# else
-#  define CONFIG_SYS_HRCW_MASTER	(__HRCW__ALL__)
-# endif
-#endif	/* CONFIG_MPC8255 */
-
-/* no slaves so just fill with zeros */
-#define CONFIG_SYS_HRCW_SLAVE1		0
-#define CONFIG_SYS_HRCW_SLAVE2		0
-#define CONFIG_SYS_HRCW_SLAVE3		0
-#define CONFIG_SYS_HRCW_SLAVE4		0
-#define CONFIG_SYS_HRCW_SLAVE5		0
-#define CONFIG_SYS_HRCW_SLAVE6		0
-#define CONFIG_SYS_HRCW_SLAVE7		0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR		0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE	0x4000  /* Size of used area in DPRAM    */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- *
- * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM
- * is mapped at SDRAM_BASE2_PRELIM.
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers                    2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
-				HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID2        0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register                                     5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CONFIG_SYS_RMR         RMR_CSRE
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration                                       4-25
- *-----------------------------------------------------------------------
- */
-#ifdef	CONFIG_BUSMODE_60x
-#define CONFIG_SYS_BCR         (BCR_EBM|BCR_L2C|BCR_LETM|\
-			 BCR_NPQM0|BCR_NPQM1|BCR_NPQM2)	/* 60x mode  */
-#else
-#define BCR_APD01	0x10000000
-#define CONFIG_SYS_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration                             4-31
- *-----------------------------------------------------------------------
- */
-#if 0
-#define CONFIG_SYS_SIUMCR      (SIUMCR_DPPC10|SIUMCR_APPC10)
-#else
-#define CONFIG_SYS_SIUMCR      (SIUMCR_DPPC00|SIUMCR_APPC10)
-#endif
-
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control                             4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control                     4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control                 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control                                   9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CONFIG_SYS_SCCR        0
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration                         13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR        0
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus     Machine PortSz  Device
- * ---- ---     ------- ------  ------
- *  0   60x     GPCM    64 bit  FLASH
- *  1   60x     SDRAM   64 bit  SDRAM
- *  2   Local   SDRAM   32 bit  SDRAM
- *
- */
-
-	/* Initialize SDRAM on local bus
-	 */
-#define CONFIG_SYS_INIT_LOCAL_SDRAM
-
-#define SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
-
-/* Minimum mask to separate preliminary
- * address ranges for CS[0:2]
- */
-#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT	(512<<20)	/* less than 512 MB */
-#define CONFIG_SYS_LOCAL_SDRAM_LIMIT	(128<<20)	/* less than 128 MB */
-
-#define CONFIG_SYS_MPTPR       0x4000
-
-/*-----------------------------------------------------------------------------
- * Address for Mode Register Set (MRS) command
- *-----------------------------------------------------------------------------
- * In fact, the address is rather configuration data presented to the SDRAM on
- * its address lines. Because the address lines may be mux'ed externally either
- * for 8 column or 9 column devices, some bits appear twice in the 8260's
- * address:
- *
- * |   (RFU)   |   (RFU)   | WBL |    TM    |     CL    |  BT | Burst Length |
- * | BA1   BA0 | A12 : A10 |  A9 |  A8   A7 |  A6 : A4  |  A3 |   A2 :  A0   |
- *  8 columns mux'ing:     |  A9 | A10  A21 | A22 : A24 | A25 |  A26 : A28   |
- *  9 columns mux'ing:     |  A8 | A20  A21 | A22 : A24 | A25 |  A26 : A28   |
- *  Settings:              |  0  |  0    0  |  0  1  0  |  0  |   0  1  0    |
- *-----------------------------------------------------------------------------
- */
-#define CONFIG_SYS_MRS_OFFS	0x00000110
-
-
-/* Bank 0 - FLASH
- */
-#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
-			 BRx_PS_64                      |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
-			 ORxG_CSNT                      |\
-			 ORxG_ACS_DIV1                  |\
-			 ORxG_SCY_3_CLK                 |\
-			 ORxG_EHTR                      |\
-			 ORxG_TRLX)
-
-	/* SDRAM on TQM8260 can have either 8 or 9 columns.
-	 * The number affects configuration values.
-	 */
-
-/* Bank 1 - 60x bus SDRAM
- */
-#define CONFIG_SYS_PSRT        0x20
-#define CONFIG_SYS_LSRT        0x20
-#ifndef CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
-			 BRx_PS_64                      |\
-			 BRx_MS_SDRAM_P                 |\
-			 BRx_V)
-
-#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR1_8COL
-
-
-	/* SDRAM initialization values for 8-column chips
-	 */
-#define CONFIG_SYS_OR1_8COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI1_A7             |\
-			 ORxS_NUMR_12)
-
-#define CONFIG_SYS_PSDMR_8COL  (PSDMR_PBI                      |\
-			 PSDMR_SDAM_A15_IS_A5           |\
-			 PSDMR_BSMA_A12_A14             |\
-			 PSDMR_SDA10_PBI1_A8            |\
-			 PSDMR_RFRC_7_CLK               |\
-			 PSDMR_PRETOACT_2W              |\
-			 PSDMR_ACTTORW_2W               |\
-			 PSDMR_LDOTOPRE_1C              |\
-			 PSDMR_WRC_2C                   |\
-			 PSDMR_EAMUX                    |\
-			 PSDMR_CL_2)
-
-	/* SDRAM initialization values for 9-column chips
-	 */
-#define CONFIG_SYS_OR1_9COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI1_A5             |\
-			 ORxS_NUMR_13)
-
-#define CONFIG_SYS_PSDMR_9COL  (PSDMR_PBI                      |\
-			 PSDMR_SDAM_A16_IS_A5           |\
-			 PSDMR_BSMA_A12_A14             |\
-			 PSDMR_SDA10_PBI1_A7            |\
-			 PSDMR_RFRC_7_CLK               |\
-			 PSDMR_PRETOACT_2W              |\
-			 PSDMR_ACTTORW_2W               |\
-			 PSDMR_LDOTOPRE_1C              |\
-			 PSDMR_WRC_2C                   |\
-			 PSDMR_EAMUX                    |\
-			 PSDMR_CL_2)
-
-/* Bank 2 - Local bus SDRAM
- */
-#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM
-#define CONFIG_SYS_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
-			 BRx_PS_32                      |\
-			 BRx_MS_SDRAM_L                 |\
-			 BRx_V)
-
-#define CONFIG_SYS_OR2_PRELIM	CONFIG_SYS_OR2_8COL
-
-#define SDRAM_BASE2_PRELIM	0x80000000
-
-	/* SDRAM initialization values for 8-column chips
-	 */
-#define CONFIG_SYS_OR2_8COL    ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI1_A8             |\
-			 ORxS_NUMR_12)
-
-#define CONFIG_SYS_LSDMR_8COL  (PSDMR_PBI                      |\
-			 PSDMR_SDAM_A15_IS_A5           |\
-			 PSDMR_BSMA_A13_A15             |\
-			 PSDMR_SDA10_PBI1_A9            |\
-			 PSDMR_RFRC_7_CLK               |\
-			 PSDMR_PRETOACT_2W              |\
-			 PSDMR_ACTTORW_2W               |\
-			 PSDMR_BL                       |\
-			 PSDMR_LDOTOPRE_1C              |\
-			 PSDMR_WRC_2C                   |\
-			 PSDMR_CL_2)
-
-	/* SDRAM initialization values for 9-column chips
-	 */
-#define CONFIG_SYS_OR2_9COL    ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI1_A6             |\
-			 ORxS_NUMR_13)
-
-#define CONFIG_SYS_LSDMR_9COL  (PSDMR_PBI                      |\
-			 PSDMR_SDAM_A16_IS_A5           |\
-			 PSDMR_BSMA_A13_A15             |\
-			 PSDMR_SDA10_PBI1_A8            |\
-			 PSDMR_RFRC_7_CLK               |\
-			 PSDMR_PRETOACT_2W              |\
-			 PSDMR_ACTTORW_2W               |\
-			 PSDMR_BL                       |\
-			 PSDMR_LDOTOPRE_1C              |\
-			 PSDMR_WRC_2C                   |\
-			 PSDMR_CL_2)
-
-#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h
deleted file mode 100644
index 9c7e16305d1..00000000000
--- a/include/configs/TQM8272.h
+++ /dev/null
@@ -1,735 +0,0 @@
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8272_FAMILY   1
-#define CONFIG_TQM8272		1
-
-#define	CONFIG_SYS_TEXT_BASE	0x40000000
-
-#define	CONFIG_GET_CPU_STR_F	1	/* Get the CPU ID STR */
-#define CONFIG_BOARD_GET_CPU_CLK_F	1 /* Get the CLKIN from board fct */
-
-#define	STK82xx_150		1	/* on a STK82xx.150 */
-
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-#define CONFIG_82xx_CONS_SMC1	1	/* console on SMC1		*/
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define CONFIG_BOARD_EARLY_INIT_R	1
-
-#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
-#define CONFIG_BAUDRATE		230400
-#else
-#define CONFIG_BAUDRATE		115200
-#endif
-
-#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"consdev=ttyCPM0\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"hostname=tqm8272\0"						\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addcons=setenv bootargs ${bootargs} "				\
-		"console=$(consdev),$(baudrate)\0"			\
-	"flash_nfs=run nfsargs addip addcons;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addcons;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 300000 ${bootfile};"				\
-		"run nfsargs addip addcons;bootm\0"			\
-	"rootpath=/opt/eldk/ppc_82xx\0"					\
-	"bootfile=/tftpboot/tqm8272/uImage\0"				\
-	"kernel_addr=40080000\0"					\
-	"ramdisk_addr=40100000\0"					\
-	"load=tftp 300000 /tftpboot/tqm8272/u-boot.bin\0"		\
-	"update=protect off 40000000 4003ffff;era 40000000 4003ffff;"	\
-		"cp.b 300000 40000000 40000;"			        \
-		"setenv filesize;saveenv\0"				\
-	"cphwib=cp.b 4003fc00 33fc00 400\0"				\
-	"upd=run load cphwib update\0"					\
-	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#define CONFIG_I2C	1
-
-#if CONFIG_I2C
-/* enable I2C and select the hardware/software driver */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED	400000
-#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
-#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
-#define I2C_READ	((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
-			else    iop->pdat &= ~0x00010000
-#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
-			else    iop->pdat &= ~0x00020000
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-
-#define CONFIG_I2C_X
-
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
-#define CONFIG_SYS_I2C_MULTI_EEPROMS		1	/* more than one eeprom */
-
-/* I2C RTC */
-#define CONFIG_RTC_DS1337		/* Use ds1337 rtc via i2c	*/
-#define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* at address 0x68		*/
-
-/* I2C SYSMON (LM75) */
-#define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
-#define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
-#define CONFIG_SYS_DTT_MAX_TEMP	70
-#define CONFIG_SYS_DTT_LOW_TEMP	-30
-#define CONFIG_SYS_DTT_HYSTERESIS	3
-
-#else
-#undef CONFIG_SYS_I2C
-#undef CONFIG_HARD_I2C
-#undef CONFIG_SYS_I2C_SOFT
-#endif
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#define CONFIG_CONS_ON_SMC		/* define if console on SMC */
-#undef  CONFIG_CONS_ON_SCC		/* define if console on SCC */
-#undef  CONFIG_CONS_NONE		/* define if console on something else*/
-#ifdef CONFIG_82xx_CONS_SMC1
-#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
-#endif
-#ifdef CONFIG_82xx_CONS_SMC2
-#define CONFIG_CONS_INDEX	2	/* which serial channel for console */
-#endif
-
-#undef  CONFIG_CONS_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
-#define CONFIG_CONS_EXTC_RATE	3686400	/* SMC/SCC ext clk rate in Hz */
-#define CONFIG_CONS_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9 */
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- *
- * (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
- * X.29 connector, and FCC2 is hardwired to the X.1 connector)
- */
-#define CONFIG_SYS_FCC_ETHERNET
-
-#if defined(CONFIG_SYS_FCC_ETHERNET)
-#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
-#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
-#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
-#define	CONFIG_ETHER_INDEX    2		/* which SCC/FCC channel for ethernet */
-#else
-#define	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
-#undef	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
-#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
-#define	CONFIG_ETHER_INDEX    1		/* which SCC/FCC channel for ethernet */
-#endif
-
-#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
-
-/*
- *  - RX clk is CLK11
- *  - TX clk is CLK12
- */
-# define CONFIG_SYS_CMXSCR_VALUE	(CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
-
-#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
-
-/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CONFIG_SYS_CPMFCR_RAMTYPE	0
-# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
-
-#define CONFIG_MII			/* MII PHY management		*/
-#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
-/*
- * GPIO pins used for bit-banged MII communications
- */
-#define MDIO_PORT	2		/* Port C */
-#define MDIO_DECLARE	volatile ioport_t *iop = ioport_addr ( \
-				(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-#define MDC_DECLARE	MDIO_DECLARE
-
-#if STK82xx_150
-#define CONFIG_SYS_MDIO_PIN	0x00008000	/* PC16 */
-#define CONFIG_SYS_MDC_PIN	0x00004000	/* PC17 */
-#endif
-
-#if STK82xx_100
-#define CONFIG_SYS_MDIO_PIN	0x00000002	/* PC30 */
-#define CONFIG_SYS_MDC_PIN	0x00000001	/* PC31 */
-#endif
-
-#if 1
-#define MDIO_ACTIVE	(iop->pdir |=  CONFIG_SYS_MDIO_PIN)
-#define MDIO_TRISTATE	(iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
-#define MDIO_READ	((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
-
-#define MDIO(bit)	if(bit) iop->pdat |=  CONFIG_SYS_MDIO_PIN; \
-			else	iop->pdat &= ~CONFIG_SYS_MDIO_PIN
-
-#define MDC(bit)	if(bit) iop->pdat |=  CONFIG_SYS_MDC_PIN; \
-			else	iop->pdat &= ~CONFIG_SYS_MDC_PIN
-#else
-#define MDIO_ACTIVE	({unsigned long tmp; tmp = iop->pdir; tmp |=  CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;})
-#define MDIO_TRISTATE	({unsigned long tmp; tmp = iop->pdir; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;})
-#define MDIO_READ	((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
-
-#define MDIO(bit)	if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |=  CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}\
-			else	{unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}
-
-#define MDC(bit)	if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |=  CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}\
-			else	{unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}
-#endif
-
-#define MIIDELAY	udelay(1)
-
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#define CONFIG_8260_CLKIN	66666666	/* in Hz */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SNTP
-
-#if CONFIG_I2C
-    #define CONFIG_CMD_I2C
-    #define CONFIG_CMD_DATE
-    #define CONFIG_CMD_DTT
-    #define CONFIG_CMD_EEPROM
-#endif
-
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-
-#if 0
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define	CONFIG_SYS_LOAD_ADDR	0x300000	/* default load address	*/
-
-#define	CONFIG_SYS_RESET_ADDRESS 0x40000104	/* "bad" address		*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * CAN stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_CAN_BASE	0x51000000
-#define	CONFIG_SYS_CAN_SIZE	1
-#define CONFIG_SYS_CAN_BR	((CONFIG_SYS_CAN_BASE & BRx_BA_MSK)	|\
-			 BRx_PS_8			|\
-			 BRx_MS_UPMC			|\
-			 BRx_V)
-
-#define CONFIG_SYS_CAN_OR	(MEG_TO_AM(CONFIG_SYS_CAN_SIZE)	|\
-			 ORxU_BI)
-
-
-/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8272/config.mk
- * The main FLASH is whichever is connected to *CS0.
- */
-#define CONFIG_SYS_FLASH0_BASE 0x40000000
-#define CONFIG_SYS_FLASH0_SIZE 32	/* 32 MB */
-
-/* Flash bank size (for preliminary settings)
- */
-#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_CFI				/* flash is CFI compat.	*/
-#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver*/
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector	*/
-#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-
-#define CONFIG_SYS_UPDATE_FLASH_SIZE
-
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
-#define CONFIG_ENV_SIZE		0x20000
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	0x20000
-
-/* Where is the Hardwareinformation Block (from Monitor Sources) */
-#define MON_RES_LENGTH		(0x0003FC00)
-#define HWIB_INFO_START_ADDR    (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH)
-#define HWIB_INFO_LEN           512
-#define CIB_INFO_START_ADDR     (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN)
-#define CIB_INFO_LEN            512
-
-#define CONFIG_SYS_HWINFO_OFFSET	0x3fc00	/* offset of HW Info block */
-#define CONFIG_SYS_HWINFO_SIZE		0x00000060	/* size   of HW Info block */
-#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-#if defined(CONFIG_CMD_NAND)
-
-#define CONFIG_SYS_NAND_CS_DIST		0x80
-#define CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS	0x20
-#define CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS	0x40
-
-#define CONFIG_SYS_NAND_BR	((CONFIG_SYS_NAND0_BASE & BRx_BA_MSK)	|\
-			 BRx_PS_8			|\
-			 BRx_MS_UPMB			|\
-			 BRx_V)
-
-#define CONFIG_SYS_NAND_OR	(MEG_TO_AM(CONFIG_SYS_NAND_SIZE)	|\
-			 ORxU_BI			|\
-			 ORxU_EHTR_8IDLE)
-
-#define CONFIG_SYS_NAND_SIZE	1
-#define CONFIG_SYS_NAND0_BASE 0x50000000
-#define CONFIG_SYS_NAND1_BASE (CONFIG_SYS_NAND0_BASE + CONFIG_SYS_NAND_CS_DIST)
-#define CONFIG_SYS_NAND2_BASE (CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST)
-#define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST)
-
-#define CONFIG_SYS_MAX_NAND_DEVICE     4       /* Max number of NAND devices           */
-
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
-			     CONFIG_SYS_NAND1_BASE, \
-			     CONFIG_SYS_NAND2_BASE, \
-			     CONFIG_SYS_NAND3_BASE, \
-			   }
-
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr)) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr)))
-#define WRITE_NAND_UPM(d, adr, off) do \
-{ \
-	volatile unsigned char *addr = (unsigned char *) (adr + off); \
-	WRITE_NAND(d, addr); \
-} while(0)
-
-#endif /* CONFIG_CMD_NAND */
-
-#define	CONFIG_PCI
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
-#define CONFIG_PCI_PNP
-#define CONFIG_EEPRO100
-#define CONFIG_SYS_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
-#define CONFIG_PCI_SCAN_SHOW
-#endif
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
- */
-#if 0
-#define	__HRCW__ALL__		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
-
-#  define CONFIG_SYS_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0111)
-#else
-#define CONFIG_SYS_HRCW_MASTER	(HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111)
-#endif
-
-/* no slaves so just fill with zeros */
-#define CONFIG_SYS_HRCW_SLAVE1		0
-#define CONFIG_SYS_HRCW_SLAVE2		0
-#define CONFIG_SYS_HRCW_SLAVE3		0
-#define CONFIG_SYS_HRCW_SLAVE4		0
-#define CONFIG_SYS_HRCW_SLAVE5		0
-#define CONFIG_SYS_HRCW_SLAVE6		0
-#define CONFIG_SYS_HRCW_SLAVE7		0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR		0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE	0x2000  /* Size of used area in DPRAM    */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers                    2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
-				HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID2        0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register                                     5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CONFIG_SYS_RMR         RMR_CSRE
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration                                       4-25
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_BCR_60x         (BCR_EBM|BCR_NPQM0|BCR_NPQM2)	/* 60x mode  */
-#define BCR_APD01	0x10000000
-#define CONFIG_SYS_BCR_SINGLE		(BCR_APD01|BCR_ETM)	/* 8260 mode */
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration                             4-31
- *-----------------------------------------------------------------------
- */
-#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
-#define CONFIG_SYS_SIUMCR_LOW		(SIUMCR_DPPC00)
-#define CONFIG_SYS_SIUMCR_HIGH		(SIUMCR_DPPC00 | SIUMCR_ABE)
-#else
-#define CONFIG_SYS_SIUMCR		(SIUMCR_DPPC00)
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control                             4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control                     4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control                 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control                                   9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CONFIG_SYS_SCCR        SCCR_DFBRG01
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration                         13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR        0
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus     Machine PortSz  Device
- * ---- ---     ------- ------  ------
- *  0   60x     GPCM    32 bit  FLASH
- *  1   60x     SDRAM   64 bit  SDRAM
- *  2   60x	UPMB	 8 bit	NAND
- *  3   60x	UPMC	 8 bit	CAN
- *
- */
-
-/* Initialize SDRAM
-	 */
-#undef CONFIG_SYS_INIT_LOCAL_SDRAM		/* No SDRAM on Local Bus */
-
-#define SDRAM_MAX_SIZE	0x20000000	/* max. 512 MB		*/
-
-/* Minimum mask to separate preliminary
- * address ranges for CS[0:2]
- */
-#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT	(512<<20)	/* less than 512 MB */
-
-#define CONFIG_SYS_MPTPR       0x4000
-
-/*-----------------------------------------------------------------------------
- * Address for Mode Register Set (MRS) command
- *-----------------------------------------------------------------------------
- * In fact, the address is rather configuration data presented to the SDRAM on
- * its address lines. Because the address lines may be mux'ed externally either
- * for 8 column or 9 column devices, some bits appear twice in the 8260's
- * address:
- *
- * |   (RFU)   |   (RFU)   | WBL |    TM    |     CL    |  BT | Burst Length |
- * | BA1   BA0 | A12 : A10 |  A9 |  A8   A7 |  A6 : A4  |  A3 |   A2 :  A0   |
- *  8 columns mux'ing:     |  A9 | A10  A21 | A22 : A24 | A25 |  A26 : A28   |
- *  9 columns mux'ing:     |  A8 | A20  A21 | A22 : A24 | A25 |  A26 : A28   |
- *  Settings:              |  0  |  0    0  |  0  1  0  |  0  |   0  1  0    |
- *-----------------------------------------------------------------------------
- */
-#define CONFIG_SYS_MRS_OFFS	0x00000110
-
-/* Bank 0 - FLASH
- */
-#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
-			 BRx_PS_32                      |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
-			 ORxG_CSNT                      |\
-			 ORxG_ACS_DIV4                  |\
-			 ORxG_SCY_8_CLK                 |\
-			 ORxG_TRLX)
-
-/* SDRAM on TQM8272 can have either 8 or 9 columns.
- * The number affects configuration values.
- */
-
-/* Bank 1 - 60x bus SDRAM
- */
-#define CONFIG_SYS_PSRT        0x20	/* Low Value */
-/* #define CONFIG_SYS_PSRT        0x10	 Fast Value */
-#define CONFIG_SYS_LSRT        0x20	/* Local Bus */
-#ifndef CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
-			 BRx_PS_64                      |\
-			 BRx_MS_SDRAM_P                 |\
-			 BRx_V)
-
-#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR1_8COL
-
-/* SDRAM initialization values for 8-column chips
- */
-#define CONFIG_SYS_OR1_8COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI1_A7             |\
-			 ORxS_NUMR_12)
-
-#define CONFIG_SYS_PSDMR_8COL  (PSDMR_PBI                      |\
-			 PSDMR_SDAM_A15_IS_A5           |\
-			 PSDMR_BSMA_A12_A14             |\
-			 PSDMR_SDA10_PBI1_A8            |\
-			 PSDMR_RFRC_7_CLK               |\
-			 PSDMR_PRETOACT_2W              |\
-			 PSDMR_ACTTORW_2W               |\
-			 PSDMR_LDOTOPRE_1C              |\
-			 PSDMR_WRC_2C                   |\
-			 PSDMR_EAMUX                    |\
-			 PSDMR_BUFCMD			|\
-			 PSDMR_CL_2)
-
-
-/* SDRAM initialization values for 9-column chips
- */
-#define CONFIG_SYS_OR1_9COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI1_A5             |\
-			 ORxS_NUMR_13)
-
-#define CONFIG_SYS_PSDMR_9COL  (PSDMR_PBI                      |\
-			 PSDMR_SDAM_A16_IS_A5           |\
-			 PSDMR_BSMA_A12_A14             |\
-			 PSDMR_SDA10_PBI1_A7            |\
-			 PSDMR_RFRC_7_CLK               |\
-			 PSDMR_PRETOACT_2W              |\
-			 PSDMR_ACTTORW_2W               |\
-			 PSDMR_LDOTOPRE_1C              |\
-			 PSDMR_WRC_2C                   |\
-			 PSDMR_EAMUX                    |\
-			 PSDMR_BUFCMD			|\
-			 PSDMR_CL_2)
-
-#define CONFIG_SYS_OR1_10COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI1_A4             |\
-			 ORxS_NUMR_13)
-
-#define CONFIG_SYS_PSDMR_10COL  (PSDMR_PBI                      |\
-			 PSDMR_SDAM_A17_IS_A5           |\
-			 PSDMR_BSMA_A12_A14             |\
-			 PSDMR_SDA10_PBI1_A4            |\
-			 PSDMR_RFRC_6_CLK               |\
-			 PSDMR_PRETOACT_2W              |\
-			 PSDMR_ACTTORW_2W               |\
-			 PSDMR_LDOTOPRE_1C              |\
-			 PSDMR_WRC_2C                   |\
-			 PSDMR_EAMUX                    |\
-			 PSDMR_BUFCMD			|\
-			 PSDMR_CL_2)
-
-#define PSDMR_RFRC_66MHZ_SINGLE         0x00028000  /* PSDMR[RFRC] at 66 MHz single mode */
-#define PSDMR_RFRC_100MHZ_SINGLE        0x00030000  /* PSDMR[RFRC] at 100 MHz single mode */
-#define PSDMR_RFRC_133MHZ_SINGLE        0x00030000  /* PSDMR[RFRC] at 133 MHz single mode */
-#define PSDMR_RFRC_66MHZ_60X            0x00030000  /* PSDMR[RFRC] at 66 MHz 60x mode */
-#define PSDMR_RFRC_100MHZ_60X           0x00028000  /* PSDMR[RFRC] at 100 MHz 60x mode */
-#define PSDMR_RFRC_DEFAULT              PSDMR_RFRC_133MHZ_SINGLE  /* PSDMR[RFRC] default value */
-
-#define PSDMR_PRETOACT_66MHZ_SINGLE     0x00002000  /* PSDMR[PRETOACT] at 66 MHz single mode */
-#define PSDMR_PRETOACT_100MHZ_SINGLE    0x00002000  /* PSDMR[PRETOACT] at 100 MHz single mode */
-#define PSDMR_PRETOACT_133MHZ_SINGLE    0x00002000  /* PSDMR[PRETOACT] at 133 MHz single mode */
-#define PSDMR_PRETOACT_66MHZ_60X        0x00001000  /* PSDMR[PRETOACT] at 66 MHz 60x mode */
-#define PSDMR_PRETOACT_100MHZ_60X       0x00001000  /* PSDMR[PRETOACT] at 100 MHz 60x mode */
-#define PSDMR_PRETOACT_DEFAULT          PSDMR_PRETOACT_133MHZ_SINGLE  /* PSDMR[PRETOACT] default value */
-
-#define PSDMR_WRC_66MHZ_SINGLE          0x00000020  /* PSDMR[WRC] at 66 MHz single mode */
-#define PSDMR_WRC_100MHZ_SINGLE         0x00000020  /* PSDMR[WRC] at 100 MHz single mode */
-#define PSDMR_WRC_133MHZ_SINGLE         0x00000010  /* PSDMR[WRC] at 133 MHz single mode */
-#define PSDMR_WRC_66MHZ_60X             0x00000010  /* PSDMR[WRC] at 66 MHz 60x mode */
-#define PSDMR_WRC_100MHZ_60X            0x00000010  /* PSDMR[WRC] at 100 MHz 60x mode */
-#define PSDMR_WRC_DEFAULT               PSDMR_WRC_133MHZ_SINGLE  /* PSDMR[WRC] default value */
-
-#define PSDMR_BUFCMD_66MHZ_SINGLE       0x00000000  /* PSDMR[BUFCMD] at 66 MHz single mode */
-#define PSDMR_BUFCMD_100MHZ_SINGLE      0x00000000  /* PSDMR[BUFCMD] at 100 MHz single mode */
-#define PSDMR_BUFCMD_133MHZ_SINGLE      0x00000004  /* PSDMR[BUFCMD] at 133 MHz single mode */
-#define PSDMR_BUFCMD_66MHZ_60X          0x00000000  /* PSDMR[BUFCMD] at 66 MHz 60x mode */
-#define PSDMR_BUFCMD_100MHZ_60X         0x00000000  /* PSDMR[BUFCMD] at 100 MHz 60x mode */
-#define PSDMR_BUFCMD_DEFAULT            PSDMR_BUFCMD_133MHZ_SINGLE  /* PSDMR[BUFCMD] default value */
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h
index f57820d8f59..54b7028c560 100644
--- a/include/configs/ac14xx.h
+++ b/include/configs/ac14xx.h
@@ -13,6 +13,9 @@
 #define __CONFIG_H
 
 #define CONFIG_AC14XX 1
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_GENERIC_BOARD
+
 /*
  * Memory map for the ifm AC14xx board:
  *
diff --git a/include/configs/aria.h b/include/configs/aria.h
index c36cf33f070..2f9677c3328 100644
--- a/include/configs/aria.h
+++ b/include/configs/aria.h
@@ -13,6 +13,9 @@
 #define __CONFIG_H
 
 #define CONFIG_ARIA 1
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_GENERIC_BOARD
+
 /*
  * Memory map for the ARIA board:
  *
diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h
index 2a8cb3940b6..76ec168c202 100644
--- a/include/configs/digsy_mtc.h
+++ b/include/configs/digsy_mtc.h
@@ -22,6 +22,8 @@
 
 #define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
 #define CONFIG_DIGSY_MTC	1	/* ... on InterControl digsyMTC board */
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_GENERIC_BOARD
 
 /*
  * Valid values for CONFIG_SYS_TEXT_BASE are:
diff --git a/include/configs/hymod.h b/include/configs/hymod.h
deleted file mode 100644
index c973365e12c..00000000000
--- a/include/configs/hymod.h
+++ /dev/null
@@ -1,728 +0,0 @@
-/*
- * (C) Copyright 2000
- * Murray Jensen <Murray.Jensen@cmst.csiro.au>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Config header file for Hymod board
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_HYMOD		1	/* ...on a Hymod board		*/
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-#define	CONFIG_SYS_TEXT_BASE	0x40000000
-
-#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
-
-#define CONFIG_BOARD_POSTCLK_INIT	/* have board_postclk_init() function */
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#undef	CONFIG_CONS_ON_SMC		/* define if console on SMC */
-#define	CONFIG_CONS_ON_SCC		/* define if console on SCC */
-#undef	CONFIG_CONS_NONE		/* define if console on something else*/
-#define	CONFIG_CONS_INDEX	1	/* which serial channel for console */
-#define	CONFIG_CONS_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
-#define	CONFIG_CONS_EXTC_RATE	3686400	/* SMC/SCC ext clk rate in Hz */
-#define	CONFIG_CONS_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC	*/
-#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC	*/
-#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
-#define CONFIG_ETHER_INDEX	1	/* which channel for ether	*/
-#define CONFIG_ETHER_LOOPBACK_TEST	/* add ether external loopback test */
-
-#ifdef CONFIG_ETHER_ON_FCC
-
-#if (CONFIG_ETHER_INDEX == 1)
-
-/*
- * - Rx-CLK is CLK10
- * - Tx-CLK is CLK11
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK1	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11)
-# define CONFIG_SYS_CPMFCR_RAMTYPE	0
-# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-# define MDIO_PORT		0		/* Port A */
-# define MDIO_DECLARE		volatile ioport_t *iop = ioport_addr ( \
-					(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-# define MDC_DECLARE		MDIO_DECLARE
-
-# define MDIO_DATA_PINMASK	0x00040000	/* Pin 13 */
-# define MDIO_CLCK_PINMASK	0x00080000	/* Pin 12 */
-
-#elif (CONFIG_ETHER_INDEX == 2)
-
-/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CONFIG_SYS_CPMFCR_RAMTYPE	0
-# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-# define MDIO_PORT		0		/* Port A */
-# define MDIO_DECLARE		volatile ioport_t *iop = ioport_addr ( \
-					(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-# define MDC_DECLARE		MDIO_DECLARE
-
-# define MDIO_DATA_PINMASK	0x00000040	/* Pin 25 */
-# define MDIO_CLCK_PINMASK	0x00000080	/* Pin 24 */
-
-#elif (CONFIG_ETHER_INDEX == 3)
-
-/*
- * - Rx-CLK is CLK15
- * - Tx-CLK is CLK16
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK3	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
-# define CONFIG_SYS_CPMFCR_RAMTYPE	0
-# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-# define MDIO_PORT		0		/* Port A */
-# define MDIO_DECLARE		volatile ioport_t *iop = ioport_addr ( \
-					(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-# define MDC_DECLARE		MDIO_DECLARE
-
-# define MDIO_DATA_PINMASK	0x00000100	/* Pin 23 */
-# define MDIO_CLCK_PINMASK	0x00000200	/* Pin 22 */
-
-#endif	/* CONFIG_ETHER_INDEX */
-
-#define CONFIG_MII			/* MII PHY management	*/
-#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
-
-#define MDIO_ACTIVE	(iop->pdir |=  MDIO_DATA_PINMASK)
-#define MDIO_TRISTATE	(iop->pdir &= ~MDIO_DATA_PINMASK)
-#define MDIO_READ	((iop->pdat &  MDIO_DATA_PINMASK) != 0)
-
-#define MDIO(bit)	if(bit) iop->pdat |=  MDIO_DATA_PINMASK; \
-			else	iop->pdat &= ~MDIO_DATA_PINMASK
-
-#define MDC(bit)	if(bit) iop->pdat |=  MDIO_CLCK_PINMASK; \
-			else	iop->pdat &= ~MDIO_CLCK_PINMASK
-
-#define MIIDELAY	udelay(1)
-
-#endif	/* CONFIG_ETHER_ON_FCC */
-
-
-/* other options */
-#define CONFIG_HARD_I2C		1	/* To enable I2C hardware support	*/
-#define CONFIG_DTT_ADM1021	1	/* ADM1021 temp sensor support */
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#ifdef DEBUG
-#define CONFIG_8260_CLKIN	33333333	/* in Hz */
-#else
-#define CONFIG_8260_CLKIN	66666666	/* in Hz */
-#endif
-
-#if defined(CONFIG_CONS_USE_EXTC)
-#define CONFIG_BAUDRATE		115200
-#else
-#define CONFIG_BAUDRATE		9600
-#endif
-
-/* default ip addresses - these will be overridden */
-#define CONFIG_IPADDR		192.168.1.1	/* hymod "boot" address */
-#define CONFIG_SERVERIP		192.168.1.254	/* hymod "server" address */
-
-#define CONFIG_LAST_STAGE_INIT
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_CDP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_DTT
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_KGDB
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_PORTIO
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SNTP
-
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_XIMG
-
-#ifdef DEBUG
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#define CONFIG_BOOT_RETRY_TIME 30	/* retry autoboot after 30 secs	*/
-#define CONFIG_BOOT_RETRY_MIN	1	/* can go down to 1 second timeout */
-/* Be selective on what keys can delay or stop the autoboot process
- *	To stop use: " "
- */
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT		"Autobooting in %d seconds, " \
-					"press <SPACE> to stop\n", bootdelay
-#define CONFIG_AUTOBOOT_STOP_STR	" "
-#undef CONFIG_AUTOBOOT_DELAY_STR
-#define DEBUG_BOOTKEYS		0
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
-#define	CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
-#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
-#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
-#define	CONFIG_KGDB_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
-#define	CONFIG_KGDB_EXTC_RATE	3686400	/* serial ext clk rate in Hz */
-#define	CONFIG_KGDB_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
-# if defined(CONFIG_KGDB_USE_EXTC)
-#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
-# else
-#define CONFIG_KGDB_BAUDRATE	9600	/* speed to run kgdb serial port at */
-# endif
-#endif
-
-#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
-
-#define CONFIG_RTC_PCF8563		/* use Philips PCF8563 RTC	*/
-
-/*
- * Hymod specific configurable options
- */
-#undef	CONFIG_SYS_HYMOD_DBLEDS			/* walk mezz board LEDs */
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#if defined(CONFIG_CMD_KGDB)
-#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x03c00000	/* 4 ... 60 MB in DRAM	*/
-
-#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
-
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define	CONFIG_SYS_I2C_SPEED		50000
-#define	CONFIG_SYS_I2C_SLAVE		0x7e
-
-/* these are for the ST M24C02 2kbit serial i2c eeprom */
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* base address */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address"    */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
-
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4	/* 16 byte write page size */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
-
-#define CONFIG_SYS_I2C_MULTI_EEPROMS	1		/* hymod has two eeproms */
-
-#define CONFIG_SYS_I2C_RTC_ADDR	0x51	/* philips PCF8563 RTC address */
-
-/*
- * standard dtt sensor configuration - bottom bit will determine local or
- * remote sensor of the ADM1021, the rest determines index into
- * CONFIG_SYS_DTT_ADM1021 array below.
- *
- * On HYMOD board, the remote sensor should be connected to the MPC8260
- * temperature diode thingy, but an errata said this didn't work and
- * should be disabled - so it isn't connected.
- */
-#if 0
-#define CONFIG_DTT_SENSORS		{ 0, 1 }
-#else
-#define CONFIG_DTT_SENSORS		{ 0 }
-#endif
-
-/*
- * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
- * there will be one entry in this array for each two (dummy) sensors in
- * CONFIG_DTT_SENSORS.
- *
- * For HYMOD board:
- * - only one ADM1021
- * - i2c addr 0x2a (both ADD0 and ADD1 are N/C)
- * - conversion rate 0x02 = 0.25 conversions/second
- * - ALERT ouput disabled
- * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
- * - remote temp sensor disabled (see comment for CONFIG_DTT_SENSORS above)
- */
-#define CONFIG_SYS_DTT_ADM1021		{ { 0x2a, 0x02, 0, 1, 0, 85, 0, } }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
- */
-#ifdef DEBUG
-#define CONFIG_SYS_HRCW_MASTER	(HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
-			 HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
-			 HRCW_MODCK_H0010)
-#else
-#define CONFIG_SYS_HRCW_MASTER	(HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
-			 HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
-			 HRCW_MODCK_H0101)
-#endif
-/* no slaves so just duplicate the master hrcw */
-#define CONFIG_SYS_HRCW_SLAVE1	CONFIG_SYS_HRCW_MASTER
-#define CONFIG_SYS_HRCW_SLAVE2	CONFIG_SYS_HRCW_MASTER
-#define CONFIG_SYS_HRCW_SLAVE3	CONFIG_SYS_HRCW_MASTER
-#define CONFIG_SYS_HRCW_SLAVE4	CONFIG_SYS_HRCW_MASTER
-#define CONFIG_SYS_HRCW_SLAVE5	CONFIG_SYS_HRCW_MASTER
-#define CONFIG_SYS_HRCW_SLAVE6	CONFIG_SYS_HRCW_MASTER
-#define CONFIG_SYS_HRCW_SLAVE7	CONFIG_SYS_HRCW_MASTER
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR		0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_SIZE	0x4000	/* Size of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define	CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_TEXT_BASE
-#define	CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_FPGA_BASE		0x80000000
-/*
- * unfortunately, CONFIG_SYS_MONITOR_LEN must include the
- * (very large i.e. 256kB) environment flash sector
- */
-#define	CONFIG_SYS_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor*/
-#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Mem map for Linux*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of memory banks	*/
-#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max num of sects on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Flash Erase Timeout (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
-
-#define	CONFIG_ENV_IS_IN_FLASH	1
-#define	CONFIG_ENV_SIZE		0x40000	/* Total Size of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE	0x40000	/* see README - env sect real size */
-#define	CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE)
-#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value*/
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers			 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
-				HID0_IFEM|HID0_ABE)
-#ifdef DEBUG
-#define CONFIG_SYS_HID0_FINAL	0
-#else
-#define CONFIG_SYS_HID0_FINAL	(HID0_ICE|HID0_IFEM|HID0_ABE)
-#endif
-#define CONFIG_SYS_HID2	0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register					 5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#ifdef DEBUG
-#define CONFIG_SYS_RMR		0
-#else
-#define CONFIG_SYS_RMR		RMR_CSRE
-#endif
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration					 4-25
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_BCR		(BCR_ETM)
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				 4-31
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SIUMCR	(SIUMCR_DPPC10|SIUMCR_L2CPC01|\
-			 SIUMCR_APPC10|SIUMCR_MMR11)
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				 4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x & Local Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control			 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control					 9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CONFIG_SYS_SCCR	(SCCR_DFBRG01)
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration				13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR	0
-
-/*
- * Init Memory Controller:
- *
- * Bank	Bus	Machine	PortSz	Device
- * ----	---	-------	------	------
- *  0	60x	GPCM	32 bit	FLASH
- *  1	60x	GPCM	32 bit	FLASH (same as 0 - unused for now)
- *  2	60x	SDRAM	64 bit	SDRAM
- *  3	Local	UPMC	 8 bit	Main Xilinx configuration
- *  4	Local	GPCM	32 bit	Main Xilinx register mode
- *  5	Local	UPMB	32 bit	Main Xilinx port mode
- *  6	Local	UPMC	 8 bit	Mezz Xilinx configuration
- */
-
-/*
- * Bank 0 - FLASH
- *
- * Quotes from the HYMOD IO Board Reference manual:
- *
- * "The flash memory is two Intel StrataFlash chips, each configured for
- *  16 bit operation and connected to give a 32 bit wide port."
- *
- * "The chip select logic is configured to respond to both *CS0 and *CS1.
- *  Therefore the FLASH memory will be mapped to both bank 0 and bank 1.
- *  It is suggested that bank 0 be read-only and bank 1 be read/write. The
- *  FLASH will then appear as ROM during boot."
- *
- * Initially, we are only going to use bank 0 in read/write mode.
- */
-
-/* 32 bit, read-write, GPCM on 60x bus */
-#define	CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_FLASH_BASE&BRx_BA_MSK)|\
-				BRx_PS_32|BRx_MS_GPCM_P|BRx_V)
-/* up to 32 Mb */
-#define	CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(32)|ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
-
-/*
- * Bank 2 - SDRAM
- *
- * Quotes from the HYMOD IO Board Reference manual:
- *
- * "The main memory is implemented using TC59SM716FTL-10 SDRAM and has a
- *  fixed size of 64 Mbytes. The Toshiba TC59SM716FTL-10 is a CMOS synchronous
- *  dynamic random access memory organised as 4 banks by 4096 rows by 512
- *  columns by 16 bits. Four chips provide a 64-bit port on the 60x bus."
- *
- * "The locations in SDRAM are accessed using multiplexed address pins to
- *  specify row and column. The pins also act to specify commands. The state
- *  of the inputs *RAS, *CAS and *WE defines the required action. The a10/AP
- *  pin may function as a row address or as the AUTO PRECHARGE control line,
- *  depending on the cycle type. The 60x bus SDRAM machine allows the MPC8260
- *  address lines to be configured to the required multiplexing scheme."
- */
-
-#define CONFIG_SYS_SDRAM_SIZE	64
-
-/* 64 bit, read-write, SDRAM on 60x bus */
-#define	CONFIG_SYS_BR2_PRELIM	((CONFIG_SYS_SDRAM_BASE&BRx_BA_MSK)|\
-				BRx_PS_64|BRx_MS_SDRAM_P|BRx_V)
-/* 64 Mb, 4 int banks per dev, row start addr bit = A6, 12 row addr lines */
-#define	CONFIG_SYS_OR2_PRELIM	(MEG_TO_AM(CONFIG_SYS_SDRAM_SIZE)|\
-				ORxS_BPD_4|ORxS_ROWST_PBI1_A6|ORxS_NUMR_12)
-
-/*
- * The 60x Bus SDRAM Mode Register (PDSMR) is set as follows:
- *
- * Page Based Interleaving, Refresh Enable, Address Multiplexing where A5
- * is output on A16 pin (A6 on A17, and so on), use address pins A14-A16
- * as bank select, A7 is output on SDA10 during an ACTIVATE command,
- * earliest timing for ACTIVATE command after REFRESH command is 6 clocks,
- * earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
- * is 2 clocks, earliest timing for READ/WRITE command after ACTIVATE
- * command is 2 clocks, earliest timing for PRECHARGE after last data
- * was read is 1 clock, earliest timing for PRECHARGE after last data
- * was written is 1 clock, CAS Latency is 2.
- */
-
-#define CONFIG_SYS_PSDMR	(PSDMR_PBI|PSDMR_SDAM_A16_IS_A5|\
-				PSDMR_BSMA_A14_A16|PSDMR_SDA10_PBI1_A7|\
-				PSDMR_RFRC_6_CLK|PSDMR_PRETOACT_2W|\
-				PSDMR_ACTTORW_2W|PSDMR_LDOTOPRE_1C|\
-				PSDMR_WRC_1C|PSDMR_CL_2)
-
-/*
- * The 60x bus-assigned SDRAM Refresh Timer (PSRT) (10-31) and the Refresh
- * Timers Prescale (PTP) value in the Memory Refresh Timer Prescaler Register
- * (MPTPR) (10-32) must also be set up (it used to be called the Periodic Timer
- * Prescaler, hence the P instead of the R). The refresh timer period is given
- * by (note that there was a change in the 8260 UM Errata):
- *
- *	TimerPeriod = (PSRT + 1) / Fmptc
- *
- * where Fmptc is the BusClock divided by PTP. i.e.
- *
- *	TimerPeriod = (PSRT + 1) / (BusClock / PTP)
- *
- * or
- *
- *	TImerPeriod = (PTP * (PSRT + 1)) / BusClock
- *
- * The requirement for the Toshiba TC59SM716FTL-10 is that there must be
- * 4K refresh cycles every 64 ms. i.e. one refresh cycle every 64000/4096
- * = 15.625 usecs.
- *
- * So PTP * (PSRT + 1) <= 15.625 * BusClock. At 66.666MHz, PSRT=31 and PTP=32
- * appear to be reasonable.
- */
-
-#ifdef DEBUG
-#define CONFIG_SYS_PSRT	39
-#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV8
-#else
-#define CONFIG_SYS_PSRT	31
-#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV32
-#endif
-
-/*
- * Banks 3,4,5 and 6 - FPGA access
- *
- * Quotes from the HYMOD IO Board Reference manual:
- *
- * "The IO Board is fitted with a Xilinx XCV300E main FPGA. Provision is made
- *  for configuring an optional FPGA on the mezzanine interface.
- *
- *  Access to the FPGAs may be divided into several catagories:
- *
- *  1. Configuration
- *  2. Register mode access
- *  3. Port mode access
- *
- *  The main FPGA is supported for modes 1, 2 and 3. The mezzanine FPGA can be
- *  configured only (mode 1). Consequently there are four access types.
- *
- *  To improve interface performance and simplify software design, the four
- *  possible access types are separately mapped to different memory banks.
- *
- *  All are accessed using the local bus."
- *
- *	 Device		    Mode      Memory Bank Machine Port Size    Access
- *
- *	  Main		Configuration	   3	   UPMC	     8bit	R/W
- *	  Main		  Register	   4	   GPCM	    32bit	R/W
- *	  Main		    Port	   5	   UPMB	    32bit	R/W
- *	Mezzanine	Configuration	   6	   UPMC	     8bit	W/O
- *
- * "Note that mezzanine mode 1 access is write-only."
- */
-
-/* all the bank sizes must be a power of two, greater or equal to 32768 */
-#define FPGA_MAIN_CFG_BASE	(CONFIG_SYS_FPGA_BASE)
-#define FPGA_MAIN_CFG_SIZE	32768
-#define FPGA_MAIN_REG_BASE	(FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE)
-#define FPGA_MAIN_REG_SIZE	32768
-#define FPGA_MAIN_PORT_BASE	(FPGA_MAIN_REG_BASE + FPGA_MAIN_REG_SIZE)
-#define FPGA_MAIN_PORT_SIZE	32768
-#define FPGA_MEZZ_CFG_BASE	(FPGA_MAIN_PORT_BASE + FPGA_MAIN_PORT_SIZE)
-#define FPGA_MEZZ_CFG_SIZE	32768
-
-/* 8 bit, read-write, UPMC */
-#define	CONFIG_SYS_BR3_PRELIM	(FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
-/* up to 32Kbyte, burst inhibit */
-#define	CONFIG_SYS_OR3_PRELIM	(P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI)
-
-/* 32 bit, read-write, GPCM */
-#define	CONFIG_SYS_BR4_PRELIM	(FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V)
-/* up to 32Kbyte */
-#define	CONFIG_SYS_OR4_PRELIM	(P2SZ_TO_AM(FPGA_MAIN_REG_SIZE))
-
-/* 32 bit, read-write, UPMB */
-#define	CONFIG_SYS_BR5_PRELIM	(FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V)
-/* up to 32Kbyte */
-#define	CONFIG_SYS_OR5_PRELIM	(P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI)
-
-/* 8 bit, write-only, UPMC */
-#define	CONFIG_SYS_BR6_PRELIM	(FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
-/* up to 32Kbyte, burst inhibit */
-#define	CONFIG_SYS_OR6_PRELIM	(P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI)
-
-/*-----------------------------------------------------------------------
- * MBMR - Machine B Mode					10-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_MBMR	(MxMR_BSEL|MxMR_OP_NORM)	/* XXX - needs more */
-
-/*-----------------------------------------------------------------------
- * MCMR - Machine C Mode					10-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_MCMR	(MxMR_BSEL|MxMR_DSx_2_CYCL)	/* XXX - needs more */
-
-/*
- * FPGA I/O Port/Bit information
- */
-
-#define FPGA_MAIN_PROG_PORT	IOPIN_PORTA
-#define FPGA_MAIN_PROG_PIN	4	/* PA4 */
-#define FPGA_MAIN_INIT_PORT	IOPIN_PORTA
-#define FPGA_MAIN_INIT_PIN	5	/* PA5 */
-#define FPGA_MAIN_DONE_PORT	IOPIN_PORTA
-#define FPGA_MAIN_DONE_PIN	6	/* PA6 */
-
-#define FPGA_MEZZ_PROG_PORT	IOPIN_PORTA
-#define FPGA_MEZZ_PROG_PIN	0	/* PA0 */
-#define FPGA_MEZZ_INIT_PORT	IOPIN_PORTA
-#define FPGA_MEZZ_INIT_PIN	1	/* PA1 */
-#define FPGA_MEZZ_DONE_PORT	IOPIN_PORTA
-#define FPGA_MEZZ_DONE_PIN	2	/* PA2 */
-#define FPGA_MEZZ_ENABLE_PORT	IOPIN_PORTA
-#define FPGA_MEZZ_ENABLE_PIN	3	/* PA3 */
-
-/*
- * FPGA Interrupt configuration
- */
-#define FPGA_MAIN_IRQ		SIU_INT_IRQ2
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT		""
-#define MTDPARTS_DEFAULT	""
-*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h
index 6c19817f86a..0b9cbae5bad 100644
--- a/include/configs/mecp5123.h
+++ b/include/configs/mecp5123.h
@@ -15,6 +15,9 @@
 #define __CONFIG_H
 
 #define CONFIG_MECP5123 1
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_GENERIC_BOARD
+
 /*
  * Memory map for the MECP5123 board:
  *
diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h
index 7de245b33cb..41ae0a53f89 100644
--- a/include/configs/mpc5121ads.h
+++ b/include/configs/mpc5121ads.h
@@ -12,6 +12,9 @@
 #define __CONFIG_H
 
 #define CONFIG_MPC5121ADS 1
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_GENERIC_BOARD
+
 /*
  * Memory map for the MPC5121ADS board:
  *
diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h
deleted file mode 100644
index a210e293a9b..00000000000
--- a/include/configs/p3mx.h
+++ /dev/null
@@ -1,434 +0,0 @@
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Based on original work by
- *      Roel Loeffen, (C) Copyright 2006 Prodrive B.V.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/************************************************************************
- * p3mx.h - configuration for Prodrive P3M750 & P3M7448 boards
- *
- * The defines:
- * CONFIG_P3M750 or
- * CONFIG_P3M7448
- * are written into include/config.h by the "make xxx_config" command
- ***********************************************************************/
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_P3Mx			/* used for both board versions	*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xfff00000
-
-#if defined (CONFIG_P3M750)
-#define CONFIG_750FX			/* 750GL/GX/FX			*/
-#define CONFIG_HIGH_BATS		/* High BATs supported		*/
-#define CONFIG_SYS_BOARD_NAME		"P3M750"
-#define CONFIG_SYS_BUS_CLK		100000000
-#define CONFIG_SYS_TCLK		100000000
-#elif defined (CONFIG_P3M7448)
-#define CONFIG_74xx
-#define CONFIG_SYS_BOARD_NAME		"P3M7448"
-#define CONFIG_SYS_BUS_CLK		133333333
-#define CONFIG_SYS_TCLK		133333333
-#endif
-#define CONFIG_SYS_GT_DUAL_CPU			/* also for JTAG even with one cpu */
-
-/* which initialization functions to call for this board */
-#define CONFIG_SYS_BOARD_ASM_INIT	1
-#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f	*/
-#define CONFIG_MISC_INIT_R      1	/* Call misc_init_r()		*/
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#ifdef CONFIG_P3M750
-#define CONFIG_SYS_SDRAM1_BASE		0x10000000	/* each 256 MByte	*/
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#if defined (CONFIG_P3M750)
-#define CONFIG_SYS_FLASH_BASE		0xff800000	/* start of flash banks	*/
-#define CONFIG_SYS_BOOT_SIZE		_8M		/* boot flash		*/
-#elif defined (CONFIG_P3M7448)
-#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of flash banks	*/
-#define CONFIG_SYS_BOOT_SIZE		_16M		/* boot flash		*/
-#endif
-#define CONFIG_SYS_BOOT_SPACE		CONFIG_SYS_FLASH_BASE	/* BOOT_CS0 flash 0    */
-#define CONFIG_SYS_MONITOR_BASE	0xfff00000
-#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
-#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
-#define CONFIG_SYS_MISC_REGION_BASE	0xf0000000
-
-#define CONFIG_SYS_DFL_GT_REGS		0xf1000000	/* boot time GT_REGS */
-#define CONFIG_SYS_GT_REGS		0xf1000000	/* GT Registers are mapped here */
-#define CONFIG_SYS_INT_SRAM_BASE	0x42000000	/* GT offers 256k internal SRAM */
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in internal SRAM)
- *----------------------------------------------------------------------*/
- /*
- * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
- * To an unused memory region. The stack will remain in cache until RAM
- * is initialized
-*/
-#undef	CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR	0x42000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_MPSC			/* MV64460 Serial		*/
-#define CONFIG_MPSC_PORT	0
-#define CONFIG_BAUDRATE		115200	/* console baudrate		*/
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-/*-----------------------------------------------------------------------
- * Ethernet
- *----------------------------------------------------------------------*/
-/* Change the default ethernet port, use this define (options: 0, 1, 2) */
-#define CONFIG_SYS_ETH_PORT		ETH_0
-#define MV_ETH_DEVS		2
-#define CONFIG_PHY_RESET        1	/* reset phy upon startup         */
-#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible		*/
-#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver		*/
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protection	*/
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
-#if defined (CONFIG_P3M750)
-#define CONFIG_ENV_SECT_SIZE	0x20000	/* one sector (1 device)		*/
-#elif defined (CONFIG_P3M7448)
-#define CONFIG_ENV_SECT_SIZE	0x40000	/* two sectors (2 devices parallel	*/
-#endif
-#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_MV64460_ECC
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_SPEED		100000		/* I2C speed default	*/
-
-/* I2C RTC */
-#define CONFIG_RTC_M41T11	1
-#define CONFIG_SYS_I2C_RTC_ADDR	0x68
-#define CONFIG_SYS_M41T11_BASE_YEAR	1900	/* play along with linux	*/
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *----------------------------------------------------------------------*/
-#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#undef CONFIG_PCI			/* include pci support		*/
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
-#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-#define CONFIG_PCI_SCAN_SHOW		/* show devices on bus		*/
-#endif /* CONFIG_PCI */
-
-/* PCI MEMORY MAP section */
-#define CONFIG_SYS_PCI0_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI0_MEM_SIZE	_128M
-#define CONFIG_SYS_PCI1_MEM_BASE	0x88000000
-#define CONFIG_SYS_PCI1_MEM_SIZE	_128M
-
-#define CONFIG_SYS_PCI0_0_MEM_SPACE	(CONFIG_SYS_PCI0_MEM_BASE)
-#define CONFIG_SYS_PCI1_0_MEM_SPACE	(CONFIG_SYS_PCI1_MEM_BASE)
-
-/* PCI I/O MAP section */
-#define CONFIG_SYS_PCI0_IO_BASE	0xfa000000
-#define CONFIG_SYS_PCI0_IO_SIZE	_16M
-#define CONFIG_SYS_PCI1_IO_BASE	0xfb000000
-#define CONFIG_SYS_PCI1_IO_SIZE	_16M
-
-#define CONFIG_SYS_PCI0_IO_SPACE	(CONFIG_SYS_PCI0_IO_BASE)
-#define CONFIG_SYS_PCI0_IO_SPACE_PCI	0x00000000
-#define CONFIG_SYS_PCI1_IO_SPACE	(CONFIG_SYS_PCI1_IO_BASE)
-#define CONFIG_SYS_PCI1_IO_SPACE_PCI	0x00000000
-
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI0_IO_BASE)
-#define CONFIG_SYS_PCI_IDSEL 0x30
-
-#undef	CONFIG_BOOTARGS
-#define	CONFIG_EXTRA_ENV_SETTINGS_COMMON				\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
-		"bootm\0"						\
-	"rootpath=/opt/eldk/ppc_6xx\0"					\
-	"u-boot=p3mx/u-boot/u-boot.bin\0"				\
-	"load=tftp 100000 ${u-boot}\0"					\
-	"update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;"	\
-		"cp.b 100000 fff00000 40000;"			        \
-		"setenv filesize;saveenv\0"				\
-	"upd=run load update\0"						\
-	"serverip=11.0.0.152\0"
-
-#if defined (CONFIG_P3M750)
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_EXTRA_ENV_SETTINGS_COMMON				\
-	"hostname=p3m750\0"						\
-	"bootfile=/tftpboot/p3mx/vxWorks.st\0"				\
-	"kernel_addr=fc000000\0"					\
-	"ramdisk_addr=fc180000\0"					\
-	"vxfile=p3m750/vxWorks\0"					\
-	"vxuser=ddg\0"							\
-	"vxpass=ddg\0"							\
-	"vxtarget=target\0"						\
-	"vxflags=0x8\0"							\
-	"vxargs=setenv bootargs mgi(0,0)host:${vxfile} h=${serverip} "	\
-		"e=${ipaddr} u=${vxuser} pw=${vxpass} tn=${vxtarget} "	\
-		"f=${vxflags}\0"
-#elif defined (CONFIG_P3M7448)
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_EXTRA_ENV_SETTINGS_COMMON				\
-	"hostname=p3m7448\0"
-#endif
-
-#if defined (CONFIG_P3M750)
-#define CONFIG_BOOTCOMMAND	"tftp;run vxargs;bootvx"
-#elif defined (CONFIG_P3M7448)
-#define CONFIG_BOOTCOMMAND	" "
-#endif
-
-#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_SDRAM
-
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_HUSH_PARSER
-
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE	        256	/* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	        16	/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	        CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on	        */
-#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0x08000000	/* default load address */
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
-/*-----------------------------------------------------------------------
- * Marvell MV64460 config settings
- *----------------------------------------------------------------------*/
-/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected device width */
-#if defined (CONFIG_P3M750)
-#define CONFIG_SYS_BOOT_PAR		0x8FDFF87F	/* 16 bit flash, disable burst*/
-#elif defined (CONFIG_P3M7448)
-#define CONFIG_SYS_BOOT_PAR		0x8FEFFFFF	/* 32 bit flash, burst enabled */
-#endif
-
-/*
- * MPP[0]	Serial Port 0 TxD	TxD	OUT	Connected to P14 (buffered)
- * MPP[1]	Serial Port 0 RxD	RxD	IN	Connected to P14 (buffered)
- * MPP[2]	NC
- * MPP[3]	Serial Port 1 TxD	TxD	OUT	Connected to P14 (buffered)
- * MPP[4]	PCI Monarch#		GPIO	IN	Connected to P12
- * MPP[5]	Serial Port 1 RxD	RxD	IN	Connected to P14 (buffered)
- * MPP[6]	PMC Carrier Interrupt 0	Int	IN	Connected to P14
- * MPP[7]	PMC Carrier Interrupt 1	Int	IN	Connected to P14
- * MPP[8]	Reserved				Do not use
- * MPP[9]	Reserved				Do not use
- * MPP[10]	Reserved				Do not use
- * MPP[11]	Reserved				Do not use
- * MPP[12]	Phy 0 Interrupt		Int	IN
- * MPP[13]	Phy 1 Interrupt		Int	IN
- * MPP[14]	NC
- * MPP[15]	NC
- * MPP[16]	PCI Interrupt C		Int	IN	Connected to P11
- * MPP[17]	PCI Interrupt D		Int	IN	Connected to P11
- * MPP[18]	Watchdog NMI#		GPIO	IN	Connected to MPP[24]
- * MPP[19]	Watchdog Expired#	WDE	OUT	Connected to rst logic
- * MPP[20]	Watchdog Status		WD_STS	IN	Read back of rst by watchdog
- * MPP[21]	NC
- * MPP[22]	GP LED Green		GPIO	OUT
- * MPP[23]	GP LED Red		GPIO	OUT
- * MPP[24]	Watchdog NMI#		Int	OUT
- * MPP[25]	NC
- * MPP[26]	NC
- * MPP[27]	PCI Interrupt A		Int	IN	Connected to P11
- * MPP[28]	NC
- * MPP[29]	PCI Interrupt B		Int	IN	Connected to P11
- * MPP[30]	Module reset		GPIO	OUT	Board reset
- * MPP[31]	PCI EReady		GPIO	IN	Connected to P12
- */
-#define CONFIG_SYS_MPP_CONTROL_0	0x00303022
-#define CONFIG_SYS_MPP_CONTROL_1	0x00000000
-#define CONFIG_SYS_MPP_CONTROL_2	0x00004000
-#define CONFIG_SYS_MPP_CONTROL_3	0x00000004
-#define CONFIG_SYS_GPP_LEVEL_CONTROL	0x280730D0
-
-/*----------------------------------------------------------------------
- * Initial BAT mappings
- */
-
-/* NOTES:
- * 1) GUARDED and WRITE_THRU not allowed in IBATS
- * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
- */
-/* SDRAM */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* init ram */
-#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
-
-/* PCI0, PCI1 in one BAT */
-#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
-#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* GT regs, bootrom, all the devices, PCI I/O */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-/* set rest out of range for Linux !!!!!!!!!!! */
-
-/* IBAT5 and DBAT5 */
-#define CONFIG_SYS_IBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT5U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-
-/* IBAT6 and DBAT6 */
-#define CONFIG_SYS_IBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT6U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-
-/* IBAT7 and DBAT7 */
-#define CONFIG_SYS_IBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT7U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8<<20) /* Initial Memory map for Linux */
-#define CONFIG_SYS_VXWORKS_MAC_PTR	0x42010000 /* use some memory in SRAM that's not used!!! */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * L2CR setup -- make sure this is right for your board!
- * look in include/mpc74xx.h for the defines used here
- */
-#define CONFIG_SYS_L2
-
-#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
-#define L2_INIT 0
-#else
-#define L2_INIT		(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
-			L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
-#endif
-
-#define L2_ENABLE	(L2_INIT | L2CR_L2E)
-
-#ifndef __ASSEMBLY__
-#include <../board/Marvell/include/core.h>
-#endif
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/pdm360ng.h b/include/configs/pdm360ng.h
index 553eb8f9672..17d7bcab008 100644
--- a/include/configs/pdm360ng.h
+++ b/include/configs/pdm360ng.h
@@ -13,6 +13,8 @@
 #define __CONFIG_H
 
 #define CONFIG_PDM360NG 1
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_GENERIC_BOARD
 
 /*
  * Memory map for the PDM360NG board: