mpc83xx: Kconfig: Migrate HRCW to Kconfig

The HRCW (hardware reset configuration word) is a constant that must be
hard-coded into the boot loader image. So, it must be available at
compile time, and cannot be migrated to the DT mechanism, but has to be
kept in Kconfig.

Configuration of this crucial variable should still be somewhat
comfortable. Hence, make its fields configurable in Kconfig, and
assemble the final value from these.

Signed-off-by: Mario Six <mario.six@gdsys.cc>

30 files changed, 0 insertions, 1038 deletions

diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index 77c30093bfd..db283578b9b 100644
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -28,38 +28,6 @@
 #define CONFIG_VSC7385_ENET
 
 /*
- * Hardware Reset Configuration Word
- * if CLKIN is 66.66MHz, then
- * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
- * We choose the A type silicon as default, so the core is 400Mhz.
- */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_2X1 |\
-	HRCWL_SVCOD_DIV_2 |\
-	HRCWL_CSB_TO_CLKIN_4X1 |\
-	HRCWL_CORE_TO_CSB_3X1)
-/*
- * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
- * in 8308's HRCWH according to the manual, but original Freescale's
- * code has them and I've expirienced some problems using the board
- * with BDI3000 attached when I've tried to set these bits to zero
- * (UART doesn't work after the 'reset run' command).
- */
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_HOST |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0X00000100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_RL_EXT_LEGACY |\
-	HRCWH_TSEC1M_IN_RGMII |\
-	HRCWH_TSEC2M_IN_RGMII |\
-	HRCWH_BIG_ENDIAN)
-
-/*
  * System IO Config
  */
 #define CONFIG_SYS_SICRH (\
diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h
index 103ace2d3a9..e14652a6268 100644
--- a/include/configs/MPC8313ERDB_NAND.h
+++ b/include/configs/MPC8313ERDB_NAND.h
@@ -424,44 +424,6 @@
 
 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000	/* PCIHOST  */
 
-#ifdef CONFIG_SYS_66MHZ
-
-/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
-/* 0x62040000 */
-#define CONFIG_SYS_HRCW_LOW (\
-	0x20000000 /* reserved, must be set */ |\
-	HRCWL_DDRCM |\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_2X1 |\
-	HRCWL_CSB_TO_CLKIN_2X1 |\
-	HRCWL_CORE_TO_CSB_2X1)
-#elif defined(CONFIG_SYS_33MHZ)
-
-/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
-/* 0x65040000 */
-#define CONFIG_SYS_HRCW_LOW (\
-	0x20000000 /* reserved, must be set */ |\
-	HRCWL_DDRCM |\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_2X1 |\
-	HRCWL_CSB_TO_CLKIN_5X1 |\
-	HRCWL_CORE_TO_CSB_2X1)
-#endif
-
-#define CONFIG_SYS_HRCW_HIGH_BASE (\
-	HRCWH_PCI_HOST |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_TSEC1M_IN_RGMII |\
-	HRCWH_TSEC2M_IN_RGMII |\
-	HRCWH_BIG_ENDIAN)
-
-#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
-		       HRCWH_FROM_0XFFF00100 |\
-		       HRCWH_ROM_LOC_NAND_SP_8BIT |\
-		       HRCWH_RL_EXT_NAND)
 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
 
 /* System IO Config */
diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h
index 64b289adce4..b550a8daf82 100644
--- a/include/configs/MPC8313ERDB_NOR.h
+++ b/include/configs/MPC8313ERDB_NOR.h
@@ -398,46 +398,6 @@
 
 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000	/* PCIHOST  */
 
-#ifdef CONFIG_SYS_66MHZ
-
-/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
-/* 0x62040000 */
-#define CONFIG_SYS_HRCW_LOW (\
-	0x20000000 /* reserved, must be set */ |\
-	HRCWL_DDRCM |\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_2X1 |\
-	HRCWL_CSB_TO_CLKIN_2X1 |\
-	HRCWL_CORE_TO_CSB_2X1)
-
-#elif defined(CONFIG_SYS_33MHZ)
-
-/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
-/* 0x65040000 */
-#define CONFIG_SYS_HRCW_LOW (\
-	0x20000000 /* reserved, must be set */ |\
-	HRCWL_DDRCM |\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_2X1 |\
-	HRCWL_CSB_TO_CLKIN_5X1 |\
-	HRCWL_CORE_TO_CSB_2X1)
-
-#endif
-
-#define CONFIG_SYS_HRCW_HIGH_BASE (\
-	HRCWH_PCI_HOST |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_TSEC1M_IN_RGMII |\
-	HRCWH_TSEC2M_IN_RGMII |\
-	HRCWH_BIG_ENDIAN)
-
-#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
-		       HRCWH_FROM_0X00000100 |\
-		       HRCWH_ROM_LOC_LOCAL_16BIT |\
-		       HRCWH_RL_EXT_LEGACY)
 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
 
 /* System IO Config */
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 53a02f415fe..446c98bad1a 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -24,40 +24,6 @@
 #define CONFIG_E300		1 /* E300 family */
 
 /*
- * Hardware Reset Configuration Word
- * if CLKIN is 66.66MHz, then
- * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
- */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_2X1 |\
-	HRCWL_SVCOD_DIV_2 |\
-	HRCWL_CSB_TO_CLKIN_2X1 |\
-	HRCWL_CORE_TO_CSB_3X1)
-#define CONFIG_SYS_HRCW_HIGH_BASE (\
-	HRCWH_PCI_HOST |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_TSEC1M_IN_RGMII |\
-	HRCWH_TSEC2M_IN_RGMII |\
-	HRCWH_BIG_ENDIAN |\
-	HRCWH_LALE_NORMAL)
-
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
-		       HRCWH_FROM_0XFFF00100 |\
-		       HRCWH_ROM_LOC_NAND_SP_8BIT |\
-		       HRCWH_RL_EXT_NAND)
-#else
-#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
-		       HRCWH_FROM_0X00000100 |\
-		       HRCWH_ROM_LOC_LOCAL_16BIT |\
-		       HRCWH_RL_EXT_LEGACY)
-#endif
-
-/*
  * System IO Config
  */
 #define CONFIG_SYS_SICRH		0x00000000
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index ee4eeec8856..7dbbb4e0fbd 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -16,30 +16,6 @@
 #define CONFIG_QE		1	/* Has QE */
 
 /*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_2X1 |\
-	HRCWL_VCO_1X2 |\
-	HRCWL_CSB_TO_CLKIN_2X1 |\
-	HRCWL_CORE_TO_CSB_2_5X1 |\
-	HRCWL_CE_PLL_VCO_DIV_2 |\
-	HRCWL_CE_PLL_DIV_1X1 |\
-	HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_HOST |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0X00000100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_BIG_ENDIAN |\
-	HRCWH_LALE_NORMAL)
-
-/*
  * System IO Config
  */
 #define CONFIG_SYS_SICRL		0x00000000
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index 0ba64772542..dad8407f679 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -13,43 +13,6 @@
 #define CONFIG_QE		1	/* Has QE */
 
 /*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_2X1 |\
-	HRCWL_VCO_1X2 |\
-	HRCWL_CSB_TO_CLKIN_2X1 |\
-	HRCWL_CORE_TO_CSB_2X1 |\
-	HRCWL_CE_PLL_VCO_DIV_2 |\
-	HRCWL_CE_PLL_DIV_1X1 |\
-	HRCWL_CE_TO_PLL_1X3)
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_AGENT |\
-	HRCWH_PCI1_ARBITER_DISABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0XFFF00100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_BIG_ENDIAN |\
-	HRCWH_LALE_NORMAL)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_HOST |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0X00000100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_BIG_ENDIAN |\
-	HRCWH_LALE_NORMAL)
-#endif
-
-/*
  * System IO Config
  */
 #define CONFIG_SYS_SICRL		0x00000000
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 4c9ee76815c..21594540614 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -17,12 +17,6 @@
  */
 #define CONFIG_E300		1	/* E300 Family */
 
-#if CONFIG_SYS_CLK_FREQ == 66000000 || CONFIG_SYS_CLK_FREQ == 66666666
-#define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_4X1
-#elif CONFIG_SYS_CLK_FREQ == 33000000
-#define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_8X1
-#endif
-
 #define CONFIG_SYS_IMMR		0xE0000000
 
 #undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
@@ -363,86 +357,6 @@
 
 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 
-#if 1 /*528/264*/
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_1X1 |\
-	HRCWL_CSB_TO_CLKIN |\
-	HRCWL_VCO_1X2 |\
-	HRCWL_CORE_TO_CSB_2X1)
-#elif 0 /*396/132*/
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_1X1 |\
-	HRCWL_CSB_TO_CLKIN |\
-	HRCWL_VCO_1X4 |\
-	HRCWL_CORE_TO_CSB_3X1)
-#elif 0 /*264/132*/
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_1X1 |\
-	HRCWL_CSB_TO_CLKIN |\
-	HRCWL_VCO_1X4 |\
-	HRCWL_CORE_TO_CSB_2X1)
-#elif 0 /*132/132*/
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_1X1 |\
-	HRCWL_CSB_TO_CLKIN |\
-	HRCWL_VCO_1X4 |\
-	HRCWL_CORE_TO_CSB_1X1)
-#elif 0 /*264/264 */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_1X1 |\
-	HRCWL_CSB_TO_CLKIN |\
-	HRCWL_VCO_1X4 |\
-	HRCWL_CORE_TO_CSB_1X1)
-#endif
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_AGENT |\
-	HRCWH_64_BIT_PCI |\
-	HRCWH_PCI1_ARBITER_DISABLE |\
-	HRCWH_PCI2_ARBITER_DISABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0X00000100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_TSEC1M_IN_GMII |\
-	HRCWH_TSEC2M_IN_GMII)
-#else
-#if defined(CONFIG_PCI_64BIT)
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_HOST |\
-	HRCWH_64_BIT_PCI |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_PCI2_ARBITER_DISABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0X00000100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_TSEC1M_IN_GMII |\
-	HRCWH_TSEC2M_IN_GMII)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_HOST |\
-	HRCWH_32_BIT_PCI |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_PCI2_ARBITER_ENABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0X00000100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_TSEC1M_IN_GMII |\
-	HRCWH_TSEC2M_IN_GMII)
-#endif /* CONFIG_PCI_64BIT */
-#endif /* CONFIG_PCISLAVE */
-
 /*
  * System performance
  */
diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h
index b9710b65882..a19e732d8a6 100644
--- a/include/configs/MPC8349EMDS_SDRAM.h
+++ b/include/configs/MPC8349EMDS_SDRAM.h
@@ -17,12 +17,6 @@
  */
 #define CONFIG_E300		1	/* E300 Family */
 
-#if CONFIG_SYS_CLK_FREQ == 66000000 || CONFIG_SYS_CLK_FREQ == 66666666
-#define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_4X1
-#elif CONFIG_SYS_CLK_FREQ == 33000000
-#define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_8X1
-#endif
-
 #define CONFIG_SYS_IMMR		0xE0000000
 
 #undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
@@ -435,86 +429,6 @@
 
 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 
-#if 1 /*528/264*/
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_1X1 |\
-	HRCWL_CSB_TO_CLKIN |\
-	HRCWL_VCO_1X2 |\
-	HRCWL_CORE_TO_CSB_2X1)
-#elif 0 /*396/132*/
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_1X1 |\
-	HRCWL_CSB_TO_CLKIN |\
-	HRCWL_VCO_1X4 |\
-	HRCWL_CORE_TO_CSB_3X1)
-#elif 0 /*264/132*/
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_1X1 |\
-	HRCWL_CSB_TO_CLKIN |\
-	HRCWL_VCO_1X4 |\
-	HRCWL_CORE_TO_CSB_2X1)
-#elif 0 /*132/132*/
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_1X1 |\
-	HRCWL_CSB_TO_CLKIN |\
-	HRCWL_VCO_1X4 |\
-	HRCWL_CORE_TO_CSB_1X1)
-#elif 0 /*264/264 */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_1X1 |\
-	HRCWL_CSB_TO_CLKIN |\
-	HRCWL_VCO_1X4 |\
-	HRCWL_CORE_TO_CSB_1X1)
-#endif
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_AGENT |\
-	HRCWH_64_BIT_PCI |\
-	HRCWH_PCI1_ARBITER_DISABLE |\
-	HRCWH_PCI2_ARBITER_DISABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0X00000100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_TSEC1M_IN_GMII |\
-	HRCWH_TSEC2M_IN_GMII)
-#else
-#if defined(CONFIG_PCI_64BIT)
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_HOST |\
-	HRCWH_64_BIT_PCI |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_PCI2_ARBITER_DISABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0X00000100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_TSEC1M_IN_GMII |\
-	HRCWH_TSEC2M_IN_GMII)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_HOST |\
-	HRCWH_32_BIT_PCI |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_PCI2_ARBITER_ENABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0X00000100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_TSEC1M_IN_GMII |\
-	HRCWH_TSEC2M_IN_GMII)
-#endif /* CONFIG_PCI_64BIT */
-#endif /* CONFIG_PCISLAVE */
-
 /*
  * System performance
  */
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index e170271c40d..6860c727946 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -39,10 +39,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
-#define CONFIG_SYS_LOWBOOT
-#endif
-
 /*
  * High Level Configuration Options
  */
@@ -461,41 +457,6 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
 
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_1X1 |\
-	HRCWL_CSB_TO_CLKIN_4X1 |\
-	HRCWL_VCO_1X2 |\
-	HRCWL_CORE_TO_CSB_2X1)
-
-#ifdef CONFIG_SYS_LOWBOOT
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_HOST |\
-	HRCWH_32_BIT_PCI |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_PCI2_ARBITER_ENABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0X00000100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_TSEC1M_IN_GMII |\
-	HRCWH_TSEC2M_IN_GMII)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_HOST |\
-	HRCWH_32_BIT_PCI |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_PCI2_ARBITER_ENABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0XFFF00100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_TSEC1M_IN_GMII |\
-	HRCWH_TSEC2M_IN_GMII)
-#endif
-
 /*
  * System performance
  */
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 33c485aab78..8c562fde2e5 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -12,48 +12,6 @@
  */
 #define CONFIG_E300		1 /* E300 family */
 
-/*
- * Hardware Reset Configuration Word
- * if CLKIN is 66MHz, then
- * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
- */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_1X1 |\
-	HRCWL_SVCOD_DIV_2 |\
-	HRCWL_CSB_TO_CLKIN_6X1 |\
-	HRCWL_CORE_TO_CSB_1_5X1)
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_AGENT |\
-	HRCWH_PCI1_ARBITER_DISABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0XFFF00100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_RL_EXT_LEGACY |\
-	HRCWH_TSEC1M_IN_RGMII |\
-	HRCWH_TSEC2M_IN_RGMII |\
-	HRCWH_BIG_ENDIAN |\
-	HRCWH_LDP_CLEAR)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_HOST |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0X00000100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_RL_EXT_LEGACY |\
-	HRCWH_TSEC1M_IN_RGMII |\
-	HRCWH_TSEC2M_IN_RGMII |\
-	HRCWH_BIG_ENDIAN |\
-	HRCWH_LDP_CLEAR)
-#endif
-
 /* Arbiter Configuration Register */
 #define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth is 4 */
 #define CONFIG_SYS_ACR_RPTCNT	3	/* Arbiter repeat count is 4 */
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 806b0f32e54..055a30e24fc 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -20,46 +20,6 @@
  */
 #define CONFIG_VSC7385_ENET
 
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_1X1 |\
-	HRCWL_SVCOD_DIV_2 |\
-	HRCWL_CSB_TO_CLKIN_5X1 |\
-	HRCWL_CORE_TO_CSB_2X1)
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_AGENT |\
-	HRCWH_PCI1_ARBITER_DISABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0XFFF00100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_RL_EXT_LEGACY |\
-	HRCWH_TSEC1M_IN_RGMII |\
-	HRCWH_TSEC2M_IN_RGMII |\
-	HRCWH_BIG_ENDIAN |\
-	HRCWH_LDP_CLEAR)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_HOST |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0X00000100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_RL_EXT_LEGACY |\
-	HRCWH_TSEC1M_IN_RGMII |\
-	HRCWH_TSEC2M_IN_RGMII |\
-	HRCWH_BIG_ENDIAN |\
-	HRCWH_LDP_CLEAR)
-#endif
-
 /* System performance - define the value i.e. CONFIG_SYS_XXX
 */
 
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 58c301553e3..be1c2893f16 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -260,41 +260,6 @@
 				/* Initial Memory map for Linux */
 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
 
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_1X1 |\
-	HRCWL_CSB_TO_CLKIN_4X1 |\
-	HRCWL_VCO_1X2 |\
-	HRCWL_CORE_TO_CSB_2X1)
-
-#if defined(CONFIG_PCI_64BIT)
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_HOST |\
-	HRCWH_64_BIT_PCI |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_PCI2_ARBITER_DISABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0X00000100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_TSEC1M_IN_GMII |\
-	HRCWH_TSEC2M_IN_GMII)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_HOST |\
-	HRCWH_32_BIT_PCI |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_PCI2_ARBITER_DISABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0X00000100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_TSEC1M_IN_GMII |\
-	HRCWH_TSEC2M_IN_GMII)
-#endif
-
 /* System IO Config */
 #define CONFIG_SYS_SICRH	0
 #define CONFIG_SYS_SICRL	SICRL_LDP_A
diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h
index 68fb989856c..5e88bd7edab 100644
--- a/include/configs/caddy2.h
+++ b/include/configs/caddy2.h
@@ -25,12 +25,6 @@
 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */
 #undef CONFIG_MPC83XX_PCI2		/* support for 2nd PCI controller */
 
-#ifdef CONFIG_PCI_66M
-#define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_4X1
-#else
-#define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_8X1
-#endif
-
 #define CONFIG_SYS_IMMR		0xE0000000
 
 #undef CONFIG_SYS_DRAM_TEST			/* memory test, takes time */
@@ -290,41 +284,6 @@
 
 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_1X1 |\
-	HRCWL_CSB_TO_CLKIN |\
-	HRCWL_VCO_1X2 |\
-	HRCWL_CORE_TO_CSB_2X1)
-
-#if defined(PCI_64BIT)
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_HOST |\
-	HRCWH_64_BIT_PCI |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_PCI2_ARBITER_DISABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0X00000100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_TSEC1M_IN_GMII |\
-	HRCWH_TSEC2M_IN_GMII)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_HOST |\
-	HRCWH_32_BIT_PCI |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_PCI2_ARBITER_ENABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0X00000100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_TSEC1M_IN_GMII |\
-	HRCWH_TSEC2M_IN_GMII)
-#endif
-
 /* System IO Config */
 #define CONFIG_SYS_SICRH 0
 #define CONFIG_SYS_SICRL SICRL_LDP_A
diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h
index 8eb12b76709..c1fe6b45bd5 100644
--- a/include/configs/hrcon.h
+++ b/include/configs/hrcon.h
@@ -17,38 +17,6 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
 
 /*
- * Hardware Reset Configuration Word
- * if CLKIN is 66.66MHz, then
- * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
- * We choose the A type silicon as default, so the core is 400Mhz.
- */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_2X1 |\
-	HRCWL_SVCOD_DIV_2 |\
-	HRCWL_CSB_TO_CLKIN_4X1 |\
-	HRCWL_CORE_TO_CSB_3X1)
-/*
- * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
- * in 8308's HRCWH according to the manual, but original Freescale's
- * code has them and I've expirienced some problems using the board
- * with BDI3000 attached when I've tried to set these bits to zero
- * (UART doesn't work after the 'reset run' command).
- */
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_HOST |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0XFFF00100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_RL_EXT_LEGACY |\
-	HRCWH_TSEC1M_IN_RGMII |\
-	HRCWH_TSEC2M_IN_RGMII |\
-	HRCWH_BIG_ENDIAN)
-
-/*
  * System IO Config
  */
 #define CONFIG_SYS_SICRH (\
diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h
index eff0addd519..4e5927ed700 100644
--- a/include/configs/ids8313.h
+++ b/include/configs/ids8313.h
@@ -25,27 +25,6 @@
 #define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
 #define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
 
-/*
- * Hardware Reset Configuration Word
- * if CLKIN is 66.000MHz, then
- * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz
- */
-#define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\
-			     HRCWL_DDR_TO_SCB_CLK_2X1 |\
-			     HRCWL_CSB_TO_CLKIN_2X1 |\
-			     HRCWL_CORE_TO_CSB_2X1)
-
-#define CONFIG_SYS_HRCW_HIGH	(HRCWH_PCI_HOST |\
-				 HRCWH_CORE_ENABLE |\
-				 HRCWH_FROM_0XFFF00100 |\
-				 HRCWH_BOOTSEQ_DISABLE |\
-				 HRCWH_SW_WATCHDOG_DISABLE |\
-				 HRCWH_ROM_LOC_LOCAL_8BIT |\
-				 HRCWH_RL_EXT_LEGACY |\
-				 HRCWH_TSEC1M_IN_MII |\
-				 HRCWH_TSEC2M_IN_MII |\
-				 HRCWH_BIG_ENDIAN)
-
 #define CONFIG_SYS_SICRH	0x00000000
 #define CONFIG_SYS_SICRL	(SICRL_LBC | SICRL_SPI_D)
 
diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h
index ec65a4208b9..7e579db6ae9 100644
--- a/include/configs/kmcoge5ne.h
+++ b/include/configs/kmcoge5ne.h
@@ -318,25 +318,6 @@
  */
 #define CONFIG_SYS_SICRH		(SICRH_UC1EOBI | SICRH_UC2E1OBI)
 
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_CSB_TO_CLKIN_4X1 | \
-	HRCWL_CORE_TO_CSB_2X1 | \
-	HRCWL_CE_PLL_VCO_DIV_2 | \
-	HRCWL_CE_TO_PLL_1X6)
-
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_CORE_ENABLE | \
-	HRCWH_FROM_0X00000100 | \
-	HRCWH_BOOTSEQ_DISABLE | \
-	HRCWH_SW_WATCHDOG_DISABLE | \
-	HRCWH_ROM_LOC_LOCAL_16BIT | \
-	HRCWH_BIG_ENDIAN | \
-	HRCWH_LALE_EARLY | \
-	HRCWH_LDP_CLEAR)
-
 /**
  * DDR RAM settings
  */
diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
index 2280f007f2f..3a98f9497b4 100644
--- a/include/configs/kmeter1.h
+++ b/include/configs/kmeter1.h
@@ -304,25 +304,6 @@
  */
 #define CONFIG_SYS_SICRH		(SICRH_UC1EOBI | SICRH_UC2E1OBI)
 
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_CSB_TO_CLKIN_4X1 | \
-	HRCWL_CORE_TO_CSB_2X1 | \
-	HRCWL_CE_PLL_VCO_DIV_2 | \
-	HRCWL_CE_TO_PLL_1X6)
-
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_CORE_ENABLE | \
-	HRCWH_FROM_0X00000100 | \
-	HRCWH_BOOTSEQ_DISABLE | \
-	HRCWH_SW_WATCHDOG_DISABLE | \
-	HRCWH_ROM_LOC_LOCAL_16BIT | \
-	HRCWH_BIG_ENDIAN | \
-	HRCWH_LALE_EARLY | \
-	HRCWH_LDP_CLEAR)
-
 /**
  * DDR RAM settings
  */
diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h
index fa12d41080a..44944754867 100644
--- a/include/configs/kmopti2.h
+++ b/include/configs/kmopti2.h
@@ -323,28 +323,6 @@
  */
 #define CONFIG_SYS_SICRL	SICRL_IRQ_CKS
 
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
-	HRCWL_DDR_TO_SCB_CLK_2X1 | \
-	HRCWL_CSB_TO_CLKIN_2X1 | \
-	HRCWL_CORE_TO_CSB_2_5X1 | \
-	HRCWL_CE_PLL_VCO_DIV_2 | \
-	HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_AGENT | \
-	HRCWH_PCI_ARBITER_DISABLE | \
-	HRCWH_CORE_ENABLE | \
-	HRCWH_FROM_0X00000100 | \
-	HRCWH_BOOTSEQ_DISABLE | \
-	HRCWH_SW_WATCHDOG_DISABLE | \
-	HRCWH_ROM_LOC_LOCAL_16BIT | \
-	HRCWH_BIG_ENDIAN | \
-	HRCWH_LALE_NORMAL)
-
 #define CONFIG_SYS_DDRCDR (\
 	DDRCDR_EN | \
 	DDRCDR_PZ_MAXZ | \
diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h
index 30898c0b75c..7c008f8516c 100644
--- a/include/configs/kmsupx5.h
+++ b/include/configs/kmsupx5.h
@@ -323,28 +323,6 @@
  */
 #define CONFIG_SYS_SICRL	SICRL_IRQ_CKS
 
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
-	HRCWL_DDR_TO_SCB_CLK_2X1 | \
-	HRCWL_CSB_TO_CLKIN_2X1 | \
-	HRCWL_CORE_TO_CSB_2_5X1 | \
-	HRCWL_CE_PLL_VCO_DIV_2 | \
-	HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_AGENT | \
-	HRCWH_PCI_ARBITER_DISABLE | \
-	HRCWH_CORE_ENABLE | \
-	HRCWH_FROM_0X00000100 | \
-	HRCWH_BOOTSEQ_DISABLE | \
-	HRCWH_SW_WATCHDOG_DISABLE | \
-	HRCWH_ROM_LOC_LOCAL_16BIT | \
-	HRCWH_BIG_ENDIAN | \
-	HRCWH_LALE_NORMAL)
-
 #define CONFIG_SYS_DDRCDR (\
 	DDRCDR_EN | \
 	DDRCDR_PZ_MAXZ | \
diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h
index 329a5cfe0fe..95b16ca5852 100644
--- a/include/configs/kmtegr1.h
+++ b/include/configs/kmtegr1.h
@@ -374,28 +374,6 @@
 #define CONFIG_SYS_GP2DIR 0xFF000000
 #define CONFIG_SYS_GP2ODR 0x00000000
 
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
-	HRCWL_DDR_TO_SCB_CLK_2X1 | \
-	HRCWL_CSB_TO_CLKIN_2X1 | \
-	HRCWL_CORE_TO_CSB_2X1 | \
-	HRCWL_CE_PLL_VCO_DIV_2 | \
-	HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_AGENT | \
-	HRCWH_PCI_ARBITER_DISABLE | \
-	HRCWH_CORE_ENABLE | \
-	HRCWH_FROM_0X00000100 | \
-	HRCWH_BOOTSEQ_DISABLE | \
-	HRCWH_SW_WATCHDOG_DISABLE | \
-	HRCWH_ROM_LOC_LOCAL_16BIT | \
-	HRCWH_BIG_ENDIAN | \
-	HRCWH_LALE_NORMAL)
-
 #define CONFIG_SYS_DDRCDR (\
 	DDRCDR_EN | \
 	DDRCDR_PZ_MAXZ | \
diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h
index 02b72c874e1..5191f2c4b01 100644
--- a/include/configs/kmtepr2.h
+++ b/include/configs/kmtepr2.h
@@ -323,28 +323,6 @@
  */
 #define CONFIG_SYS_SICRL	SICRL_IRQ_CKS
 
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
-	HRCWL_DDR_TO_SCB_CLK_2X1 | \
-	HRCWL_CSB_TO_CLKIN_2X1 | \
-	HRCWL_CORE_TO_CSB_2_5X1 | \
-	HRCWL_CE_PLL_VCO_DIV_2 | \
-	HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_AGENT | \
-	HRCWH_PCI_ARBITER_DISABLE | \
-	HRCWH_CORE_ENABLE | \
-	HRCWH_FROM_0X00000100 | \
-	HRCWH_BOOTSEQ_DISABLE | \
-	HRCWH_SW_WATCHDOG_DISABLE | \
-	HRCWH_ROM_LOC_LOCAL_16BIT | \
-	HRCWH_BIG_ENDIAN | \
-	HRCWH_LALE_NORMAL)
-
 #define CONFIG_SYS_DDRCDR (\
 	DDRCDR_EN | \
 	DDRCDR_PZ_MAXZ | \
diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h
index c21b9ba38f1..cc88f071ec6 100644
--- a/include/configs/kmvect1.h
+++ b/include/configs/kmvect1.h
@@ -366,28 +366,6 @@
 #define CONFIG_SYS_GP2DIR 0xFF000000
 #define CONFIG_SYS_GP2ODR 0x00000000
 
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
-	HRCWL_DDR_TO_SCB_CLK_2X1 | \
-	HRCWL_CSB_TO_CLKIN_2X1 | \
-	HRCWL_CORE_TO_CSB_2X1 | \
-	HRCWL_CE_PLL_VCO_DIV_2 | \
-	HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_AGENT | \
-	HRCWH_PCI_ARBITER_DISABLE | \
-	HRCWH_CORE_ENABLE | \
-	HRCWH_FROM_0X00000100 | \
-	HRCWH_BOOTSEQ_DISABLE | \
-	HRCWH_SW_WATCHDOG_DISABLE | \
-	HRCWH_ROM_LOC_LOCAL_16BIT | \
-	HRCWH_BIG_ENDIAN | \
-	HRCWH_LALE_NORMAL)
-
 #define CONFIG_SYS_DDRCDR (\
 	DDRCDR_EN | \
 	DDRCDR_PZ_MAXZ | \
diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h
index fd59471370d..2822aa3b9da 100644
--- a/include/configs/mpc8308_p1m.h
+++ b/include/configs/mpc8308_p1m.h
@@ -22,38 +22,6 @@
 #define CONFIG_TSEC2
 
 /*
- * Hardware Reset Configuration Word
- * if CLKIN is 66.66MHz, then
- * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
- * We choose the A type silicon as default, so the core is 400Mhz.
- */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_2X1 |\
-	HRCWL_SVCOD_DIV_2 |\
-	HRCWL_CSB_TO_CLKIN_4X1 |\
-	HRCWL_CORE_TO_CSB_3X1)
-/*
- * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
- * in 8308's HRCWH according to the manual, but original Freescale's
- * code has them and I've expirienced some problems using the board
- * with BDI3000 attached when I've tried to set these bits to zero
- * (UART doesn't work after the 'reset run' command).
- */
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_HOST |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0X00000100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_RL_EXT_LEGACY |\
-	HRCWH_TSEC1M_IN_MII |\
-	HRCWH_TSEC2M_IN_MII |\
-	HRCWH_BIG_ENDIAN)
-
-/*
  * System IO Config
  */
 #define CONFIG_SYS_SICRH (\
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 2520a77dd3c..fd67aca2079 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -22,12 +22,6 @@
 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
 #undef CONFIG_MPC83XX_PCI2		/* support for 2nd PCI controller */
 
-#ifdef CONFIG_PCI_33M
-#define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_8X1
-#else	/* 66M */
-#define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_4X1
-#endif
-
 #define CONFIG_SYS_IMMR		0xE0000000
 
 #undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
@@ -374,71 +368,6 @@
 
 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 
-#if 1 /*528/264*/
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_1X1 |\
-	HRCWL_CSB_TO_CLKIN |\
-	HRCWL_VCO_1X2 |\
-	HRCWL_CORE_TO_CSB_2X1)
-#elif 0 /*396/132*/
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_1X1 |\
-	HRCWL_CSB_TO_CLKIN |\
-	HRCWL_VCO_1X4 |\
-	HRCWL_CORE_TO_CSB_3X1)
-#elif 0 /*264/132*/
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_1X1 |\
-	HRCWL_CSB_TO_CLKIN |\
-	HRCWL_VCO_1X4 |\
-	HRCWL_CORE_TO_CSB_2X1)
-#elif 0 /*132/132*/
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_1X1 |\
-	HRCWL_CSB_TO_CLKIN |\
-	HRCWL_VCO_1X4 |\
-	HRCWL_CORE_TO_CSB_1X1)
-#elif 0 /*264/264 */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_1X1 |\
-	HRCWL_CSB_TO_CLKIN |\
-	HRCWL_VCO_1X4 |\
-	HRCWL_CORE_TO_CSB_1X1)
-#endif
-
-#if defined(CONFIG_PCI_64BIT)
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_HOST |\
-	HRCWH_64_BIT_PCI |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_PCI2_ARBITER_DISABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0X00000100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_TSEC1M_IN_GMII |\
-	HRCWH_TSEC2M_IN_GMII)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_HOST |\
-	HRCWH_32_BIT_PCI |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_PCI2_ARBITER_ENABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0X00000100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_TSEC1M_IN_GMII |\
-	HRCWH_TSEC2M_IN_GMII)
-#endif
-
 /* System IO Config */
 #define CONFIG_SYS_SICRH 0
 #define CONFIG_SYS_SICRL SICRL_LDP_A
diff --git a/include/configs/strider.h b/include/configs/strider.h
index 8c9acfba8d5..ef33eaef9b0 100644
--- a/include/configs/strider.h
+++ b/include/configs/strider.h
@@ -17,38 +17,6 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
 
 /*
- * Hardware Reset Configuration Word
- * if CLKIN is 66.66MHz, then
- * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
- * We choose the A type silicon as default, so the core is 400Mhz.
- */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_2X1 |\
-	HRCWL_SVCOD_DIV_2 |\
-	HRCWL_CSB_TO_CLKIN_4X1 |\
-	HRCWL_CORE_TO_CSB_3X1)
-/*
- * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
- * in 8308's HRCWH according to the manual, but original Freescale's
- * code has them and I've expirienced some problems using the board
- * with BDI3000 attached when I've tried to set these bits to zero
- * (UART doesn't work after the 'reset run' command).
- */
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_HOST |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0XFFF00100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_RL_EXT_LEGACY |\
-	HRCWH_TSEC1M_IN_MII |\
-	HRCWH_TSEC2M_IN_RGMII |\
-	HRCWH_BIG_ENDIAN)
-
-/*
  * System IO Config
  */
 #define CONFIG_SYS_SICRH (\
diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h
index 87f7390bcc2..c84c7c0f6e2 100644
--- a/include/configs/suvd3.h
+++ b/include/configs/suvd3.h
@@ -320,28 +320,6 @@
  */
 #define CONFIG_SYS_SICRL	SICRL_IRQ_CKS
 
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
-	HRCWL_DDR_TO_SCB_CLK_2X1 | \
-	HRCWL_CSB_TO_CLKIN_2X1 | \
-	HRCWL_CORE_TO_CSB_2_5X1 | \
-	HRCWL_CE_PLL_VCO_DIV_2 | \
-	HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_AGENT | \
-	HRCWH_PCI_ARBITER_DISABLE | \
-	HRCWH_CORE_ENABLE | \
-	HRCWH_FROM_0X00000100 | \
-	HRCWH_BOOTSEQ_DISABLE | \
-	HRCWH_SW_WATCHDOG_DISABLE | \
-	HRCWH_ROM_LOC_LOCAL_16BIT | \
-	HRCWH_BIG_ENDIAN | \
-	HRCWH_LALE_NORMAL)
-
 #define CONFIG_SYS_DDRCDR (\
 	DDRCDR_EN | \
 	DDRCDR_PZ_MAXZ | \
diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h
index 1cd0985dc29..8f60db30550 100644
--- a/include/configs/tuge1.h
+++ b/include/configs/tuge1.h
@@ -323,28 +323,6 @@
  */
 #define CONFIG_SYS_SICRL	SICRL_IRQ_CKS
 
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
-	HRCWL_DDR_TO_SCB_CLK_2X1 | \
-	HRCWL_CSB_TO_CLKIN_2X1 | \
-	HRCWL_CORE_TO_CSB_2_5X1 | \
-	HRCWL_CE_PLL_VCO_DIV_2 | \
-	HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_AGENT | \
-	HRCWH_PCI_ARBITER_DISABLE | \
-	HRCWH_CORE_ENABLE | \
-	HRCWH_FROM_0X00000100 | \
-	HRCWH_BOOTSEQ_DISABLE | \
-	HRCWH_SW_WATCHDOG_DISABLE | \
-	HRCWH_ROM_LOC_LOCAL_16BIT | \
-	HRCWH_BIG_ENDIAN | \
-	HRCWH_LALE_NORMAL)
-
 #define CONFIG_SYS_DDRCDR (\
 	DDRCDR_EN | \
 	DDRCDR_PZ_MAXZ | \
diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h
index d476a75e3ee..58c6089becb 100644
--- a/include/configs/tuxx1.h
+++ b/include/configs/tuxx1.h
@@ -323,28 +323,6 @@
  */
 #define CONFIG_SYS_SICRL	SICRL_IRQ_CKS
 
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
-	HRCWL_DDR_TO_SCB_CLK_2X1 | \
-	HRCWL_CSB_TO_CLKIN_2X1 | \
-	HRCWL_CORE_TO_CSB_2_5X1 | \
-	HRCWL_CE_PLL_VCO_DIV_2 | \
-	HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_AGENT | \
-	HRCWH_PCI_ARBITER_DISABLE | \
-	HRCWH_CORE_ENABLE | \
-	HRCWH_FROM_0X00000100 | \
-	HRCWH_BOOTSEQ_DISABLE | \
-	HRCWH_SW_WATCHDOG_DISABLE | \
-	HRCWH_ROM_LOC_LOCAL_16BIT | \
-	HRCWH_BIG_ENDIAN | \
-	HRCWH_LALE_NORMAL)
-
 #define CONFIG_SYS_DDRCDR (\
 	DDRCDR_EN | \
 	DDRCDR_PZ_MAXZ | \
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index 2ef6f88bdf6..c4bdfe574a7 100644
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -308,25 +308,6 @@
 				/* Initial Memory map for Linux*/
 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
 
-/* 0x64050000 */
-#define CONFIG_SYS_HRCW_LOW (\
-	0x20000000 /* reserved, must be set */ |\
-	HRCWL_DDRCM |\
-	HRCWL_CSB_TO_CLKIN_4X1 | \
-	HRCWL_CORE_TO_CSB_2_5X1)
-
-/* 0xa0600004 */
-#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \
-	HRCWH_PCI_ARBITER_ENABLE | \
-	HRCWH_CORE_ENABLE | \
-	HRCWH_FROM_0X00000100 | \
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT | \
-	HRCWH_TSEC1M_IN_MII | \
-	HRCWH_BIG_ENDIAN | \
-	HRCWH_LALE_EARLY)
-
 /* System IO Config */
 #define CONFIG_SYS_SICRH	(0x01000000 | \
 				SICRH_ETSEC2_B | \
diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index c5086958ff3..ca6233a26ec 100644
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -25,14 +25,6 @@
 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */
 #undef CONFIG_MPC83XX_PCI2		/* support for 2nd PCI controller */
 
-#define CONFIG_PCI_66M
-
-#ifdef CONFIG_PCI_66M
-#define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_4X1
-#else
-#define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_8X1
-#endif
-
 #define CONFIG_SYS_IMMR		0xE0000000
 
 #undef CONFIG_SYS_DRAM_TEST			/* memory test, takes time */
@@ -292,41 +284,6 @@
 
 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-	HRCWL_DDR_TO_SCB_CLK_1X1 |\
-	HRCWL_CSB_TO_CLKIN |\
-	HRCWL_VCO_1X2 |\
-	HRCWL_CORE_TO_CSB_2X1)
-
-#if defined(CONFIG_PCI_64BIT)
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_HOST |\
-	HRCWH_64_BIT_PCI |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_PCI2_ARBITER_DISABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0X00000100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_TSEC1M_IN_GMII |\
-	HRCWH_TSEC2M_IN_GMII)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_HOST |\
-	HRCWH_32_BIT_PCI |\
-	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_PCI2_ARBITER_ENABLE |\
-	HRCWH_CORE_ENABLE |\
-	HRCWH_FROM_0X00000100 |\
-	HRCWH_BOOTSEQ_DISABLE |\
-	HRCWH_SW_WATCHDOG_DISABLE |\
-	HRCWH_ROM_LOC_LOCAL_16BIT |\
-	HRCWH_TSEC1M_IN_GMII |\
-	HRCWH_TSEC2M_IN_GMII)
-#endif
-
 /* System IO Config */
 #define CONFIG_SYS_SICRH 0
 #define CONFIG_SYS_SICRL SICRL_LDP_A