Squashed 'dts/upstream/' changes from aaba2d45dc2a..b35b9bd1d4ee

b35b9bd1d4ee Merge tag 'v6.8-dts-raw'
1f50937554b4 Merge tag 'sound-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
576ba37bcbf9 Merge tag 'net-6.8-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
c83dc02bae3e Merge tag 'qcom-arm64-fixes-for-6.8-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes
fb254675a395 ASoC: dt-bindings: nvidia: Fix 'lge' vendor prefix
c748b8a7dbe8 Merge tag 'tegra-for-6.8-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/fixes
a2e893adde74 Merge tag 'imx-fixes-6.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
abb0f1b369e4 Merge tag 'qcom-arm64-fixes-for-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes
f143aa9a89ec Revert "arm64: dts: qcom: msm8996: Hook up MPM"
9a5690b7be49 arm64: dts: qcom: sc8280xp-x13s: limit pcie4 link speed
ca6dcb63bd34 arm64: dts: qcom: sc8280xp-crd: limit pcie4 link speed
8532bb680bd0 dt-bindings: net: renesas,ethertsn: Document default for delays
42569705a4a0 Merge tag 'v6.8-rc6-dts-raw'
06c62487a0b4 arm64: dts: imx8mp: Fix LDB clocks property
7c93039778e4 arm64: dts: imx8mp: Fix TC9595 reset GPIO on DH i.MX8M Plus DHCOM SoM
7f9a36c5ce39 ARM: dts: imx7: remove DSI port endpoints
87ea8526eaf3 Merge tag 'loongarch-fixes-6.8-3' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
d4a4b892cd33 Merge tag 'arm-fixes-6.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
4faf103c7468 Merge tag 'renesas-fixes-for-v6.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/fixes
c1858748b935 Merge tag 'riscv-dt-fixes-for-v6.8-rc6' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into arm/fixes
f1bb487d660f LoongArch: dts: Minor whitespace cleanup
b60485a78d66 Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
d641a222a5d4 arm64: tegra: Fix Tegra234 MGBE power-domains
31aeabc2669e ARM: dts: renesas: rcar-gen2: Add missing #interrupt-cells to DA9063 nodes
8c5d69d4f1e9 arm64: dts: qcom: Fix interrupt-map cell sizes
43b35c5b7347 arm: dts: Fix dtc interrupt_map warnings
f00ce91341b9 arm64: dts: Fix dtc interrupt_provider warnings
c21ad68d3254 arm: dts: Fix dtc interrupt_provider warnings
20a9f605f025 Merge tag 'v6.8-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes
1d9be1dcae7c Merge tag 'imx-fixes-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
c27426925b7b Merge tag 'v6.8-rc5-dts-raw'
582c3e28f603 Merge tag 'sound-6.8-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
81da29f3007e arm64: tegra: Set the correct PHY mode for MGBE
30e4bc5d76ff Merge tag 'devicetree-fixes-for-6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
f0c34a9f448e riscv: dts: sifive: add missing #interrupt-cells to pmic
db36be2a8839 arm64: dts: rockchip: Correct Indiedroid Nova GPIO Names
ec7d411e57d6 arm64: dts: rockchip: Drop interrupts property from rk3328 pwm-rockchip node
105b1e4e5e28 arm64: dts: rockchip: set num-cs property for spi on px30
a05f0ca9a008 arm64: dts: rockchip: minor rk3588 whitespace cleanup
41d6b3786aa9 riscv: dts: starfive: replace underscores in node names
910c8965eb0c dt-bindings: ufs: samsung,exynos-ufs: Add size constraints on "samsung,sysreg"
d78e8a541b0a net: marvell,prestera: Fix example PCI bus addressing
b40e56bea854 ASoC: dt-bindings: google,sc7280-herobrine: Drop bouncing @codeaurora
48b3246a26fe Revert "arm64: dts: imx8mn-var-som-symphony: Describe the USB-C connector"
a1c414f8f89a Revert "arm64: dts: imx8mp-dhcom-pdk3: Describe the USB-C connector"
768ad06f1efa arm64: dts: tqma8mpql: fix audio codec iov-supply
77040f90f388 Merge tag 'v6.8-rc3-dts-raw'
65143ffc8608 arm64: dts: rockchip: drop unneeded status from rk3588-jaguar gpio-leds
39497955d1c0 ARM: dts: rockchip: Drop interrupts property from pwm-rockchip nodes
610e244453be arm64: dts: rockchip: Fix the num-lanes of pcie3x4 on Cool Pi CM5 EVB
d6e600aea013 arm64: dts: rockchip: rename vcc5v0_usb30_host regulator for Cool Pi CM5 EVB
6be17990ec10 arm64: dts: rockchip: aliase sdmmc as mmc1 for Cool Pi CM5 EVB
77765eecb670 arm64: dts: rockchip: aliase sdmmc as mmc1 for Cool Pi 4B
7bca62b5ae66 arm64: dts: qcom: sm6115: Fix missing interconnect-names
b2bc58ba4504 arm64: dts: imx8mp: Disable UART4 by default on Data Modul i.MX8M Plus eDM SBC
9474eb5c3d86 ALSA: Various fixes for Cirrus Logic CS35L56 support
1e8df48d4da1 dt-bindings: tpm: Drop type from "resets"
4d5c46ab184f dt-bindings: display: nxp,tda998x: Fix 'audio-ports' constraints
fede8bd8306c dt-bindings: xilinx: replace Piyush Mehta maintainership
eb691d1ece78 Merge tag 'v6.8-rc2-dts-raw'
5b093a56e797 ASoC: sun4i-spdif: Add Allwinner H616 compatible
f2ce9dca7322 ASoC: sun4i-spdif: Fix requirements for H6
fd23c7505f20 arm64: dts: qcom: sm8650-mtp: add gpio74 as reserved gpio
cfbd9243ac13 arm64: dts: qcom: sm8650-qrd: add gpio74 as reserved gpio
101ce3470b0e Merge tag 'drm-fixes-2024-01-27' of git://anongit.freedesktop.org/drm/drm
71ca3bf1c96e Merge tag 'arm-fixes-6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
74c898882ebb riscv: dts: sophgo: separate sg2042 mtime and mtimecmp to fit aclint format
28b77b56d972 arm64: dts: rockchip: mark system power controller on rk3588-evb1
986a9f1778ef Merge tag 'samsung-fixes-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/fixes
6cf0227916ec arm64: dts: Fix TPM schema violations
60245a9006e9 ARM: dts: Fix TPM schema violations
92924d8db61a Merge tag 'exynos-drm-fixes-for-v6.8-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-fixes
3b240d0d94a9 dt-bindings: media: Remove K3 Family Prefix from Compatible
186b38b97035 ARM: dts: exynos4212-tab3: add samsung,invert-vclk flag to fimd
c4f0c99dffb8 arm64: dts: exynos: gs101: comply with the new cmu_misc clock names
429796fee0f1 dt-bindings: clock: gs101: rename cmu_misc clock-names
80d76b25d32f Merge tag 'v6.8-rc1-dts-raw'
339d8d1caab5 Merge tag 'timers-core-2024-01-21' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
df1980733ce9 Merge tag 'dmaengine-fix-6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
8c23badf69c3 Merge tag 'riscv-for-linus-6.8-mw4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
d5a95e32a555 Merge tag 'loongarch-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
815e38060bf4 Merge tag 'sound-fix-6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
f07a1b362766 Merge tag 'for-v6.8-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply
9411a3099e9c Merge tag 'i2c-for-6.8-rc1-rebased' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
fcb7108dc362 Merge tag 'rtc-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux
8e06ce5908ff Merge tag 'input-for-v6.8-rc0' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
7b18579c0bef Merge tag 'phy-for-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
dd4871a00012 Merge tag 'gpio-fixes-for-v6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux
8dfd2acd2c0c Merge tag 'backlight-next-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/backlight
736ecd5cf03c Merge tag 'iommu-updates-v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
7d29a06cb311 dt-bindings: i2c: document st,stm32mp25-i2c compatible
365a95704e98 dt-bindings: at24: add ROHM BR24G04
05d2a9834fd6 Merge tag 'usb-6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
70a7bee43907 Merge tag 'tty-6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
6a04bf7a4f07 Merge tag 'char-misc-6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
e0c35697cd80 Merge tag 'pci-v6.8-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
cf29a14b0a23 Merge tag 'pinctrl-v6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
902219ef9ed0 Merge tag 'mailbox-v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox
c437f65015a8 Merge tag 'leds-next-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/leds
d0902d05b4a0 Merge tag 'mfd-next-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
8be1d4636d32 Merge tag 'rproc-v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux
6eaaddf12639 Merge tag 'riscv-for-linus-6.8-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
2cb012b6fe68 LoongArch: dts: DeviceTree for Loongson-2K2000
6ab0a6f08b83 LoongArch: dts: DeviceTree for Loongson-2K1000
491426707de1 LoongArch: dts: DeviceTree for Loongson-2K0500
c007f27059d1 dt-bindings: interrupt-controller: loongson,liointc: Fix dtbs_check warning for interrupt-names
d9a3ae336ecb dt-bindings: interrupt-controller: loongson,liointc: Fix dtbs_check warning for reg-names
4ee19a9d7583 dt-bindings: loongarch: Add Loongson SoC boards compatibles
3e99ee3f7c53 dt-bindings: loongarch: Add CPU bindings for LoongArch
e8bc7c9c625e dt-bindings: don't anchor DT_SCHEMA_FILES to bindings directory
f5918b47370e dt-bindings: rtc: max31335: add max31335 bindings
7e34d7b53615 rtc: rv8803: add wakeup-source support
81d186f05921 Merge branch 'pci/dt-bindings'
8bd798490681 Merge branch 'pci/controller/rcar'
e166e5aad3b0 Merge branch 'pci/controller/cadence'
9de355a75fde dt-bindings: gpio: xilinx: Fix node address in gpio
28bf1e4e9775 dt-bindings: mailbox: qcom-ipcc: document the X1E80100 Inter-Processor Communication Controller
f6b31bdd3c60 dt-bindings: mailbox: add Versal IPI bindings
c3301d070937 dt-bindings: mailbox: zynqmp: extend required list
6bf977408719 dt-bindings: mailbox: qcom,apcs-kpss-global: use fallbacks
b9ea63718a7e dt-bindings: mailbox: qcom,apcs-kpss-global: drop duplicated qcom,ipq8074-apcs-apps-global
e485b251a3a4 Merge tag 'devicetree-for-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
60edd8755b1b Merge tag 'pwm/for-6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm
f946a0610062 Merge tag 'hid-for-linus-2024010801' of git://git.kernel.org/pub/scm/linux/kernel/git/hid/hid
5a9222178c60 Merge tag 'media/v6.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
0c57fa00ac11 Merge tag 'mmc-v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
120152dd192c Merge tag 'pmdomain-v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm
f25acec1f182 Merge tag 'gnss-6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/johan/gnss
040b6611cd72 Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
432f2b929aa4 Merge tag 'gpio-updates-for-v6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux
5df1a59e6086 Merge tag 'linux-watchdog-6.8-rc1' of git://www.linux-watchdog.org/linux-watchdog
1d81fba29be6 Merge tag 'hwmon-for-v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging
dd7110d3d5d1 Merge tag 'sound-6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
c916bd7a1d38 Merge tag 'drm-next-2024-01-10' of git://anongit.freedesktop.org/drm/drm
32704b03c7ec Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
c0d1d21fe5ff dt-bindings: fpga: altera: Convert bridge bindings to yaml
86986ec77fc7 dt-bindings: fpga: Convert bridge binding to yaml
149beabce38e dt-bindings: vendor-prefixes: Add smi
da831df01407 Merge tag 'soc-drivers-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
d0949aef9e29 Merge tag 'soc-dt-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
c5ee04d9a430 Merge tag 'net-next-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next
17d4b2f2c7c6 dt-bindings: riscv: Document cbop-block-size
6361e08793d7 dt-bindings: riscv: permit numbers in "riscv,isa"
99f0fa81f51f dt-bindings: riscv: cpus: Clarify mmu-type interpretation
5744984c407c ARM: dts: usr8200: Fix phy registers
fd6e692990ee dt-bindings: PCI: brcmstb: Add property "brcm,clkreq-mode"
db07ea081cee dt-bindings: power: Clarify wording for wakeup-source property
9deb5d7e7649 Merge tag 'v6.8-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
f412e763e552 dt-bindings: mfd: sprd: Add support for UMS9620
b50b2489e1a2 dt-bindings: input: bindings for Adafruit Seesaw Gamepad
9fcf5401177c Merge patch series "riscv: hwprobe: add Zicond, Zacas and Ztso support"
6b479ffcb9ed dt-bindings: riscv: add Zacas ISA extension description
45e895d242d0 Merge remote-tracking branch 'palmer/fixes' into for-next
129abc9e5b89 Merge tag 'thermal-6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
72e795875f31 Merge tag 'mtd/for-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
a0d6ec02f5dd Merge tag 'spi-v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
092d72f89f32 Merge tag 'regulator-v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator
f19bbcb501a1 Merge branch 'clk-rs9' into clk-next
6c5ff3361f38 Merge branches 'clk-zynq', 'clk-xilinx' and 'clk-stm' into clk-next
5348f28123c3 Merge branches 'clk-imx', 'clk-qcom', 'clk-amlogic' and 'clk-mediatek' into clk-next
dde8a0d89600 Merge branches 'clk-versa', 'clk-silabs', 'clk-samsung', 'clk-starfive' and 'clk-sophgo' into clk-next
147299598f64 dt-bindings: ignore paths outside kernel for DT_SCHEMA_FILES
5e8ad2415574 dt-bindings: tpm: Document Microsoft fTPM bindings
4446def763e6 dt-bindings: tpm: Convert IBM vTPM bindings to DT schema
d46251bba773 dt-bindings: tpm: Convert Google Cr50 bindings to DT schema
4c0c46fcf77f dt-bindings: tpm: Consolidate TCG TIS bindings
fc825b2e9d71 dt-bindings: display: rockchip,inno-hdmi: Document RK3128 compatible
5d51cf126484 dt-bindings: arm: Add remote etm dt-binding
32c458bd3442 dt-bindings: mmc: sdhci-pxa: Fix 'regs' typo
c9ab453dff7c media: dt-bindings: samsung,s5p-mfc: Fix iommu properties schemas
481554b6b752 dt-bindings: display: panel: Add synaptics r63353 panel controller
e04e21bef16e dt-bindings: arm: merge qcom,idle-state with idle-state
452e35e6ff26 Merge tag 'irq-core-2024-01-08' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
d35742374b96 dt-bindings: display: samsung,exynos-mixer: Fix 'regs' typo
ac8ffc6d0764 Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
daf5be0b133e Merge tag 'powerpc-6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
b633610fad05 Revert "net: stmmac: Enable Per DMA Channel interrupt"
fc2b6856183b dt-bindings: rtc: qcom-pm8xxx: fix inconsistent example
5c111c61a49a dt-bindings: net: snps,dwmac: per channel irq
94d319464237 ASoC: dt-bindings: move tas2563 from tas2562.yaml to tas2781.yaml
8fbbcaccc3ff Merge tag 'socfpga_dts_updates_for_v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt
1161aaee27ae dt-bindings: mmc: add Marvell ac5
e9a747531a5d dt-bindings: mmc: brcm,sdhci-brcmstb: Add support for 74165b0
57b4e3b1199f Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
cab393f5e80d dt-bindings: serial: Describe ARM dcc interface
1d92607a561e dt-bindings: usb: dwc3: Limit num-hc-interrupters definition
cee9797861a0 dt-bindings: usb: xhci: Add num-hc-interrupters definition
4823f8dd230f arm64: dts: mediatek: mt8195: Add 'rx-fifo-depth' for cherry
4a4f48930e20 dt-bindings: usb: mtk-xhci: add a property for Gen1 isoc-in transfer issue
4ddd871b77e8 arm64: dts: qcom: msm8996: Remove PNoC clock from MSS
5598c7c58459 arm64: dts: qcom: msm8996: Remove AGGRE2 clock from SLPI
a06133f3b90d arm64: dts: qcom: msm8998: Remove AGGRE2 clock from SLPI
0e31729b965a arm64: dts: qcom: msm8939: Drop RPM bus clocks
a9231f1fa44d arm64: dts: qcom: sdm630: Drop RPM bus clocks
7806d0946f48 arm64: dts: qcom: qcs404: Drop RPM bus clocks
6bbd4a339ffd arm64: dts: qcom: msm8996: Drop RPM bus clocks
6c5785d4dec0 arm64: dts: qcom: msm8916: Drop RPM bus clocks
d99558e0d6ba dt-bindings: usb: qcom,dwc3: Fix SDM660 clock description
0e7834fa9ba2 dt-bindings: usb: dwc3: Clean up hs_phy_irq in binding
f7405c1062e5 dt-bindings: connector: Add child nodes for multiple PD capabilities
a2f2b957f7b0 arm64: dts: intel: minor whitespace cleanup around '='
a21ad91a14ac arm64: dts: socfpga: agilex: drop redundant status
c64326a0161d arm64: dts: socfpga: agilex: add unit address to soc node
70eea150a8db arm64: dts: socfpga: agilex: move firmware out of soc node
056acfded5ce arm64: dts: socfpga: agilex: move FPGA region out of soc node
8e373ef160c7 arm64: dts: socfpga: agilex: align pin-controller name with bindings
56a65e118b36 arm64: dts: socfpga: stratix10_swvp: drop unsupported DW MSHC properties
5ea405da6608 arm64: dts: socfpga: stratix10_socdk: align NAND chip name with bindings
0bc2b8deec9a arm64: dts: socfpga: stratix10: add unit address to soc node
3932c6fc63c2 arm64: dts: socfpga: stratix10: move firmware out of soc node
174dfac57ae2 arm64: dts: socfpga: stratix10: move FPGA region out of soc node
e63c11b1c86c arm64: dts: socfpga: stratix10: align pincfg nodes with bindings
5ad3116fb135 arm64: dts: socfpga: stratix10: add clock-names to DWC2 USB
9185b800f9c3 arm64: dts: socfpga: drop unsupported cdns,page-size and cdns,block-size
b3832f4d101c ARM: dts: socfpga: align NAND controller name with bindings
7772fcc4eef4 ARM: dts: socfpga: drop unsupported cdns,page-size and cdns,block-size
f466442c93ff dt-bindings: clock: mediatek: add clock controllers of MT7988
967ed08fdbd4 dt-bindings: reset: mediatek: add MT7988 ethwarp reset IDs
8bb435f3ea7d dt-bindings: clock: mediatek: add MT7988 clock IDs
8b8c659b2121 dt-bindings: clock: sophgo: Add clock controller of CV1800 series SoC
b822e804fd2c dt-bindings: gpio: add NPCM sgpio driver bindings
f4c19e862d2b dt-bindings: gpio: realtek: Add realtek,rtd-gpio
6690161ed7a9 Merge branches 'apple/dart', 'arm/rockchip', 'arm/smmu', 'virtio', 'x86/vt-d', 'x86/amd' and 'core' into next
7382fa53a648 dt-bindings: net: renesas,etheravb: Document RZ/G3S support
247b8886892f dt-bindings: hwmon: (lm75) Add AMS AS6200 temperature sensor
fec847c57a81 dt-bindings: Add MP2856/MP2857 voltage regulator device
42c42ff6c177 dt-bindings: hwmon: gpio-fan: Convert txt bindings to yaml
6c13c9d07051 dt-bindings: mmc: sdhci-msm: document dedicated IPQ4019 and IPQ8074
1e934476b96c dt-bindings: mmc: synopsys-dw-mshc: add iommus for Intel SocFPGA
82a434279c9e dt-bindings: HID: i2c-hid: elan: Introduce Ilitek ili2901
5fa4567d6c4f Merge tag 'v6.8-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
a04786e0b7e0 Merge tag 'v6.8-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
0bf9a2425459 Merge tag 'qcom-arm64-for-6.8-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
a3fde0732d5b Merge tag 'qcom-arm32-for-6.8-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
62073621d812 Merge tag 'arm-soc/for-6.8/devicetree' of https://github.com/Broadcom/stblinux into soc/dt
4cfe8fd4e2b4 Merge tag 'sprd-dt-6.8-rc1' of https://github.com/lyrazhang/linux into soc/dt
a355b8e8cbdd dt-bindings: thermal: qcom-spmi-adc-tm5/hc: Clean up examples
36a030b546d0 dt-bindings: thermal: qcom-spmi-adc-tm5/hc: Fix example node names
ca1c0a8c8091 dt-bindings: thermal: sun8i: Add binding for D1/T113s THS controller
7123707b90de dt-bindings: thermal-zones: Document critical-action
c29ec9b83fd7 dt-bindings: thermal: qcom-tsens: document the SM8650 Temperature Sensor
5a12787401b5 dt-bindings: thermal: loongson,ls2k-thermal: Fix binding check issues
0a6d923c5231 dt-bindings: thermal: convert Mediatek Thermal to the json-schema
dc5dd3862b77 dt-bindings: input: iqs269a: Add bindings for OTP variants
5aa00301cee3 dt-bindings: input: iqs269a: Add bindings for slider gestures
c4635c803af3 Merge tag 'iio-for-6.8b' of https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-next
571d91b8d8df arm64: dts: rockchip: Fix led pinctrl of lubancat 1
548cbdf62c21 arm64: dts: rockchip: correct gpio_pwrctrl1 typo on nanopc-t6
86c28823371d arm64: dts: rockchip: correct gpio_pwrctrl1 typo on rock-5b
275bc737b480 arm64: dts: rockchip: support poweroff on the rock-5b
e4f7332bb7f8 arm64: dts: rockchip: Support poweroff on Orange Pi 5
d0c46aeba839 arm64: dts: rockchip: nanopc-t6 sdmmc beautification
df73c00bc509 arm64: dts: sprd: Change UMS512 idle-state nodename to match bindings
12243eba2b74 arm64: dts: sprd: Add clock reference for pll2 on UMS512
af72bfcc73f3 arm64: dts: sprd: Removed unused clock references from etm nodes
d8f5562e697b arm64: dts: sprd: Add support for Unisoc's UMS9620
bd8f67f82f65 dt-bindings: arm: Add compatible strings for Unisoc's UMS9620
9da3db96fae0 arm64: dts: sprd: fix the cpu node for UMS512
3ebc08960525 Merge tag 'v6.7-rc7' into gpio/for-next
cb90fcbed71e dt-bindings: timer: Add StarFive JH8100 clint
6f2b19f4df72 dt-bindings: timer: thead,c900-aclint-mtimer: separate mtime and mtimecmp regs
4421b3e3124f dt-bindings: iio: Add AD7091R-8
51a0454cffd6 dt-bindings: power: supply: bq24190: Add BQ24296 compatible
4639caeeab2f dt-bindings: power: reset: xilinx: Rename node names in examples
c873132667ed dt-bindings: power: reset: qcom-pon: fix inconsistent example
64cf7a912b11 arm64: dts: rockchip: Fix rk3588 USB power-domain clocks
815a2542ad42 arm64: dts: rockchip: configure eth pad driver strength for orangepi r1 plus lts
9df823a6207b arm64: dts: rockchip: Support poweroff on NanoPC-T6
78bd00069022 arm64: dts: rockchip: rk3308-rock-pi-s gpio-line-names cleanup
9d6e0741ae7c arm64: dts: rockchip: Add support for rk3588 based board Cool Pi CM5 EVB
a64a2e009e21 dt-bindings: arm: rockchip: Add Cool Pi CM5
4397d62daec8 arm64: dts: rockchip: Add support for rk3588s based board Cool Pi 4B
f1a9c321e26f dt-bindings: arm: rockchip: Add Cool Pi 4B
1e413c69529f dt-bindings: vendor-prefixes: Add Cool Pi
a67ded35095e arm64: dts: rockchip: add gpio-line-names to rk3328-rock-pi-e
e0ec5767b690 ARM: dts: rockchip: Remove rockchip,default-sample-phase from rk3036.dtsi
75e0afe6681c ARM: dts: rockchip: Add stdout-path for rk3036 kylin
5b38dc06a1e9 dt-bindings: watchdog: qcom,pm8916-wdt: add parent spmi node to example
d2f78877f2ea dt-bindings: watchdog: nxp,pnx4008-wdt: convert txt to yaml
af1fdc5cd02d dt-bindings: watchdog: qca,ar7130-wdt: convert txt to yaml
5c3d9631b9ac dt-bindings: watchdog: intel,keembay: reference common watchdog schema
6d86f883fd9c dt-bindings: watchdog: re-order entries to match coding convention
e28051167c06 dt-bindings: touchscreen: neonode,zforce: Use standard properties
3119a224ac1c dt-bindings: touchscreen: convert neonode,zforce to json-schema
15bf36928144 Merge tag 'icc-6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next
dd37eb39a550 dt-bindings: input: convert drv266x to json-schema
795f4eddfec7 Merge tag 'qcom-arm64-for-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
991ab34b2120 Merge tag 'reset-for-v6.8' of git://git.pengutronix.de/pza/linux into soc/drivers
4e7b4659bc67 dt-bindings: mtd: partitions: u-boot: Fix typo
35dd951a7fd5 Merge tag 'riscv-cache-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers
69b18d58cc6d Merge tag 'riscv-soc-drivers-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers
fc5aa9bf69fd Merge tag 'samsung-drivers-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/drivers
84c9739eb5b5 Merge tag 'qcom-drivers-for-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
0ef14d7a1f46 dt-bindings: crypto: qcom-qce: document the SC7280 crypto engine
2fd8394e6d9f dt-bindings: crypto: qcom-qce: constrain clocks for SM8150-compatible QCE
40fd9d4f3234 dt-bindings: crypto: qcom-qce: constrain clocks for IPQ9574 QCE
30960ac02d6e dt-bindings: rng: starfive: Add jh8100 compatible string
e6272a79f69c Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
dcd8ac1c5dd8 dt-bindings: spi: stm32: add st,stm32mp25-spi compatible
87166d1d3f3f Merge tag 'riscv-dt-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
69abc2365d38 dt-bindings: phy: qcom,sc8280xp-qmp-usb3-uni: Add X1E80100 USB PHY binding
822a13d2bf90 dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Document X1E80100 compatible
6722c7fe2a57 dt-bindings: phy: qcom: snps-eusb2: Document the X1E80100 compatible
a38a399bccf1 dt-bindings: phy: mediatek: tphy: add a property for force-mode switch
ca521e2ecf25 dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: fix path to header
aa156a9707ec Merge tag 'amlogic-arm64-dt-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt
e6127e00f352 Merge tag 'mvebu-dt64-6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt
aad08c0a0671 Merge tag 'mvebu-dt-6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt
e4320c558711 Merge tag 'samsung-dt64-6.8-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
077793e138f6 Merge tag 'qcom-arm32-for-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
7ff5e1692425 Merge tag 'ti-k3-dt-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
f009c98b2a3f dt-bindings: iio: dac: add MCP4821
e46c2c536959 Merge tag 'ti-keystone-dt-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
edeab43af36b Merge tag 'zynqmp-dt-for-6.8' of https://github.com/Xilinx/linux-xlnx into soc/dt
4e78ad68f722 Merge tag 'imx-dt64-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
f4ece4b3d883 Merge tag 'imx-dt-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
1a2b6b1db701 Merge tag 'imx-bindgins-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
71e20fbc3d5b Merge tag 'ux500-dts-soc-for-v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into soc/dt
056c9efa37c5 Merge tag 'renesas-dts-for-v6.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
339491d0999f Merge tag 'stm32-dt-for-v6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt
06086605676a dt-bindings: dma: fsl-edma: Add fsl-edma.h to prevent hardcoding in dts
640904451ab8 dt-bindings: dmaengine: Add Loongson LS2X APB DMA controller
f88d59ec5d12 Merge tag 'sunxi-dt-for-6.8-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
e833ff47f9b9 Merge tag 'at91-dt-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt
9f821c027b01 Merge tag 'juno-update-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/dt
4bab8a451f49 Merge tag 'v6.8-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
a4789dd06449 Merge tag 'v6.8-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
5045526f0b7c Merge tag 'mtk-dts64-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
a7603f8260b8 Merge tag 'samsung-dt-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
16a1d6e0b098 Merge tag 'samsung-dt64-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
0f1f66f39700 ARM: dts: ste: minor whitespace cleanup around '='
22532c5d3f4a Merge tag 'omap-for-v6.8/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into soc/dt
5288e13a2ad4 Merge tag 'hisi-arm64-dt-for-6.8' of https://github.com/hisilicon/linux-hisi into soc/dt
f44f238cabce Merge tag 'w1-drv-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-w1 into char-misc-next
61f41fa45eaf Merge tag 'iio-for-6.8a' of https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-next
07d575b06ff9 dt-bindings: pwm: ti,pwm-omap-dmtimer: Update binding for yaml
fc02de1f5dc0 dt-bindings: riscv: cpus: Add AMD MicroBlaze V compatible
780449a81d3c dt-bindings: pwm: remove Xinlei's mail
f96dd7edb887 arm64: dts: qcom: sc8180x: Fix up PCIe nodes
b1ecf20e17e0 arm64: dts: qcom: sc8180x: Mark PCIe hosts cache-coherent
eeed8f113289 dt-bindings: pinctrl: xilinx: Rename *gpio to *gpio-grp
2ef9211e8711 dt-bindings: pinctrl: qcom: drop common properties and allow wakeup-parent
188c161805d3 dt-bindings: pinctrl: qcom: drop common properties
7834682c0d2c dt-bindings: pinctrl: qcom,ipq5018-tlmm: use common TLMM bindings
c31ea3c9600f dt-bindings: pinctrl: qcom,x1e80100-tlmm: restrict number of interrupts
6cec6f6f090c dt-bindings: pinctrl: qcom,sm8650-tlmm: restrict number of interrupts
ef7b1c134921 dt-bindings: pinctrl: qcom,sm8550-tlmm: restrict number of interrupts
a3abecdd0e2e dt-bindings: pinctrl: qcom,sdx75-tlmm: restrict number of interrupts
2b1d1c0dd621 dt-bindings: pinctrl: qcom,sa8775p-tlmm: restrict number of interrupts
36f8bb953634 dt-bindings: pinctrl: qcom,qdu1000-tlmm: restrict number of interrupts
670ced18d87f dt-bindings: pinctrl: qcom: create common LPASS LPI schema
5ca197c58799 dt-bindings: pinctrl: qcom: Add SM4450 pinctrl
8d27a131f7ad dt-bindings: pinctrl: qcom,pmic-mpp: clean up example
6674c2217ce1 Merge tag 'mediatek-drm-next-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next
d7dde4a72dfa Merge tag 'drm-msm-next-2023-12-15' of https://gitlab.freedesktop.org/drm/msm into drm-next
64ddcb330a18 arm64: dts: qcom: x1e80100-qcp: Fix supplies for some LDOs in PM8550
206ab99c38ce arm64: dts: qcom: sm8550: Update idle state time requirements
319f395fbc2a arm64: dts: qcom: sm8550: Separate out X3 idle state
af2f75b56294 ARM: dts: qcom: sdx55: Fix the base address of PCIe PHY
4a72661b117b arm64: dts: qcom: ipq6018: fix clock rates for GCC_USB0_MOCK_UTMI_CLK
5b72e989a37a arm64: dts: qcom: x1e80100: align mem timer size cells with bindings
b17d7383c10f arm64: dts: qcom: sc7280: Mark SDHCI hosts as cache-coherent
3840ead2163a ARM: dts: qcom: sdx55: fix USB SS wakeup
9e773fad2487 ARM: dts: qcom: sdx55: fix USB DP/DM HS PHY interrupts
d0728def7588 ARM: dts: qcom: sdx55: fix pdc '#interrupt-cells'
0ee9dac79d46 ASoC: qcom: add sound card support for SM8650
345b970f1857 add es8326 dt-bindings, commonize headset codec
85a45459eeed GPIO inclusion fixes to misc sound drivers
616e88e1109d arm64: dts: qcom: sc8180x: fix USB SS wakeup
f3d1b2acf659 arm64: dts: qcom: sdm670: fix USB SS wakeup
987f42804a25 arm64: dts: qcom: sdm670: fix USB DP/DM HS PHY interrupts
2e58236aa851 ASoC: dt-bindings: qcom,lpass-va-macro: remove spurious contains in if statement
bded77d8cc7b dt-bindings: regulator: qcom,usb-vbus-regulator: clean up example
e1481a467961 powerpc/fsl: Fix fsl,tmu-calibration to match the schema
26e2fad496d4 arm64: dts: amlogic: fix format for s4 uart node
8a5115be3855 arm64: dts: amlogic: drop redundant status=okay
799049c22bf2 arm64: dts: amlogic: enable some nodes for board AQ222
3fea93dcdd73 arm64: dts: amlogic: add some device nodes for S4
44721ac7f4da Merge tag 'drm-misc-next-2023-12-14' of git://anongit.freedesktop.org/drm/drm-misc into drm-next
d623bb97a280 Merge tag 'samsung-pinctrl-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel
81d84dd62616 ASoC: dt-bindings: qcom,lpass-rx-macro: Add X1E80100 LPASS WSA
4f673348bd77 ASoC: dt-bindings: qcom,lpass-rx-macro: Add X1E80100 LPASS VA
d5b1bc404268 ASoC: dt-bindings: qcom,lpass-rx-macro: Add X1E80100 LPASS TX
40420db77069 ASoC: dt-bindings: qcom,lpass-rx-macro: Add X1E80100 LPASS RX
605001444f21 ASoC: dt-bindings: qcom,sm8250: Add X1E80100 sound card
4e179f2c3905 ASoC: dt-bindings: mt8188-mt6359: add es8326 support
0c819517fcb2 ASoC: dt-bindings: qcom,sm8250: document SM8650 sound card
0292b51ac8c4 ASoC: tegra: tegra20_ac97: Convert to use GPIO descriptors
4c6bc6503e5e Merge tag 'device_is_big_endian-6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core into gpio/for-next
31d8096d43a1 dt-bindings: gpio: dwapb: allow gpio-ranges
873d4c02bbfa dt-bindings: clock: google,gs101: rename CMU_TOP gate defines
bfc73914844a dt-bindings: clock: si5351: add PLL reset mode property
af0493badd9d dt-bindings: clock: si5351: convert to yaml
d1a5fb288be1 dt-bindings: stm32: add clocks and reset binding for stm32mp25 platform
ee353e29bfb4 dt-bindings: clk: rs9: Add 9FGV0841
48b20705829d dt-bindings: clock: brcm,kona-ccu: convert to YAML
b2b282bb3ba9 dt-bindings: arm: mediatek: move ethsys controller & convert to DT schema
e35ce136c12f dt-bindings: clock: xilinx: add versal compatible
746818ace7a3 dt-bindings: rtc: Add Nuvoton ma35d1 rtc
d8c717fd9bc8 dt-bindings: Remove alt_ref from versal
e9caccbf099c arm64: dts: qcom: sc8180x-primus: Allow UFS regulators load/mode setting
b616df631790 arm64: dts: qcom: sc8180x: Describe the GIC redistributor
ae7e39a80f0f arm64: dts: qcom: sc8180x: Add interconnects to UFS
0f32e7aa54e0 arm64: dts: qcom: sc8180x: Add missing MDP clocks
3641f17d731d arm64: dts: qcom: sc8180x: Add UFS GDSC
2bbb23973697 arm64: dts: qcom: sc7280*: move MPSS and WPSS memory to dtsi
a5b4605b6fc6 ARM: dts: qcom: msm8974*: Re-enable remoteprocs on various boards
f1ecb44efc55 ARM: dts: qcom: msm8974: Remove bogus cd-gpio pinctrl
9dd85d38d004 ARM: dts: qcom: msm8974-klte: Remove unused property
34c2fdcebf94 arm64: dts: qcom: sc7280: Rename reserved-memory nodes
84a50703ca7d dt-bindings: remoteproc: qcom: sc7180-pas: Add SC7280 compatibles
47f83514132e dt-bindings: remoteproc: qcom: sc7180-pas: Fix SC7280 MPSS PD-names
1dce719ef64f arm64: dts: qcom: sc7280: Remove unused second MPSS reg
afedac693f18 arm64: dts: qcom: sdm670: add display subsystem
1d8d2d147ea5 dt-bindings: soc: qcom,aoss-qmp: document the X1E80100 Always-On Subsystem side channel
3ea56a52a7c2 dt-bindings: wdt: Add ts72xx
18522cdf3ec6 dt-bindings: watchdog: dlg,da9062-watchdog: Document DA9063 watchdog
688fe0bdd724 dt-bindings: watchdog: dlg,da9062-watchdog: Add fallback for DA9061 watchdog
9054003bb13e dt-bindings: watchdog: mediatek,mtk-wdt: add MT7988 watchdog and toprgu
63d466a6e3b3 dt-bindings: watchdog: realtek,rtd1295-watchdog: convert txt to yaml
5b6c41392896 dt-bindings: watchdog: qcom-wdt: Make the interrupt example edge triggered
4f8423c375eb dt-bindings: iio: chemical: add aosong,ags02ma
766801c2fc4b dt-bindings: vendor-prefixes: add aosong
530dcc2cff54 arm64: dts: qcom: sm8150-hdk: enable DisplayPort and USB-C altmode
a63d7ac5c9ca arm64: dts: qcom: sm8150: add USB-C ports to the OTG USB host
6177bf5ba3b4 arm64: dts: qcom: sm8150: add USB-C ports to the USB+DP QMP PHY
cccb449ab331 arm64: dts: qcom: sm8150: add DisplayPort controller
414013ad4921 arm64: dts: qcom: sm8150-hdk: fix SS USB regulators
94e5a8422a14 arm64: dts: qcom: sm8150-hdk: enable HDMI output
94cd2b0ff062 arm64: dts: qcom: sm8150: make dispcc cast minimal vote on MMCX
d8577fce5e20 arm64: dts: qcom: sm8650: add fastrpc-compute-cb nodes
e14f9c1044bd arm64: dts: qcom: sm8550-qrd: add PM8010 regulators
66e97e0962a7 arm64: dts: qcom: sm8550-mtp: Add pm8010 regulators
6437200479ec arm64: dts: qcom: qcm2290: Hook up MPM
75b87eb7e3ee arm64: dts: qcom: msm8996: Hook up MPM
e043072a3a33 arm64: dts: qcom: sm6375: Hook up MPM
623a6180066f dt-bindings: arm: qcom: Add Motorola Moto G 4G (2013)
030e5c73208a arm64: dts: qcom: x1e80100-crd: Fix supplies for some LDOs in PM8550
58e87053c1f0 arm64: dts: qcom: sc7280: add QCrypto nodes
6d138c9b4127 arm64: dts: qcom: sc7180: Switch pompom to the generic edp-panel
9248e79cd654 arm64: dts: qcom: sm8150: fix USB SS wakeup
8143f0f67202 arm64: dts: qcom: sm8150: fix USB DP/DM HS PHY interrupts
1d46c82d351b arm64: dts: qcom: sdm845: fix USB SS wakeup
5c261eb8cd11 arm64: dts: qcom: sdm845: fix USB DP/DM HS PHY interrupts
2998fdbc15fe arm64: dts: qcom: sc8180x: fix USB DP/DM HS PHY interrupts
220ee261025f arm64: dts: qcom: sm8550: drop unneeded assigned-clocks from codec macros
ef2823c0a498 arm64: dts: qcom: sm8550: move Soundwire pinctrl to its nodes
611112fa3972 arm64: dts: qcom: sm8450: drop unneeded assigned-clocks from codec macros
7fe6ee08b28c arm64: dts: qcom: sm8450: move Soundwire pinctrl to its nodes
eb6e95625c03 arm64: dts: qcom: sm8550: add missing two RX Soundwire ports in configuration
6f45533e32ad arm64: dts: qcom: sm8650: drop unneeded assigned-clocks from WSA macro
108c60eb7746 dt-bindings: arm: qcom: Fix up htc-memul compatible
c493fe546f0a arm64: dts: qcom: sm6115: Hook up interconnects
fd22f3a58a9e Merge branch 'icc-sm6115' of https://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into HEAD
85a531800a07 ARM: dts: qcom: msm8926-motorola-peregrine: Add initial device tree
9c323b20cda8 ARM: dts: qcom: ipq4019: add dedicated SDHCI compatible
2fcaa70bfc3c arm64: dts: qcom: ipq8074: add dedicated SDHCI compatible
757c981838e3 arm64: dts: qcom: Fix coresight warnings in in-ports and out-ports
34e4f27862d1 arm64: dts: qcom: msm8998: Fix 'out-ports' is a required property
61e7df01e058 arm64: dts: qcom: msm8996: Fix 'in-ports' is a required property
786be94e8465 arm64: dts: qcom: qrb5165-rb5: add the Bluetooth node
fe9d727180d2 arm64: dts: qcom: sa8775p: Add missing space between node name and braces
8df2548eb151 arm64: dts: qcom: Use "pcie" as the node name instead of "pci"
756ec289cf35 ARM: dts: qcom: Use "pcie" as the node name instead of "pci"
2066a55949a7 arm64: dts: qcom: acer-aspire1: Add sound
90485d1f88ce arm64: dts: qcom: acer-aspire1: Correct audio codec definition
3d97796b14f9 arm64: dts: qcom: acer-aspire1: Enable RTC
5d870a6a209b arm64: dts: qcom: sm8450: switch UFS QMP PHY to new style of bindings
1e57f262d57c arm64: dts: qcom: sm8350: switch UFS QMP PHY to new style of bindings
731a9974488a arm64: dts: qcom: sm8250: switch UFS QMP PHY to new style of bindings
8a512baad9fa arm64: dts: qcom: sm8150: switch UFS QMP PHY to new style of bindings
9c4063711b1f arm64: dts: qcom: sm6350: switch UFS QMP PHY to new style of bindings
79c130d88048 arm64: dts: qcom: sm6115: switch UFS QMP PHY to new style of bindings
65d88afa8518 arm64: dts: qcom: sdm845: switch UFS QMP PHY to new style of bindings
fa34450ebcf9 arm64: dts: qcom: msm8998: switch UFS QMP PHY to new style of bindings
2d00768d0566 arm64: dts: qcom: msm8996: switch UFS QMP PHY to new style of bindings
6d501541ab8b arm64: dts: qcom: sm8450-hdk: Enable the A730 GPU
9999a06044c2 arm64: dts: qcom: sm8550-mtp: Enable the A740 GPU
1c8862cd1be0 arm64: dts: qcom: sm8550-qrd: Enable the A740 GPU
db2dd74a4321 arm64: dts: qcom: sm8550: Add GPU nodes
41411e46e180 arm64: dts: qcom: sm8450: Add GPU nodes
67082abed4d1 arm64: dts: qcom: msm8939: Make blsp_dma controlled-remotely
b0768548dacf arm64: dts: qcom: msm8916: Make blsp_dma controlled-remotely
e529c8cd00c4 arm64: dts: qcom: msm8939: Add clock-frequency for broadcast timer
dc95d696633b arm64: dts: qcom: Add missing vio-supply for AW2013
ce476167f046 arm64: dts: qcom: ipq6018: Add QUP5 SPI node
4723cf41be1a arm64: dts: qcom: ipq6018: Add remaining QUP UART node
af3ecf0ef5eb Merge branch '20231201-videocc-8150-v3-1-56bec3a5e443@quicinc.com' into clk-for-6.8
eeb32e2a4dbd dt-bindings: clock: Update the videocc resets for sm8150
c591d3616c87 arm64: dts: qcom: qrb4210-rb2: Enable MPSS and Wi-Fi
479632ff42dd arm64: dts: freescale: fix the schema check errors for fsl,tmu-calibration
4c12613ce6e0 ARM: dts: imx27-phytec-phycore-som: Use 'rtc' as node name
e55cb89e6ef8 ARM: dts: imx25: Remove unneeded keypad properties
610b835be6b9 dt-bindings: net: marvell,orion-mdio: Drop "reg" sizes schema
5605354f949e arm64: dts: freescale: imx8qxp: Disable dsp reserved memory by default
bb83d09752aa arm64: dts: imx8qxp: Add VPU subsystem file
11f5b7454c94 arm64: dts: imx8qxp-mek: Move port under USB connector
f6d6c203902d arm64: dts: imx8mn-bsh-smm-s2/pro: add display setup
643674137f59 dt-bindings: PCI: qcom: Document the SM8650 PCIe Controller
ddec040496f1 dt-bindings: PCI: dwc: rockchip: Document optional PCIe reference clock input
2d8a490fd767 dt-bindings: PCI: qcom: Correct reset-names property
2bdefbbe9381 dt-bindings: PCI: qcom: Correct clocks for SM8150
01ce80af6cc2 dt-bindings: PCI: qcom: Correct clocks for SC8180x
9c60f1faccc9 dt-bindings: PCI: qcom: Adjust iommu-map for different SoC
c78e4dd9c7c0 arm64: dts: rockchip: make use gpio-keys for buttons on puma-haikou
146cf4124863 arm64: dts: rockchip: expose BIOS Disable feedback pin on rk3399-puma
26575df71b2d arm64: dts: rockchip: fix misleading comment in rk3399-puma-haikou.dts
93c2098cfa35 ARM: dts: ux500-href: Switch HREF520 to AB8505
488dc522177c ARM: dts: ux500-href: Push AB8500 config out
7acade644174 ARM: dts: ux500-href: Push AB8500 inclusion to the top
0043c908a991 dt-bindings: connector: usb: add accessory mode description
7b7f80d863a5 arm64: dts: rockchip: Add vop on rk3588
ef9ea9ea51ca arm64: dts: ti: k3-j784s4-main: Add Itap Delay Value For DDR50 speed mode
a843a4a028e7 arm64: dts: ti: k3-j721s2-main: Add Itap Delay Value For DDR50 speed mode
83869275890f arm64: dts: ti: k3-j7200-main: Add Itap Delay Value For DDR52 speed mode
237d1d3aa847 arm64: dts: ti: k3-am6*: Add additional regs for DMA components
6540bf190683 arm64: dts: ti: k3-j7*: Add additional regs for DMA components
f584859d0f96 arm64: dts: ti: k3-am65: Add additional regs for DMA components
e76881a36a46 arm64: dts: cn913x: add device trees for COM Express boards
a57b87e79272 dt-bindings: arm64: add Marvell COM Express boards
22b670935a1f arm64: dts: armada-3720-turris-mox: set irq type for RTC
6b8494ce5492 ARM64: dts: Add special compatibles for the Turris Mox
8fcbbd77bc4f ARM64: dts: marvell: Fix some common switch mistakes
61b4fbe68e70 ARM: dts: marvell: make dts use gpio-fan matrix instead of array
1a025bb583e1 ARM: dts: marvell: Fix some common switch mistakes
283f9ebb847c dt-bindings: serial: Add a new compatible string for UMS9620
42414ddb491a dt-bindings: serial: imx: Properly describe the i.MX1 interrupts
a5b226724ae1 dt-bindings: usb: qcom,dwc3: Add X1E80100 binding
a94c79572ac2 dt-bindings: usb: Document WCD939x USB SubSystem Altmode/Analog Audio Switch
6c2112d5f3f3 arm64: dts: qcom: qrb5165-rb5: use u16 for DP altmode svid
79493bc9fc10 dt-bindings: connector: usb: add altmodes description
a98f9ad936ee dt-bindings: usb: nxp,ptn5110: Fix typos in the title
da44f4e15545 dt-bindings: usb: genesys,gl850g: Document 'peer-hub'
c32fd07e4010 dt-bindings: nvmem: add new stm32mp25 compatible for stm32-romem
cc8835249ffb ARM: dts: stm32: add dcmipp support to stm32mp135
dc483bc0495b dt-bindings: gnss: u-blox: add "reset-gpios" binding
82239f64506f dt-bindings: iommu: rockchip: Add Rockchip RK3588
b10f7d79bc86 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
e39b04bbed6e Merge branch 'icc-qcm2290' into icc-next
c95f389c0366 Merge branch 'icc-sm6115' into icc-next
b1f1b32e611b dt-bindings: PCI: rcar-pci-host: Add optional regulators
51eab76bc15c arm64: dts: allwinner: h618: add Transpeed 8K618-T TV box
8f65017d5eb4 dt-bindings: arm: sunxi: document Transpeed 8K618-T board name
a043657dff28 dt-bindings: vendor-prefixes: add Transpeed
b9b13eec182f arm64: dts: st: add bsec support to stm32mp25
4ba9da13226a ARM: dts: stm32: Consolidate usbh_[eo]hci phy properties on stm32mp15
3cd8f921b287 ARM: dts: stm32: don't mix SCMI and non-SCMI board compatibles
9d7cd7004fbc dt-bindings: arm: stm32: don't mix SCMI and non-SCMI board compatibles
3409584c8b1b ARM: dts: stm32: minor whitespace cleanup around '='
46d3a566ba35 regulator: dt-bindings: qcom,rpmh: add compatible for pm8010
b876feae34ef ASoC: dt-bindings: audio-graph-port: Document new DAI link flags playback-only/capture-only
b0c246496fbc dt-bindings: display: msm: dp: declare compatible string for sm8150
363bcab6054e scsi: ufs: qcom: dt-bindings: Add SC7280 compatible string
3d1e051b5db8 arm64: dts: imx8mp-dhcom-pdk3: Describe the USB-C connector
ef545aff5ca3 arm64: dts: imx8mn-var-som-symphony: Describe the USB-C connector
13069c168986 arm64: dts: imx8mp-tqma8mpql-mba8mpxl: Fix USB connector description
c92840a54a7a arm64: dts: imx8mp-venice: Fix USB connector description
d0235ca7db0f arm64: dts: imx8mp-verdin: Fix USB connector description
8e6a721ca452 arm64: dts: imx8dxl-ss-conn: Move clk_dummy out of USB node
7662ace2b978 arm64: dts: imx8mn-evk: Move port under USB connector
92576b82f349 arm64: dts: imx8mm-evk: Move port under USB connector
91c629656840 arm64: dts: freescale: introduce dimonoff-gateway-evk board
8b75c148251b dt-bindings: arm: fsl: add Dimonoff gateway EVK board
192ca710eafd dt-bindings: vendor-prefixes: add dimonoff
edc62a2939e3 arm64: dts: imx8m*-tqma8m*: Add chassis-type
d35e9fd630d7 arm64: dts: imx8mn-beacon: Support overdrive mode
a684f6ef9a40 arm64: dts: imx8mn: Enable Overdrive mode
0c6ce8fb001d arm64: dts: imx8mm-beacon: Enable overdrive mode
42e3d3eaa3cb arm64: dts: imx8mm: Add optional overdrive DTSI
f9b749293626 arm64: dts: imx8mm: Reduce GPU to nominal speed
aadc35d489bd arm64: dts: imx93: Fix the micfil clock-names entries
f8b732c140f6 ARM: dts: imx23/28: Fix the DMA controller node name
9697ec153a9c ARM: dts: imx23-sansa: Use preferred i2c-gpios properties
62875ee7373e ARM: dts: imx27-apf27dev: Fix LED name
6bd0d6d0fb3d ARM: dts: imx25/27: Pass timing0
3cd4341f361d ARM: dts: imx25: Fix the iim compatible string
52eef6a12e21 arm64: dts: exynos: google: Add initial Oriole/pixel 6 board support
b0f009ddef83 arm64: dts: exynos: google: Add initial Google gs101 SoC support
7932b36aab04 dt-bindings: arm: google: Add bindings for Google ARM platforms
c439b1ecd46b dt-bindings: PCI: ti,j721e-pci-*: Add j784s4-pci-* compatible strings
5114ddf2754e dt-bindings: PCI: ti,j721e-pci-*: Add checks for num-lanes
5142777cc846 arm64: dts: renesas: white-hawk-cpu: Fix missing serial console pin control
9c5b72f0dbf7 arm64: dts: renesas: rzg3s-smarc-som: Enable the Ethernet interfaces
c20cd1060c83 arm64: dts: renesas: rzg3s-smarc-som: Use switches' names to select on-board functionalities
d1702886b9b1 arm64: dts: renesas: r9a08g045: Add Ethernet nodes
c8bc29914258 arm64: dts: renesas: r9a08g045: Add IA55 interrupt controller node
2ac19b878bcd arm64: zynqmp: Add missing destination mailbox compatible
bfda609d3986 arm64: zynqmp: Fix clock node name in kv260 cards
bf79a715a44c arm64: zynqmp: Move fixed clock to / for kv260
067130bf35dd dt-bindings: soc: Add new board description for MicroBlaze V
3909199b5365 dt-bindings: soc: xilinx: Move xilinx.yaml from arm to soc
5a30f0c409d5 arm64: xilinx: Remove address/size-cells from gem nodes
c7afa96873c9 arm64: xilinx: Remove address/size-cells from flash node
e3a99f7f8d11 arm64: xilinx: Put ethernet phys to mdio node
6f4a9a0c8df9 arm64: xilinx: Remove mt25qu512a compatible string from SOM
e3823e6a85e8 arm64: xilinx: Use lower case for partition address
ee878ab978b7 arm64: xilinx: Do not use '_' in DT node names
edb56e5ac871 riscv: dts: starfive: Enable SDIO wifi on JH7100 boards
738fd2fd6271 riscv: dts: starfive: Enable SD-card on JH7100 boards
4a3456d5f756 riscv: dts: starfive: Add JH7100 MMC nodes
0b98a998f256 riscv: dts: starfive: Add pool for coherent DMA memory on JH7100 boards
b7e59570a83e riscv: dts: starfive: Add JH7100 cache controller
0e3644417255 riscv: dts: starfive: Mark the JH7100 as having non-coherent DMAs
2ce3980ca0ba riscv: dts: starfive: Group tuples in interrupt properties
21bb4608c1f4 arm64: dts: ti: k3-am62-main: Add GPU device node
21dbc3bb6085 dt-bindings: interconnect: qcom,msm8998-bwmon: Add QCM2290 bwmon instance
0a5288800340 dt-bindings: rockchip,vop2: Add more endpoint definition
689213783aed dt-bindings: display: vop2: Add rk3588 support
d06f02a431a5 dt-bindings: interconnect: qcom,msm8998-bwmon: Add SM6115 bwmon instance
a67732e07f79 arm64: dts: fsd: Add MFC related DT enteries
a8f325704092 arm64: dts: ti: k3-j721s2-evm: Add overlay for PCIE1 Endpoint Mode
c33d48e723e9 arm64: dts: ti: k3-j721e-evm: Add overlay for PCIE0 Endpoint Mode
411f344456e4 arm64: dts: ti: k3-j721e-sk: Add TPS6594 family PMICs
e88109a7ea70 arm64: dts: ti: k3-am69-sk: Add support for TPS6594 PMIC
8203df16463f arm64: dts: ti: k3-j784s4-evm: Add support for TPS6594 PMIC
12693cd3a151 arm64: dts: ti: k3-j721e-som-p0: Add TP6594 family PMICs
022683d6bab2 arm64: dts: ti: k3-j721s2-som-p0: Add TP6594 family PMICs
b13637076b0a arm64: dts: ti: k3-j7200-som-p0: Add TP6594 family PMICs
073920a8e469 spi: dw: Remove Intel Thunder Bay SOC support
853b38b4ccbe dt-bindings: media: s5p-mfc: Add mfcv12 variant
af1444135df0 dt-bindings: soc: rockchip: add rk3588 vop/vo syscon
ea9d3ade1f63 media: dt-bindings: Add OmniVision OV64A40
eac07152e0b8 media: dt-bindings: media: imx335: Add supply bindings
37535c00a2ec media: dt-bindings: gc0308: add binding
9be8a81b5d55 media: dt-bindings: ov8856: decouple lanes and link frequency from driver
e78a33d58798 media: dt-bindings: alvium: add document YAML binding
123e53dddda5 dt-bindings: vendor-prefixes: Add prefix alliedvision
5367c47d39ee media: dt-bindings: ak7375: Add ak7345 support
33368f1c353f dt-bindings: mfd: pm8008: Clean up example node names
2ab5a6b315e7 dt-bindings: leds: qcom,spmi-flash-led: Fix example node name
fa6a05463677 dt-bindings: leds: aw200xx: Fix led pattern and add reg constraints
44e89edff478 dt-bindings: leds: awinic,aw200xx: Add AW20108 device
6cd025d35790 dt-bindings: leds: aw200xx: Remove property "awinic,display-rows"
65b3a1cec5b9 dt-bindings: leds: aw200xx: Introduce optional enable-gpios property
48e46bb513fb dt-bindings: leds: Add Allwinner A100 LED controller
193b43eae00d dt-bindings: leds: Fix JSON pointer in max-brightness
ac28e493721a ARM: dts: imx25: Move usbphy nodes out of simple-bus
90f8840e451d ARM: dts: imx1: Use 'bus' for AIPI bus
dfc79426f635 ARM: dts: imx27-phytec-phycore-rdk: Move usbphy nodes out of simple-bus
92c19f27621f ARM: dts: imx27-pdk: Move usbphy0 out of simple-bus
09cddc0d2c3d ARM: dts: imx27: Use 'bus' for EMI bus
e7cd1893e9ea ARM: dts: imx27: Use 'bus' for AIPI bus
81e952ba68c6 media: dt-bindings: media: i2c: Add bindings for TW9900
2ed7758d7c0a dt-bindings: vendor-prefixes: Add techwell vendor prefix
9b5febaeea2a arm64: dts: freescale: add fsl-lx2160a-mblx2160a board
c763b70a3ecc dt-bindings: arm: fsl: Add TQ-Systems LX2160A based boards
6c6fc780325f ARM: dts: imx27-phytec-phycore-som: Use the mux- prefix
2571ab1025eb ARM: dts: imx1: Fix sram node
c64c46277345 ARM: dts: imx27: Fix sram node
4606862f29a7 ARM: dts: imx: Use flash@0,0 pattern
e9c196aff7af ARM: dts: imx25/27-eukrea: Fix RTC node name
34087a021485 ARM: dts: imx25-pdk: Pass #sound-dai-cells
f91e9208f059 ARM: dts: imx25: Pass I2C clock-names property
cb93e178f443 arm64: dts: freescale: imx93: add i3c1 and i3c2
3b2d451cf59f arm64: dts: ls1012a: Remove big-endian from thermal
25e47251c772 dt-bindings: input: microchip,cap11xx: add advanced sensitivity settings
a0fb1bc7fd22 Merge tag 'exynos-drm-next-for-v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next
aae3e1a63026 dt-bindings: riscv: add Zfa ISA extension description
ab9eea090f24 dt-bindings: riscv: add Zvfh[min] ISA extension description
7a64028da27c dt-bindings: riscv: add Zihintntl ISA extension description
f4789213e5b6 dt-bindings: riscv: add Zfh[min] ISA extensions description
c5de05064f79 dt-bindings: riscv: add vector crypto ISA extensions description
215c236fe6da dt-bindings: riscv: add scalar crypto ISA extensions description
1a96ef0c118a Merge tag 'pef2256-framer' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
6dbce6382acc Merge tag 'pef2256-framer' into devel
1c566bdd0e0f dt-bindings: net: Add the Lantiq PEF2256 E1/T1/J1 framer
0e2e3f19a42d arm64: dts: rockchip: Add Anbernic RG351V
aa1c981f085f arm64: dts: rockchip: Split RG351M from Odroid Go Advance
5985d0436d7f dt-bindings: arm: rockchip: Add Anbernic RG351V
dddd8bf614e2 arm64: dts: rockchip: Add ethernet0 alias to the dts for RK3588(S) boards
e79626358af1 arm64: dts: rockchip: Add ethernet0 alias to the dts for RK3566 boards
c2bbb4cb37ce arm64: dts: rockchip: Remove ethernet0 alias from the SoC dtsi for PX30
5df2cd229ef2 arm64: dts: rockchip: Remove ethernetX aliases from the SoC dtsi for RK3328
773747ea9224 arm64: dts: rockchip: Remove ethernet0 alias from the SoC dtsi for RK3368
c47780f2190d arm64: dts: rockchip: Remove ethernet0 alias from the SoC dtsi for RK3399
0e5a28940713 arm64: dts: rockchip: make dts use gpio-fan matrix instead of array
51d3d03836a0 arm64: dts: rockchip: add gpio alias for gpio dt nodes
5fcf2d67aa35 arm64: dts: rockchip: Add dynamic-power-coefficient to rk3399 GPU
80e922961b8e arm64: dts: rockchip: add rk3588 spi aliases to soc dtsi
8f3fbd13ee16 arm64: dts: rockchip: add rk3588 gpio aliases to soc dtsi
15b3dffcbe21 arm64: dts: rockchip: add rk3588 i2c aliases to soc dtsi
095c6f3ed2af arm64: dts: rockchip: move rk3588 serial aliases to soc dtsi
5dc789289ead arm64: dts: rockchip: add Theobroma Jaguar SBC
bc75d639d8bd dt-bindings: arm: rockchip: Add Theobroma-Systems Jaguar SBC
3c240c87c027 arm64: dts: rockchip: Add Powkiddy X55
2496d275584a dt-bindings: arm: rockchip: Add Powkiddy X55
517f4adf026d arm64: dts: rockchip: add USB3 host to rock-5a
d474a82f6b8f arm64: dts: rockchip: add USB3 host to rock-5b
4bf4fdf576e0 arm64: dts: rockchip: add missing tx/rx-fifo-depth for rk3328 gmac
56e0ff652ec1 arm64: dts: rockchip: add gpio-line-names to rk3308-rock-pi-s
36bdcd2e79dd ARM: dts: rockchip: add hdmi-connector node to rk3036-kylin
bd117185d559 ARM: dts: rockchip: fix rk3036 hdmi ports node
2127f8eafedb dt-bindings: clock: google,gs101: fix incorrect numbering and DGB suffix
fff73dbf51fc dt-bindings: soc: samsung: usi: add google,gs101-usi compatible
37ffa8542576 dt-bindings: serial: samsung: Make samsung,uart-fifosize a required property
fd8ed4626aeb dt-bindings: serial: samsung: Add google-gs101-uart compatible
33bfe5e1dc68 dt-bindings: watchdog: Document Google gs101 watchdog bindings
e6381c01b68b riscv: dts: thead: Enable LicheePi 4A eMMC and microSD
3bd0505c030a riscv: dts: thead: Enable BeagleV Ahead eMMC and microSD
a53de85228bf riscv: dts: thead: Add TH1520 mmc controllers and sdhci clock
fd1214b13ed4 ARM: dts: microchip: sama5d27_som1_ek: Remove mmc-ddr-3_3v property from sdmmc0 node
5d2956b92dea dt-bindings: interrupt-controller: mpm: Pass MSG RAM slice through phandle
402b4259739c dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S
150ddb24b2f0 Merge tag 'coresight-next-v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux into char-misc-next
64011b700499 dt-bindings: arm-smmu: Document SM8[45]50 GPU SMMU
a5ab14d25e79 dt-bindings: arm-smmu: Add compatible for X1E80100 SoC
aaa9819e17c5 dt-bindings: iommu: arm,smmu: document the SM8650 System MMU
c04ccbbeb58a dt-bindings: iommu: arm,smmu: document clocks for the SM8350 GPU SMMU
b73f681e020f arm64: dts: juno: Align thermal zone names with bindings
8762e182cc34 dt-bindings: hwmon: Add lltc ltc4286 driver bindings
7711cd743748 Merge tag 'exynos-drm-next-for-v6.7-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into exynos-drm-next
0c9c816dddb4 Backmerge tag 'v6.7-rc5' into drm-next
cc330eac5dd3 dt-bindings: iio: humidity: Add TI HDC302x support
07a88600291a dt-bindings: iio: light: add ltr390
a803f8c65ec8 dt-bindings: iio: pressure: add honeywell,hsc030
49600f0eeb26 dt-bindings: iio: temperature: add MLX90635 device
5f69a9e8d3dd dt-bindings: hwmon: Increase max number of io-channels
565f404ae838 dt-bindings: hwmon: Add mps mp5990 driver bindings
ad5cba1ee29a ASoC: dt-bindings: qcom,lpass-wsa-macro: Add SM8650 LPASS WSA
880126e66fb3 ASoC: dt-bindings: qcom,lpass-va-macro: Add SM8650 LPASS VA
19ed8a218bd9 ASoC: dt-bindings: qcom,lpass-tx-macro: Add SM8650 LPASS TX
322423704418 ASoC: dt-bindings: qcom,lpass-rx-macro: Add SM8650 LPASS RX
f09397ff6cbf dt-bindings: dma: Add dma-channel-mask to nvidia,tegra210-adma
6263d2ffbb0f dt-bindings: dma: sf-pdma: add new compatible name
7581e8bd108d arm64: dts: mediatek: mt8192: Add Smart Voltage Scaling node
de53c9a33f27 arm64: dts: mediatek: mt8195: Add SVS node and reduce LVTS_AP iospace
53ceb33cc2de arm64: dts: mediatek: mt8183: Change iospaces for thermal and svs
d305525393a4 arm64: dts: mediatek: mt8186: fix address warning for ADSP mailboxes
d4dbd2b56a9f arm64: dts: mediatek: mt8186: Fix alias prefix for ovl_2l0
209e23166717 arm64: dts: mt6358: Drop bogus "regulator-fixed" compatible properties
b5aaf3dc3cc4 arm64: dts: mt8183: kukui-jacuzzi: Drop bogus anx7625 panel_flag property
aef30bad7a04 arm64: dts: Add MediaTek MT8188 dts and evaluation board and Makefile
c8d764a0bbc6 dt-bindings: soc: mediatek: pwrap: Modify compatible for MT8188
1b35e3cf8066 dt-bindings: arm: mediatek: Add mt8188 pericfg compatible
7e4914880550 dt-bindings: arm: Add compatible for MediaTek MT8188
c4c85ca7297e arm64: dts: mediatek: mt8195: add DSI and MIPI DPHY nodes
e7300ae6b913 dt-bindings: display: mediatek: dsi: add compatible for MediaTek MT8195
cebba0dd1a01 arm64: dts: mediatek: mt6358: Merge ldo_vcn33_* regulators
8ac8be12ac45 dt-bindings: arm: mediatek: convert audsys and mt2701-afe-pcm to yaml
275042f3fe7b arm64: dts: mediatek: mt8195: add MDP3 nodes
aba1f17e7acc arm64: dts: mediatek: mt8195: revise VDOSYS RDMA node name
7032d5f144c2 arm64: dts: mediatek: mt8183: correct MDP3 DMA-related nodes
22bae315e031 dt-bindings: display: mediatek: padding: add compatible for MT8195
751c1a1076cb dt-bindings: display: mediatek: split: add compatible for MT8195
e2f195c9941b dt-bindings: display: mediatek: ovl: add compatible for MT8195
98aa994aefee dt-bindings: display: mediatek: merge: add compatible for MT8195
6f5d6cbaa3f9 dt-bindings: display: mediatek: color: add compatible for MT8195
ef86984ae659 dt-bindings: display: mediatek: aal: add compatible for MT8195
8f6efe19695a dt-bindings: media: mediatek: mdp3: add component TDSHP for MT8195
f3a2d9b01651 dt-bindings: media: mediatek: mdp3: add component TCC for MT8195
9952a02bb5ee dt-bindings: media: mediatek: mdp3: add component STITCH for MT8195
6c49acbc4134 dt-bindings: media: mediatek: mdp3: add component HDR for MT8195
d6fdbfb3b4ad dt-bindings: media: mediatek: mdp3: add component FG for MT8195
a7d6e829425b dt-bindings: media: mediatek: mdp3: add compatible for MT8195 WROT
7db0370c2d66 dt-bindings: media: mediatek: mdp3: add compatible for MT8195 RSZ
5620ceb8b6ca dt-bindings: media: mediatek: mdp3: add config for MT8195 RDMA
8f056e0ef45c dt-bindings: media: mediatek: mdp3: merge the indentical RDMA under display
c2d8940ef6fd dt-bindings: media: mediatek: mdp3: correct RDMA and WROT node with generic names
4347ab16a815 media: dt-bindings: mediatek: Add phandle to mediatek,scp on MDP3 RDMA
e14664bd10f6 arm64: dts: mediatek: mt8195-cherry: Assign sram supply to MFG1 pd
0561502a0693 arm64: dts: mediatek: mt8195-cherry: Add MFG0 domain supply
08b52bb4b076 dt-bindings: reset: mt8188: Add VDOSYS reset control bits
10fbcb9df4e2 dt-bindings: arm: mediatek: Add compatible for MT8188
88c996595db3 dt-bindings: display: mediatek: padding: Add MT8188
ca5643fef42b dt-bindings: display: mediatek: merge: Add compatible for MT8188
ae3b78a94c61 dt-bindings: display: mediatek: mdp-rdma: Add compatible for MT8188
744464b66c7e dt-bindings: display: mediatek: ethdr: Add compatible for MT8188
01b1569a2d88 dt-bindings: thermal: convert Mediatek Thermal to the json-schema
90d08ec14e3c arm64: dts: mt8183: Add jacuzzi pico/pico6 board
5df3f176b5bf dt-bindings: arm64: mediatek: Add mt8183-kukui-jacuzzi-pico
281ab3bf124c arm64: dts: mt8183: Add jacuzzi makomo board
52cfc0fd5dd9 dt-bindings: arm64: mediatek: Add mt8183-kukui-jacuzzi-makomo
19dd875d8e0a arm64: dts: mt8183: Add kukui katsu board
b8dd2f8c3e1c dt-bindings: arm64: mediatek: Add mt8183-kukui-katsu
9a6a916f0bc6 arm64: dts: mediatek: Move MT6358 PMIC interrupts to MT8183 boards
3f27ea46dc3d arm64: dts: mediatek: Use interrupts-extended where possible
ad0c69fd2fa3 arm64: dts: mediatek: mt8173: Use interrupts-extended where possible
c82e8139aeaa arm64: dts: mediatek: mt8183: Use interrupts-extended where possible
d8a485fe96f7 dt-bindings: soc: mediatek: add mt8186 and mt8195 svs dt-bindings
e66d619c0c3a dt-bindings: arm: mediatek: mmsys: Add VPPSYS compatible for MT8188
5e6b938fc74f arm64: dts: mediatek: mt8192: Add thermal nodes and thermal zones
e90ef555e054 arm64: dts: mediatek: mt8183: Add decoder
0f0ccec6cc8d arm64: dts: mediatek: mt8173: Drop VDEC_SYS reg from decoder
b6aed11d9548 arm64: dts: mediatek: cherry: Add platform thermal configuration
86760b83d52b dt-bindings: display: simple: Add AUO G156HAN04.0 LVDS display
a9ddc30ef584 dt-bindings: display: panel: Add Ilitek ili9805 panel controller
defac25462fb dt-bindings: display: st7701: Add Anbernic RG-ARC panel
336bc0e68db2 dt-bindings: display: panel: add Fascontek FS035VG158 panel
955ce81826fb dt-bindings: vendor-prefixes: Add fascontek
752a79b7aaef dt-bindings: display: panel: Clean up leadtek,ltk035c5444t properties
770aea203c16 Merge 6.7-rc5 into tty-next
34ef5edc5b88 Merge 6.7-rc5 into usb-next
621073890e71 Merge branch 'for-v6.8/samsung-bindings-compatibles' into next/dt64
bf94b2d5359e arm64: dts: exynos: add minimal support for exynosautov920 sadk board
e9fd8cf1d2d8 arm64: dts: exynos: add initial support for exynosautov920 SoC
d0863d30608a dt-bindings: pinctrl: samsung: correct ExynosAutov920 wake-up compatibles
9bdf0db8ae4b dt-bindings: samsung: exynos-sysreg: combine exynosautov920 with other enum
5b54324e6d5b dt-bindings: dma: Drop undocumented examples
e2fd1a08fd82 Merge remote-tracking branch 'drm-misc/drm-misc-next' into msm-next
a04c2351b389 dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to GS101
9b3c118b3d19 dt-bindings: clock: Add Google gs101 clock management unit bindings
d97b5e938286 dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible
6a5a439c0701 dt-bindings: pinctrl: samsung: add gs101-wakeup-eint compatible
10422d721886 dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible
3a5cb767f670 media: dt-bindings: media: rkisp1: Fix the port description for the parallel interface
1da803cb7af8 arm64: dts: qcom: qcm6490-fairphone-fp5: Enable WiFi
8da528961e4e arm64: dts: qcom: qcm6490-fairphone-fp5: Enable various remoteprocs
e6fa65e6d152 arm64: dts: qcom: sc7280: Add CDSP node
fc9753f721c5 arm64: dts: qcom: sc7280: Add ADSP node
c8ee1d58df76 arm64: dts: qcom: sc7280: Use WPSS PAS instead of PIL
52f7c413fda4 arm64: dts: qcom: qcm6490-fairphone-fp5: Enable UFS
4df3a7b5d504 arm64: dts: qcom: msm8953: Set initial address for memory
423afe7e3dcb ARM: dts: qcom: msm8226: Add GPU
bba409f9c339 ARM: dts: qcom: Disable pm8941 & pm8226 smbb charger by default
7e9db953a623 arm64: dts: qcom: sc7280: Add UFS nodes for sc7280 IDP board
4e3613f89c7f arm64: dts: qcom: sc7280: Add UFS nodes for sc7280 soc
d8bfc2581200 dt-bindings: input: gpio-mouse: Convert to json-schema
2691fb7a0b13 dt-bindings: drm: rockchip: convert inno_hdmi-rockchip.txt to yaml
2dc455b73efa ARM: dts: samsung: exynos4210-i9100: Add accelerometer node
0fab2792a476 ARM: dts: samsung: exynos4210-i9100: Add node for touch keys
7ea4a30a8fd6 ARM: dts: samsung: exynos4210-i9100: Unconditionally enable LDO12
4cee9945012b ARM: dts: microchip: sama5d27_wlsom1_ek: Remove mmc-ddr-3_3v property from sdmmc0 node
e76f84dfaedb arm64: dts: qcom: sm8650: Add DisplayPort device nodes
2cfe9148e611 arm64: dts: qcom: pm8550: drop PWM address/size cells
49e3d2a63a49 dt-bindings: display: mediatek: padding: Add MT8188
8c1a5538e89b dt-bindings: display: mediatek: merge: Add compatible for MT8188
29025812d6c3 dt-bindings: cache: qcom,llcc: correct QDU1000 reg entries
3e60d5b58b7d dt-bindings: gpu: samsung-scaler: constrain iommus and power-domains
1d6aee346b02 dt-bindings: gpu: samsung-g2d: constrain iommus and power-domains
d4a84a84e922 dt-bindings: gpu: samsung: constrain clocks in top-level properties
1e0b14dc8237 dt-bindings: gpu: samsung: re-order entries to match coding convention
ba50ff463c59 dt-bindings: gpu: samsung-rotator: drop redundant quotes
1a3c1bf5b141 dt-bindings: display: mediatek: mdp-rdma: Add compatible for MT8188
0a16c7e2c414 dt-bindings: display: mediatek: ethdr: Add compatible for MT8188
925f69a6cc7d dt-bindings: serial: qcom,msm-uartdm: Vote for shared resources
44f4478aa927 dt-bindings: serial: snps-dw-apb-uart: include rs485 schema
fad4b52a0fdb arm64: dts: hisilicon: hikey970-pmic: clean up SPMI node
051c12eb5d46 arm64: dts: hisilicon: hikey970-pmic: fix regulator cells properties
e567127bd619 dt-bindings: hisilicon: Merge hi3620-clock into hisilicon,sysctrl binding
4b823f7042ef arm64: dts: qcom: x1e80100: Add Compute Reference Device
f51679f0f817 arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts
ca121fc146b2 dt-bindings: arm: qcom: Document X1E80100 SoC and boards
c53c3b8c12a4 dt-bindings: arm: cpus: Add qcom,oryon compatible
aa432318faa9 Merge branch 'icc-x1e80100' of https://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into arm64-for-6.8
9eba2f2fb214 Merge branch '20231205061002.30759-4-quic_sibis@quicinc.com' into arm64-for-6.8
f213e67c84b7 Merge branch '20231205061002.30759-4-quic_sibis@quicinc.com' into clk-for-6.8
ecc521e21905 dt-bindings: clock: qcom-rpmhcc: Add RPMHCC bindings for X1E80100
079af735ef3c dt-bindings: clock: qcom: Add X1E80100 GCC clocks
8f4495322f78 arm64: dts: qcom: sm8650-mtp: add WSA8845 speakers
02b73ff63440 arm64: dts: qcom: sm8650: add Soundwire controllers
e6679602ac09 arm64: dts: qcom: sm8650: add ADSP audio codec macros
5c0a5d9640c3 arm64: dts: qcom: sm8650: add LPASS LPI pin controller
7f6211cc8e63 arm64: dts: qcom: sm8650: add ADSP GPR
b72a9e98977b arm64: dts: qcom: sm8650-qrd: enable IPA
13bdc41575ab arm64: dts: qcom: sm8650: add IPA information
0fd767d395a1 arm64: dts: qcom: sm8650-qrd: add interconnect dependent device nodes
d68c8f7f237a arm64: dts: qcom: sm8650-mtp: add interconnect dependent device nodes
900a28b939d2 arm64: dts: qcom: sm8650: add interconnect dependent device nodes
ff01973261d0 arm64: dts: qcom: sm8650: add initial SM8650 QRD dts
185ce15a620b arm64: dts: qcom: sm8650: add initial SM8650 MTP dts
487b5dde17e2 arm64: dts: qcom: pm8550ve: make PMK8550VE SID configurable
61ff00c8e1de arm64: dts: qcom: add initial SM8650 dtsi
7266e49a2f3e dt-bindings: arm: qcom: document SM8650 and the reference boards
34a104c65fa9 Merge branch 'icc-sm8650' of https://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into arm64-for-6.8
dc9c79dc36cc Merge branch '20231106-topic-sm8650-upstream-clocks-v3-5-761a6fadb4c0@linaro.org' into arm64-for-6.8
482bf7559678 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
89cdcbe73e3a dt-bindings: display: msm: dp-controller: document SM8650 compatible
6457d6362b66 docs: dt-bindings: add DTS Coding Style document
17bd76b0dcba ARM: dts: rockchip: add gpio alias for gpio dt nodes
1e3bf6cdb555 dt-bindings: mfd: hisilicon,hi6421-spmi-pmic: Clean up example
ebf62e0e08ff dt-bindings: mfd: hisilicon,hi6421-spmi-pmic: Fix regulator binding
ff778a37f71a dt-bindings: mfd: hisilicon,hi6421-spmi-pmic: Fix up binding reference
60bfc8c9aef9 dt-bindings: firmware: qcom,scm: Allow interconnect for everyone
ae3daad140cd arm64: dts: qcom: sm8250-xiaomi-pipa: Add initial device tree
3ab4a6461f9d dt-bindings: arm: qcom: Add Xiaomi Pad 6 (xiaomi-pipa)
a4229e4b1bf7 arm64: dts: qcom: sm8550-qrd: enable IPA
0b02bd1a7f8b arm64: dts: qcom: sm8550: add IPA information
1d704f347212 dt-bindings: firmware: qcom,scm: document SCM on X1E80100 SoCs
a07e2c07074c dt-bindings: arm: qcom-soc: extend pattern matching for X1E80100 SoC
190053cb1ce8 arm64: dts: qcom: minor whitespace cleanup around '='
e5d9eb69d255 ARM: dts: qcom: minor whitespace cleanup around '='
a12829c0d5ea arm64: dts: qcom: ipq8074: Add QUP4 SPI node
81c5f29af493 arm64: dts: qcom: qdu1000: Add ECPRI clock controller
7f8d2a160503 Merge branch '20231123064735.2979802-2-quic_imrashai@quicinc.com' into clk-for-6.8
a7b1e49f140b dt-bindings: clock: qcom: Add ECPRICC clocks for QDU1000 and QRU1000
0d8365b85a68 ARM: dts: qcom: sdx55: fix USB wakeup interrupt types
4e5dc5d2a1e5 arm64: dts: qcom: sm8550: fix USB wakeup interrupt types
b0dd9226dd63 arm64: dts: qcom: sm8150: fix USB wakeup interrupt types
301d240b276b arm64: dts: qcom: sm6375: fix USB wakeup interrupt types
bcfa8e3ed274 arm64: dts: qcom: sdm845: fix USB wakeup interrupt types
20a6fe5d28b2 arm64: dts: qcom: sdm670: fix USB wakeup interrupt types
d2c7cfd6cfc3 arm64: dts: qcom: sc8180x: fix USB wakeup interrupt types
6f29d799b7cf arm64: dts: qcom: sc7280: fix usb_2 wakeup interrupt types
ca84d4480b44 arm64: dts: qcom: sc7280: fix usb_1 wakeup interrupt types
096085135fda arm64: dts: qcom: sc7180: fix USB wakeup interrupt types
6c1f003cc9a1 arm64: dts: qcom: sa8775p: fix USB wakeup interrupt types
45bd09d633c8 arm64: dts: qcom: msm8916-longcheer-l8150: Add battery and charger
195857e6f299 arm64: dts: qcom: pm8916: Add BMS and charger
6caacf1f1bd3 arm64: dts: qcom: sc7280: Add 0xac Adreno speed bin
3ddcb3a31e24 arm64: dts: qcom: sc7280: Mark Adreno SMMU as DMA coherent
b8bf84b9efc0 arm64: dts: qcom: sc7280: Fix up GPU SIDs
0830942e59a4 arm64: dts: qcom: sc7280: Add ZAP shader support
6a2b85d201c9 dt-bindings: arm: qcom-soc: extend pattern for matching existing SoCs
ddd782c9e1e9 dt-bindings: cache: qcom,llcc: Add X1E80100 compatible
573141bcc2f7 arm64: dts: qcom: sdx75-idp: Enable USB3 and PHY support
93789523f679 arm64: dts: qcom: Add USB3 and PHY support on SDX75
ddc8552a97e0 arm64: dts: qcom: Add interconnect nodes for SDX75
2f6480d75792 arm64: dts: qcom: sm8350: Fix remoteproc interrupt type
22ab1e4b96e5 arm64: dts: qcom: pm8350k: Remove hanging whitespace
648dd7cb906d arm64: dts: qcom: sm8350: Fix DMA0 address
aa5e755d7246 dt-bindings: iio: adc: qcom: Add Qualcomm smb139x
aee24a669374 arm64: dts: qcom: sc8180x: align APSS with bindings
c51b52a3c7aa arm64: dts: qcom: sm6375-pdx225: add fixed touchscreen AVDD regulator
714c2d01cb79 arm64: dts: qcom: sm6125: add interrupts to DWC3 USB controller
869ed2bf0b06 arm64: dts: qcom: sm6115: align mem timer size cells with bindings
5b01a3bc4e38 arm64: dts: qcom: sm8150: use 'gpios' suffix for PCI GPIOs
abcbd3630645 arm64: dts: qcom: sc8180x-primus: use 'gpios' suffix for PCI GPIOs
5281b1e2c756 arm64: dts: qcom: sc8180x-flex-5g: use 'gpios' suffix for PCI GPIOs
dbf927ecfde3 arm64: dts: qcom: sdm845: correct Soundwire node name
27d49e38f5d4 arm64: dts: qcom: sdm845-db845c: correct LED panic indicator
85591f38ba27 arm64: dts: qcom: qrb5165-rb5: correct LED panic indicator
65b61add6d70 arm64: dts: qcom: sm8250: Add wakeup-source to usb_1 and usb_2
343c9084fd53 arm64: dts: qcom: sdm850-lenovo-yoga: Add wakeup-sources
eb9d72ac20a4 arm64: dts: qcom: sa8775p-ride: enable pmm8654au_0_pon_resin
e4828a6315b4 arm64: dts: qcom: sm8350: move DPU opp-table to its node
cfa2fb4b7f5b arm64: dts: qcom: sc8280xp-x13s: drop sound-dai-cells from eDisplayPort
927e9926b48f arm64: dts: qcom: sc8180x-primus: drop sound-dai-cells from eDisplayPort
ca8a02834a8f arm64: dts: qcom: sm8250: correct Soundwire node name
682a341c0cdc arm64: dts: qcom: sc8280xp: correct Soundwire node name
13f2dbc0a9cb arm64: dts: qcom: qdu1000-idp: drop unused LLCC multi-ch-bit-off
6cda67d14000 arm64: dts: qcom: qdu1000: correct LLCC reg entries
208a56e344a2 arm64: dts: qcom: sm8450: fix soundwire controllers node name
c7bee631d3e9 arm64: dts: qcom: sm8550: fix soundwire controllers node name
255ca7c95406 Merge branch '20231106-topic-sm8650-upstream-clocks-v3-5-761a6fadb4c0@linaro.org' into clk-for-6.8
52721c372031 dt-bindings: clock: qcom: Document the SM8650 RPMH Clock Controller
a8430c36d8bc dt-bindings: clock: qcom: document the SM8650 GPU Clock Controller
e39f08bf115a dt-bindings: clock: qcom: document the SM8650 Display Clock Controller
076aa9fc05f3 dt-bindings: clock: qcom: document the SM8650 General Clock Controller
abeff2c9f476 dt-bindings: clock: qcom: document the SM8650 TCSR Clock Controller
3714369ceebb dt-bindings: cache: qcom,llcc: Document the SM8650 Last Level Cache Controller
cb0f1e272d52 dt-bindings: clock: qcom,gcc-msm8939: Add CSI2 related clocks
7ee4127b7a3f arm64: dts: qcom: sc8280xp: Add in CAMCC for sc8280xp
d380ef670205 Merge branch '20231026105345.3376-3-bryan.odonoghue@linaro.org' into arm64-for-6.8
30a292de3f9a Merge branch '20231026105345.3376-3-bryan.odonoghue@linaro.org' into clk-for-6.8
f007e023cbd5 dt-bindings: clock: Add SC8280XP CAMCC
aec8967c6dce dt-bindings: clock: Use gcc.yaml for common clock properties
7c1eb93bd0d3 dt-bindings: clock: qcom,gcc-ipq6018: split to separate schema
b6364ec8f82d dt-bindings: arm: qcom,ids: Add SoC ID for SM8650
3f482ad7991e arm64: dts: qcom: sm8550: Enable download mode register write
fe077e894545 arm64: dts: qcom: sm8350: Add TCSR halt register space
956699ec82d4 arm64: dts: qcom: sm8250: Add TCSR halt register space
e0bd046de230 arm64: dts: qcom: ipq5018: add few more reserved memory regions
c38c43d3b995 arm64: dts: qcom: ipq5332: add missing properties to the GPIO LED node
0390c1ee5e11 arm64: dts: qcom: ipq9574: enable GPIO based LED
2f9b91c0cf6d arm64: dts: qcom: qrb2210-rb1: use USB host mode
2196010939c0 dt-bindings: firmware: qcom,scm: document SM8650 SCM Firmware Interface
ae8a176c474a dt-bindings: soc: qcom: pmic-glink: document SM8650 compatible
c3cb68af1e5d dt-bindings: soc: qcom,aoss-qmp: document the SM8560 Always-On Subsystem side channel
a6ea4114f911 dt-bindings: mmc: mtk-sd: add tuning steps related property
30e4bc60ac6d dt-bindings: mfd: ti,am3359-tscadc: Allow dmas property to be optional
5c51588d48df dt-bindings: mfd: qcom,spmi-pmic: Add pm8916 vm-bms and lbc
a03962f53dbd dt-bindings: mfd: qcom-spmi-pmic: Document PM8937 PMIC
81a2c830f173 dt-bindings: mfd: qcom,tcsr: Add compatible for sm8250/sm8350
fe50e0fb05fc dt-bindings: mfd: ams,as3711: Convert to json-schema
197c27b6cfaa arm64: dts: fsd: add specific compatibles for Tesla FSD
395fa67b6b72 Merge branch 'for-v6.8/samsung-bindings-compatibles' into next/dt64
5927c83d20c8 dt-bindings: watchdog: samsung: add specific compatible for Tesla FSD
78e4ed4670d7 dt-bindings: samsung: exynos-pmu: add specific compatible for Tesla FSD
c168df69f5a1 dt-bindings: serial: samsung: add specific compatible for Tesla FSD
6dedf66f0e8b dt-bindings: pwm: samsung: add specific compatible for Tesla FSD
457e5d03f14d dt-bindings: i2c: exynos5: add specific compatible for Tesla FSD
4b7a14529669 dt-bindings: mmc: renesas,sdhi: Document RZ/Five SoC
a135e0045af7 dt-bindings: mmc: arasan,sdci: Add gate property for Xilinx platforms
d0ed6c92c98e dt-bindings: mmc: sdhci-of-dwcmhsc: Add T-Head TH1520 support
f7a9df14027b dt-bindings: net: microchip,ksz: document microchip,rmii-clk-internal
b81aa4a5992d media: dt-bindings: mediatek: Add phandle to mediatek,scp on MDP3 RDMA
b80f939c4051 dt-bindings: iio/adc: qcom,spmi-vadc: clean up examples
44c4f2c40551 dt-bindings: iio/adc: qcom,spmi-vadc: fix example node names
c57fab0a68f9 dt-bindings: iio/adc: qcom,spmi-rradc: clean up example
f330b6a06a10 dt-bindings: iio/adc: qcom,spmi-iadc: clean up example
d089bb38e3f6 dt-bindings: iio/adc: qcom,spmi-iadc: fix example node name
d92310a0b805 dt-bindings: iio/adc: qcom,spmi-iadc: fix reg description
6afb70912c0a Merge tag 'renesas-dts-for-v6.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
77be7b2ec3d6 arm64: dts: ti: Add verdin am62 mallow board
5fe3785a98a1 dt-bindings: arm: ti: Add verdin am62 mallow board
7bf01a4e3239 ASoC: dt-bindings: fsl,xcvr: Adjust the number of interrupts
568ee5fdf77d dt-bindings: interconnect: Add Qualcomm SM6115 NoC
7549b7adec53 arm64: dts: ti: verdin-am62: Improve spi1 chip-select pinctrl
0b160138fdcc arm64: dts: ti: k3-am625-phyboard-lyra-rdk: Remove HDMI Reset Line Name
42aed107725d arm64: dts: ti: k3-am625-phyboard-lyra-rdk: Add HDMI support
766ac2241c85 arm64: dts: ti: k3-am625-phyboard-lyra-rdk: Lower I2C1 frequency
bcf7dd5b8b09 arm64: dts: ti: phycore-am64: Add R5F DMA Region and Mailboxes
e1dfb1eb87a4 riscv: dts: microchip: add the mpfs' system controller qspi & associated flash
59d2f723c14b dt-bindings: soc: microchip: add a property for system controller flash
4b452a4cfa9e ARM: dts: imx23/28: Remove undocumented "fsl,clkctrl"
485e1601cd25 ARM: dts: bcm2711: Add BCM2711 xHCI support
439353e944b0 dt-bindings: usb: xhci: Add support for BCM2711
4b95e8b40522 ARM: dts: imx28-lwe: Pass device_type to the memory node
ea0431aa1757 ARM: dts: imx23/28: Remove unneeded "fsl,mxs-gpio"
e63738dd96c8 ARM: dts: imx28-tx28: Pass #sound-dai-cells
fc88878c01c0 arm64: dts: imx8mq-phanbell: make dts use gpio-fan matrix instead of array
e21fe3809cd3 arm64: dts: freescale: verdin-imx8mp: add support to mallow board
a75cfdc4a966 arm64: dts: freescale: verdin-imx8mm: add support to mallow board
3b7bee60295f arm64: dts: imx8mm-venice-gw7: Adjust PCI Ethernet nodes
5241ecb06203 dt-bindings: arm: fsl: add verdin imx8mp mallow board
b80ecc880136 dt-bindings: arm: fsl: add verdin imx8mm mallow board
ad1ae2498610 arm64: dts: imx8mm: Slow default video_pll1 clock rate
5aa830cec5a3 arm64: dts: imx8mm: Remove video_pll1 clock rate from clk node
110274d03548 arm64: dts: imx8mm: Simplify mipi_dsi clocks
99d898689e0b ARM: dts: imx7s: Add on-chip memory
29d17af3b09b ARM: dts: imx7: add MIPI-DSI support
d9c25edf04ae scsi: ufs: dt-bindings: Add msi-parent for UFS MCQ
dba1025f17d0 ARM: dts: nxp: Fix some common switch mistakes
4ea7b578957d arm64: dts: freescale: minor whitespace cleanup around '='
dbb52d93894b arm64: dts: imx8dxl-ss-ddr: change ddr_pmu0 compatible
941d70d2ae55 arm64: dts: tqma8mpql: Remove invalid/unused property
ec00a410133c arm64: dts: imx8-ss-audio: Remove unexistent'shared-interrupt'
604139ed79f6 arm64: dts: imx93: Remove unexistent 'shared-interrupt'
7a445842e287 arm64: dts: imx8qxp-mek: Fix gpio-sbu-mux compatible
0c2122b767be arm64: dts: imx8mp-debix-model-a: Use phy-mode
2e9827c5e054 arm64: dts: imx8mm-nitrogen-r2: Fix I2C mux subnode name
d1e22a0dfb43 arm64: dts: imx8dxl-ss-conn: Fix Ethernet interrupt-names order
6299d7ae35e5 arm64: dts: imx8mm-emcon-avari: Fix gpio-cells
9de3f32f3c7d arm64: dts: imx8qm-ss-dma: Pass lpuart dma-names
6905c613057b arm64: dts: freescale: Add SKOV IMX8MP CPU revB board
b20a05f3b464 arm64: dts: imx8mn-var-som-symphony: add vcc supply for PCA9534
a5a6af3c0bdd arm64: dts: freescale: introduce rve-gateway board
83600000758e arm64: dts: freescale: debix-som-a-bmb-08: Add CSI Power Regulators
b5e632bcd082 arm64: dts: imx8-apalis: add can power-up delay on ixora board
9804057f0f96 arm64: dts: imx8mn-var-som: add fixed 3.3V regulator for EEPROM
e3c93255cfdb arm64: dts: imx8mm-venice-gw7: Fix pci sub-nodes
8357f0b7ae64 arm64: dts: imx8mp: Disable dsp reserved memory by default
3b2b78d127df arm64: dts: imx8mp: Add NPU Node
b13969aeeefc arm64: dts: freescale: debix-som: Add heartbeat LED
5c6068a3aecc arm64: dts: freescale: Add dual-channel LVDS overlay for TQMa8MPxL
37dbfb74c066 arm64: dts: imx8mp-venice-gw74xx: remove unecessary propreties in tpm node
12f50b18b3a5 ARM: dts: nxp: minor whitespace cleanup around '='
7e4a296e0073 ARM: dts: imx7d-colibri-emmc: Add usdhc aliases
aac483d2d190 ARM: dts: imx6qdl-colibri: Add usdhc aliases
534d21c04c41 ARM: dts: imx6qdl-apalis: Add usdhc aliases
4105f51d0c63 ARM: dts: nxp: imx7d-pico: add cpu-supply nodes
4a5f36c1120b dt-bindings: arm: Add compatible for SKOV i.MX8MP RevB board
7efe4371f644 dt-bindings: arm: fsl: add RVE gateway board
3c86e357feb0 dt-bindings: vendor-prefixes: add rve
04660a3dbd9f ARM: dts: broadcom: Add BCM63138's high speed UART
2e36ee7e60cd arm64: dts: ti: k3-am62x: Add overlay for IMX219
8478bfdedc00 arm64: dts: ti: k3-am62a7-sk: Enable camera peripherals
a361c10e44cc arm64: dts: ti: k3-am62x: Add overlays for OV5640
820399f7bf0f arm64: dts: ti: k3-am62x-sk: Enable camera peripherals
4de948eeb982 arm64: dts: ti: k3-am625-beagleplay: Add overlays for OV5640
8d6be01e5e7c arm64: dts: ti: k3-am62a-main: Enable CSI2-RX
d52951f9d78a arm64: dts: ti: k3-am62-main: Enable CSI2-RX
4d667e27b3fd arm64: dts: ti: k3-am65: Add AM652 dtsi file
3d2161ed0c2b dt-bindings: perf: fsl-imx-ddr: Add i.MX8DXL compatible
189fe310f16e dt-bindings: clock: support i.MX93 ANATOP clock module
b44d3f817227 ARM: dts: imx: tqma7: add lm75a sensor (rev. 01xxx)
b654e96c546e dt-bindings: display: simple: add Evervision VGG644804 panel
05a02c1a58e1 dt-bindings: ili9881c: Add Ampire AM8001280G LCD panel
96be0427a528 ARM: dts: rockchip: Move uart aliases to SoC dtsi for RK3128
18c0b8b47af4 ARM: dts: rockchip: Move i2c aliases to SoC dtsi for RK3128
0191774d40bb ARM: dts: rockchip: Move gpio aliases to SoC dtsi for RK3128
4b6344ed1b32 ARM: dts: rockchip: Add Sonoff iHost Smart Home Hub
3cbab293b053 dt-bindings: arm: rockchip: Add Sonoff iHost
afacdf8be4db ARM: dts: rockchip: Add rv1109 SoC
ad1e5ad721a5 ARM: dts: rockchip: Split up rgmii1 pinctrl on rv1126
fc0ef88ee0a1 ARM: dts: rockchip: Add i2c2 node to rv1126
bf739d2f67ae ARM: dts: rockchip: Serial aliases for rv1126
049605e5080d ARM: dts: rockchip: Add alternate UART pins to rv1126
59e8d345382e ARM: dts: rockchip: Enable GPU for XPI-3128
464bddcf0726 ARM: dts: rockchip: Add GPU node for RK3128
8af06043d850 ARM: dts: rockchip: Add power-controller for RK3128
8f65bb97112e dt-bindings: display: himax-hx8394: Add Powkiddy X55 panel
ed2d8407a82d dt-bindings: display: Document Himax HX8394 panel rotation
5319f5062c10 dt-bindings: display: simple: Add boe,bp101wx1-100 panel
db09be0ff97b ARM: dts: imx6q-apalis: add can power-up delay on ixora board
31fdbd1cd6c6 dt-bindings: display: msm: document the SM8650 Mobile Display Subsystem
52e16372d1c6 dt-bindings: display: msm: document the SM8650 DPU
258f55b8a6c7 dt-bindings: display: msm-dsi-controller-main: document the SM8650 DSI Controller
f06034e33173 dt-bindings: display: msm-dsi-phy-7nm: document the SM8650 DSI PHY
e7cafbdafccf dt-bindings: display: msm: Add SDM670 MDSS
58504ed9c645 dt-bindings: display/msm: sdm845-dpu: Describe SDM670
d8b80f6fd0c5 dt-bindings: display/msm: dsi-controller-main: add SDM670 compatible
0c71ce621111 arm64: dts: ti: k3-am625-beagleplay: Use UART name in pinmux name
0895f560a171 arm64: dts: ti: k3-am62a7-sk: Add interrupt support for IO Expander
696f6e8d6176 arm64: dts: ti: k3-am625-verdin: Enable Verdin UART2
145b9a5ffb00 arm64: dts: ti: k3-am62-main: Add gpio-ranges properties
0d95f5e22dde arm64: dts: ti: k3-am64: Enable SDHCI nodes at the board level
8ccabbb5322f arm64: dts: ti: k3-am65: Enable SDHCI nodes at the board level
4b9d0ee63df8 arm64: dts: ti: k3-am65: Add full compatible to dss-oldi-io-ctrl node
b64af72b8e7b arm64: dts: ti: k3-j784s4: Add chipid node to wkup_conf bus
a70ca898f980 arm64: dts: ti: k3-j721s2: Add chipid node to wkup_conf bus
638e0242808a arm64: dts: ti: k3-j721e: Add chipid node to wkup_conf bus
0b0e18c3dce2 arm64: dts: ti: k3-j7200: Add chipid node to wkup_conf bus
16b21e3cf2ea arm64: dts: ti: k3-am65: Add chipid node to wkup_conf bus
ba6541592794 dt-bindings: iio: light: isl76682: Document ISL76682
3678e1e114f2 dt-bindings: pinctrl: qcom,sm8550-lpass-lpi: add X1E80100 LPASS LPI
4854bb4b43e2 dt-bindings: pinctrl: pinctrl-single: add ti,j7200-padconf compatible
062b01e5c736 dt-bindings: iio: light: add support for Vishay VEML6075
3f170ed89d6f dt-bindings: usb: tps6598x: add reset-gpios property
69a424bfd498 dt-bindings: iio/adc: ti,palmas-gpadc: Drop incomplete example
5cf3c6e7327b dt-bindings: adi,ad5791: Add support for controlling RBUF
7a11d1470ed1 dt-bindings: display: bridge: lt8912b: Add power supplies
562bb8392ec6 spi: spl022: fix sleeping in interrupt context
83c535a1ec6b dt-bindings: iio: honeywell,mprls0025pa: drop ref from pressure properties
7cb202a1a899 dt-bindings: media: add bindings for stm32 dcmipp
fce776c784a0 dt-bindings: media: Add bindings for THine THP7312 ISP
23c5bf41000e dt-bindings: media: i2c: add galaxycore,gc2145 dt-bindings
e6429afd32f1 dt-bindings: vendor-prefixes: Add prefix for GalaxyCore Inc.
d1287a3d111f dt-bindings: gpio: rockchip: add a pattern for gpio hogs
e08aefe3ce14 Merge tag 'qcom-dts-for-6.7-2' into arm32-for-6.8
66862cc676b1 ARM: dts: qcom: Add support for HTC One Mini 2
ac27d4b5eaa6 Merge tag 'v6.7-rc4' into media_stage
8a745825682b arm64: dts: qcom: sm6350: Make watchdog bark interrupt edge triggered
4de273b8d5cf arm64: dts: qcom: sc8280xp: Make watchdog bark interrupt edge triggered
94d4ed6b0efb arm64: dts: qcom: sa8775p: Make watchdog bark interrupt edge triggered
9e80723d8b4f arm64: dts: qcom: sm8250: Make watchdog bark interrupt edge triggered
ef5fa5d97caa arm64: dts: qcom: sm8150: Make watchdog bark interrupt edge triggered
3879bc4c1c04 arm64: dts: qcom: sdm845: Make watchdog bark interrupt edge triggered
8e7e69e2041a arm64: dts: qcom: sc7280: Make watchdog bark interrupt edge triggered
6584d8b4799e arm64: dts: qcom: sc7180: Make watchdog bark interrupt edge triggered
04f80707bc19 arm64: dts: qcom: sc8180x: drop duplicated PCI iommus property
04597b9d0b6f dt-bindings: arm: qcom: Add HTC One Mini 2
7ff927ff9139 dt-bindings: vendor-prefixes: document HTC Corporation
fa70da0426ea arm64: dts: qcom: sm8550: correct TX Soundwire clock
ed7e07a029d6 arm64: dts: qcom: sm8450: correct TX Soundwire clock
541ded0776d2 arm64: dts: qcom: sc8180x-primus: Fix HALL_INT polarity
39c752cf5603 arm64: dts: qcom: sc8280xp-crd: fix eDP phy compatible
e5319a1187df arm64: dts: qcom: sdm632-fairphone-fp3: Enable LPASS
daf6cf6a007f arm64: dts: qcom: msm8916-acer-a1-724: Add notification LED
2a186fbc9370 arm64: dts: qcom: ipq6018: use CPUFreq NVMEM
91d98fe1640a arm64: dts: qcom: msm8939-huawei-kiwi: Add initial device tree
6718a893d987 dt-bindings: arm: qcom: Add Huawei Honor 5X / GR5 (2016)
f36c60304a90 arm64: dts: qcom: msm8953: Use non-deprecated qcom,domain in LPASS
fa91149122fc arm64: dts: qcom: qrb2210-rb1: add wifi variant property
9862c76b6484 arm64: dts: qcom: qrb2210-rb1: Enable CAN bus controller
90510995b456 arm64: dts: qcom: qrb2210-rb1: Set up HDMI
f168a1f5fd2a arm64: dts: qcom: qcm2290: Hook up interconnects
a66c95bb5052 arm64: dts: qcom: qcm2290: Add display nodes
1b3d99e8ad9d arm64: dts: qcom: sc7280: Add the missing MDSS icc path
463b9cc7faa3 arm64: dts: qcom: sc7180: Add the missing MDSS icc path
a2b32f52593b arm64: dts: qcom: sc8280xp: Add QMP handle to RPMh stats
0541077473ea dt-bindings: soc: qcom: stats: Add QMP handle
46fd383def7f arm64: dts: qcom: sm8250-xiaomi-elish: Add pm8150b type-c node and enable usb otg
45ca7aacee21 arm64: dts: qcom: sm8250-xiaomi-elish: Fix typos
9dee357f1ff5 arm64: dts: qcom: msm8939-longcheer-l9100: Add proximity-near-level
d6b8367dbb65 arm64: dts: qcom: qrb4210-rb2: Enable bluetooth
9e8fcdbc4d75 arm64: dts: qcom: sm6115: Add UART3
e88a0c4a9117 arm64: dts: qcom: sdm632-fairphone-fp3: Enable WiFi/Bluetooth
a808b8c6d7f4 dt-bindings: arm: qcom: Fix html link
004244e4cbd5 arm64: dts: qcom: Add base qcs6490-rb3gen2 board dts
3f55e77ebc86 arm64: dts: qcom: Add base qcm6490 idp board dts
9e08836a864f dt-bindings: arm: qcom: Add QCM6490 IDP and QCS6490 RB3Gen2 board
c538a9224903 arm64: dts: qcom: sm4450-qrd: mark QRD4450 reserved gpios
34764956c2e4 arm64: dts: qcom: sm4450-qrd: add QRD4450 uart support
b5fe030e21e0 arm64: dts: qcom: sm4450: add uart console support
76478ce29df3 arm64: dts: qcom: sm4450: Add RPMH and Global clock
52ea11ee57e9 arm64: dts: qcom: sm4450: Add apps_rsc and cmd_db node
d42f9497ccad arm64: dts: qcom: ipq8074: pass QMP PCI PHY PIPE clocks to GCC
9b98d0a1718e dt-bindings: clocks: qcom,gcc-ipq8074: allow QMP PCI PHY PIPE clocks
2417b30e3609 arm64: dts: qcom: msm8953: add SPI interfaces
66dd2b49a0b3 arm64: dts: qcom: qcm6490-fairphone-fp5: Add PM7325 thermals
0b651704285a arm64: dts: qcom: qcm6490-fairphone-fp5: Add PMK7325 thermals
8630d7baedf5 arm64: dts: qcom: qcm6490-fairphone-fp5: Add PM7250B thermals
959371b1b650 iio: adc: Add PM7325 PMIC7 ADC bindings
b1e6472aae24 arm64: dts: qcom: sm8250: Add OPP table support to UFSHC
6aeff20d0bd6 arm64: dts: qcom: sdm845: Add OPP table support to UFSHC
e8d1d500097e ARM: dts: qcom: msm8974: Add watchdog node
615027dbbe1d dt-bindings: arm: qcom: drop the IPQ board types
ebb3e763ee5b arm64: dts: qcom: ipq5018: enable the CPUFreq support
3ca74e9810cf dt-bindings: clock: qcom,a53pll: add IPQ5018 compatible
dcbafe8963f4 ARM: dts: qcom: sdx65: correct SPMI node name
98b030d58c93 ARM: dts: qcom: sdx65: add missing GCC clocks
07a16205d0e0 ARM: dts: qcom: sdx65: correct PCIe EP phy-names
fe48cd5331dc dt-bindings: display: msm: Add reg bus and rotator interconnects
8c1892c5f696 dt-bindings: display: msm: qcm2290-mdss: Use the non-deprecated DSI compat
7cfd5769a991 dt-bindings: display/msm: qcom, sm8150-mdss: correct DSI PHY compatible
91abf991ed4a dt-bindings: display/msm: qcom, sm8250-mdss: add DisplayPort controller node
c203dee53e38 ARM: dts: rockchip: Enable gmac for XPI-3128
a31102a06882 ARM: dts: rockchip: Add gmac node for RK3128
d02bab784773 dt-bindings: gpu: mali-utgard: Add Rockchip RK3128 compatible
61b6b8e5340b dt-bindings: net: qcom,ipa: document SM8650 compatible
a0fa8df10233 Merge tag 'renesas-pinctrl-for-v6.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
6c58c6977828 dt-bindings: gpio: modepin: Describe label property
7f00d1c96321 dt-bindings: display: ti: Add support for am62a7 dss
6bed64726635 arm64: dts: ti: k3-am68-sk-base-board: Add alias for MCU CPSW2G
f494c9948974 arm64: dts: ti: iot2050: Add icssg-prueth nodes for PG2 devices
403938b5222f arm64: dts: ti: iot2050: Refactor the m.2 and minipcie power pin
45e3b6aa9185 arm64: dts: ti: iot2050: Definitions for runtime pinmuxing
b14c51a347fb arm64: dts: ti: iot2050: Drop unused ecap0 PWM
38f52ad2cea9 arm64: dts: ti: iot2050: Re-add aliases
a84e54a6c2a0 arm64: dts: ti: k3-am62x-sk-common: Mark mcu gpio and mcu_gpio_intr as reserved
0baa456c51ce arm64: dts: ti: k3-am62p5-sk: Mark mcu gpio and mcu_gpio_intr as reserved
131aadfec025 arm64: dts: ti: k3-am642-evm/sk: Mark mcu_gpio_intr as reserved
bbda0d8be30e arm64: dts: ti: k3-am64-main: Fix typo in epwm_tbclk node name
5e8876dba890 arm64: dts: ti: k3-am65-main: Fix DSS irq trigger type
fd78a91dedf3 arm64: dts: ti: k3-am62a-main: Fix GPIO pin count in DT nodes
05614d5b4f00 arm64: dts: ti: minor whitespace cleanup around '='
ca6dff24071e ARM: dts: omap4-embt2ws: Add Bluetooth
cff0864e2eea Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
2a2ae1545117 dt-bindings: input: gpio-keys: Allow optional dedicated wakeirq
aed93474ebc0 Merge patch series "Add Huashan Pi board support"
318917bad2c6 riscv: dts: sophgo: add Huashan Pi board device tree
8a2824be66df riscv: dts: sophgo: add initial CV1812H SoC device tree
3ff295494c04 riscv: dts: sophgo: cv18xx: Add gpio devices
dfcd3e4c81d9 riscv: dts: sophgo: Separate compatible specific for CV1800B soc
8c5d4ad957fa dt-bindings: riscv: Add SOPHGO Huashan Pi board compatibles
e393d2e6705e dt-bindings: timer: Add SOPHGO CV1812H clint
65cc6be0d442 dt-bindings: interrupt-controller: Add SOPHGO CV1812H plic
dce8266bb548 ARM: dts: omap: logicpd-torpedo: do not disguise GNSS device
0f0cee70a881 ARM: dts: omap4-embt2ws: enable 32K clock on WLAN
33dfdcf03832 ARM: dts: ti/omap: Replace deprecated extcon-usb-gpio id-gpio/vbus-gpio properties
aa5a9a109405 dt-bindings: power: meson-g12a-power: document ISP power domain
a9f86a1f45b5 dt-bindings: marvell: Add Marvell MV88E6060 DSA schema
5024553a10f5 dt-bindings: marvell: Rewrite MV88E6xxx in schema
ad4c44e96eec dt-bindings: net: ethernet-switch: Accept special variants
17baedd697fb dt-bindings: net: mvusb: Fix up DSA example
9c7ccdf2dc30 dt-bindings: net: dsa: Require ports or ethernet-ports
8adbf64f3cdd dt-bindings: input: mediatek,pmic-keys: Drop incomplete example
cdc098b167e1 dt-bindings: input: sprd,sc27xx-vibrator: Drop incomplete example
0629a76a9d04 dt-bindings: correct white-spaces in examples
2f78b6dd5c42 dt-bindings: reset: hisilicon,hi3660-reset: Drop providers and consumers from example
f835598ebf60 dt-bindings: arm/calxeda: drop unneeded quotes
0d2567437a54 dt-bindings: fsl,dpaa2-console: drop unneeded quotes
352ed027a423 dt-bindings: interrupt-controller: qcom,pdc: document pdc on X1E80100
df641036bac4 dt-bindings: qcom,pdc: document the SM8650 Power Domain Controller
1e17b2ba4499 dt-bindings: interrupt-controller: Add SDX75 PDC compatible
c0aff4abb03a dt-bindings: reset: imx-src: Simplify compatible schema and drop unneeded quotes
df20c9f94014 dt-bindings: reset: qcom: drop unneeded quotes
1516b28c7069 dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/Five SoC
a80bc27a0fe8 dt-bindings: reset: Add compatible and DT bindings for Amlogic C3 Reset Controller
0b8db84ecfc4 ASoC: Intel: Soundwire related board and match updates
303600aff1ef Merge v6.7-rc3 into drm-next
d03f6dca688d arm64: dts: rockchip: Use NCM6A-IO board for edgeble-neu6b
2dcf7dbe2812 dt-bindings: arm: rockchip: Update edgeble-neu6 bindings
b2a45d98f95b arm64: dts: rockchip: add USB3 host on rk3588s-orangepi-5
766aa3119c2f ARM: dts: motorola-mapphone: Add basic support for mz609 and mz617
3ea15a23d9c7 ARM: dts: motorola-mapphone: Move handset devices to a common file
5127524f7e6f ARM: dts: motorola-mapphone: Move LCD to common file for xt875 and xt894
7e16bd264a3a dt-bindings: omap: Add Motorola mapphone mz609 and mz617 tablets
7d420d843f98 ARM: dts: renesas: r9a06g032: Add missing space in compatible
0faa59be192f arm64: dts: renesas: r9a09g011: Add missing space in compatible
807cfe5cde5c dt-bindings: phy: add compatible for Mediatek MT8195
c52707b1bf77 dt-bindings: phy: amlogic,g12a-mipi-dphy-analog: drop unneeded reg property and example
34ec5dda2a01 dt-bindings: phy: amlogic,meson-axg-mipi-pcie-analog: drop text about parent syscon and drop example
f738d7a9dfab dt-bindings: iommu: dart: Add t8103-usb4-dart compatible
2c963cfa7e8e ARM: dts: renesas: armadillo800eva: Add LCD panel
a35135dad31c dt-bindings: pinctrl: renesas: Drop unneeded quotes
d5212619f0a0 ARM: dts: renesas: r8a7740: Add LCDC nodes
048bdb67a0f6 arm64: dts: renesas: draak: Move HDMI bus properties to correct node
ab52a67f9767 arm64: dts: renesas: draak: Make HDMI the default video input
dab3ba03f28c Merge 6.7-rc3 into usb-next
ec6cd76a8793 arm64: dts: meson-axg: jethub-jxx add support for EEPROM
2da076589eac arm64: dts: amlogic: meson-axg: pinctrl node for NAND
cdc5df918882 arm64: dts: amlogic: minor whitespace cleanup around '='
a5dead35fc4b arm64: dts: Add watchdog node for Amlogic S4 SoCs
37c5369b4667 arm64: dts: Add watchdog node for Amlogic C3 SoCs
1d8b2a265b81 dt-bindings: soc: amlogic,meson-gx-hhi-sysctrl: add example covering meson-axg-hhi-sysctrl
9556e1708419 ARM: dts: imx7s: Add DMA channels for CSPI peripherals
c1e5b6c6855f arm64: dts: imx8mp-venice-gw72xx: add TPM device
fc1ee0050ce4 arm64: dts: imx8mm-venice-gw72xx: add TPM device
5a125bf20bf1 arm64: dts: imx93: update anatop node
292fc296ecdd arm64: dts: imx93-11x11-evk: add 12 ms delay to make sure the VDD_SD power off
b81451d8d4d3 arm64: dts: imx93: change tuning start to get a large scan range for standard tuning
7ee940495143 arm64: dts: imx93-11x11-evk: set SION for cmd and data pad of USDHC
1b2037987962 arm64: dts: imx8mp: Describe M24C32-D write-lockable page in DH i.MX8MP DHCOM DT
94d5d7d36ba8 ARM: dts: imx6ul: mba6ulx: fix typo in comments
cbbed6036bfe ARM: dts: imx6qdl: mba6: fix typo in comments
e6c50d6fd99e arm64: dts: imx8mp-beacon-kit: Enable DSI to HDMI Bridge
3743277142d0 arm64: dts: imx8mm: Add CCM interrupts
663758efb819 arm64: dts: imx8mn: Add CCM interrupts
88774bafda13 arm64: dts: imx8mp: Add CCM interrupts
e4d9f4208c6c ARM: dts: imx7s: Add missing #thermal-sensor-cells
e4c3f040fee6 ARM: dts: imx7s: Fix nand-controller #size-cells
62a7c97c7c3f ARM: dts: imx7s: Fix lcdif compatible
9f3037b332bf ARM: dts: imx7d: Fix coresight funnel ports
d844fe5270b1 arm64: dts: freescale: add initial device tree for MBa93xxCA starter kit
ad161fbd54ca arm64: dts: freescale: tqma9352-mba93xxla: add 'chassis-type' property
8ec09c8f530c arm64: dts: imx93: Configure clock rate for audio PLL
9d7ba48273ea arm64: dts: imx93: Add audio device nodes
b1553710809c dt-bindings: iio: hmc425a: add entry for ADRF5740 Attenuator
471ace1f09be dt-bindings: gpio: brcmstb: drop unneeded quotes
f8159413e6f1 ARM: dts: ti: keystone: minor whitespace cleanup around '='
381a63044158 dt-bindings: clock: g12a-clkc: add MIPI ISP & CSI PHY clock ids
c1ad3e49f07c dt-bindings: clk: g12a-clkc: add CTS_ENCL clock ids
c8fb56a76774 dt-bindings: dma: qcom,gpi: document the SM8650 GPI DMA Engine
8e868f10ea21 dt-bindings: dma: rz-dmac: Document RZ/Five SoC
e1504d7602c0 dt-bindings: net: qcom,ipa: add SM8550 compatible
f118e169a194 dt-bindings: dma: qcom: gpi: add compatible for X1E80100
11518ff4d13c dt-bindings: pinctrl: qcom: Add X1E80100 pinctrl
d3fe1008f0c8 ASoC: dt-bindings: correct white-spaces in examples
f9b11918132f dt-bindings: crypto: convert Inside Secure SafeXcel to the json-schema
52b8a84c5283 dt-bindings: dma: ti: k3-udma: Describe cfg register regions
9b2e4fa1e7f2 dt-bindings: dma: ti: k3-pktdma: Describe cfg register regions
6d91e2a3766b dt-bindings: dma: ti: k3-bcdma: Describe cfg register regions
ea1d92699d2a dt-bindings: dma: ti: k3-*: Add descriptions for register regions
7cf45f021d31 arm64: dts: exynosautov9: use Exynos7 fallbacks for pin wake-up controller
dc0e2a7e69c2 arm64: dts: exynos850: use Exynos7 fallbacks for pin wake-up controllers
185cc3e40c9f dt-bindings: pinctrl: samsung: use Exynos7 fallbacks for newer wake-up controllers
54829849af39 Merge branch 'icc-x1e80100' into icc-next
8e2202f335a4 dt-bindings: interconnect: Add Qualcomm X1E80100 SoC
54f1f68e019b dt-bindings: interconnect: qcom-bwmon: document SM8650 BWMONs
4e7bf80ce812 dt-bindings: interconnect: document the RPMh Network-On-Chip Interconnect in Qualcomm SM8650 SoC
615397ecb02b Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
e673bd9cbb13 dt-bindings: serial: fsl-linflexuart: change the maintainer email address
f79b00fe4cab dt-bindings: serial: renesas,sci: Document RZ/Five SoC
911d5cce2a4e Merge tag 'drm-misc-next-2023-11-23' of git://anongit.freedesktop.org/drm/drm-misc into drm-next
ab1f350663b1 dt-bindings: power: rpmpd: Update part number to X1E80100
6fe8e1a8dc99 dt-bindings: backlight: mp3309c: Remove two required properties
cc4e22233cb5 dt-bindings: usb: qcom,dwc3: adjust number of interrupts on SM6125
9161184d7271 dt-bindings: net: renesas,ethertsn: Add Ethernet TSN
788d52642da4 Merge tag 'v6.7-rc2' into media_stage
d2975fb00035 dt-bindings: gpu: Add Imagination Technologies PowerVR/IMG GPU
59078ccb21d1 dt-bindings: usb: qcom,dwc3: document the SM8560 SuperSpeed DWC3 USB controller
627316c016dd dt-bindings: usb: renesas,usbhs: Document RZ/Five SoC
99b07ecabc3d dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible
0118ff6d8abd ASoC: dt-bindings: fsl,mqs: Convert format to json-schema
0a9a12593184 ASoC: dt-bindings: sound-card-common: List sound widgets ignoring system suspend
165648aad162 ARM: dts: stm32: add SPI support on STM32F746
8f3fa20269a0 ARM: dts: stm32: add STM32F746 syscfg clock
dc50601ba2d8 dt-bindings: net: xlnx,axi-ethernet: Introduce DMA support
72d23e1de1b0 arm64: dts: imx8mp: Add reserve-memory nodes for DSP
9bab315d31f8 spi: axi-spi-engine improvements
23a75f159231 ARM: dts: stm32: use the same 3v3 for SD and DSI nodes on stm32f469-disco
4656437906e9 ARM: dts: rockchip: Make usbphy the parent of SCLK_USB480M for RK3128
25251d661471 ARM: dts: rockchip: Add dwc2 otg fifo siztes for RK3128
2d36fa2aa286 ARM: dts: rockchip: Add USB host clocks for RK3128
4e1bd401bbe3 ARM: dts: rockchip: Add Geniatech XPI-3128 RK3128 board
7e6458d9a7f3 ARM: dts: rockchip: Add sdmmc_det pinctrl for RK3128
12867f1ccb42 dt-bindings: arm: rockchip: Add Geniatech XPI-3128
fda729bcbd69 arm64: dts: rockchip: Add Powkiddy RK2023
317a36f59e1b arm64: dts: rockchip: Update powkiddy,rgb30 include to rk2023 DTSI
dc9a81379af6 dt-bindings: arm: rockchip: Add Powkiddy RK2023
70a31fd9ffa3 dt-bindings: spi: axi-spi-engine: convert to yaml
b68504144dbe Merge tag 'drm-misc-next-2023-11-17' of git://anongit.freedesktop.org/drm/drm-misc into drm-next
8260e721d1b5 dt-bindings: display: nv3051d: Update NewVision NV3051D compatibles
0a502f9716cc arm64: dts: renesas: rzg3s-smarc: Enable SDHI1
eccf7ee1aefe arm64: dts: renesas: rzg3s-smarc-som: Enable SDHI2
fbd14cd9ff35 ARM: dts: microchip: sam9x60ek: Add IRQ support for ethernet PHY
c86d9749ca2a ARM: dts: microchip: sam9x60_curiosity: Add IRQ support for ethernet PHY
1e1f6887a01b arm64: dts: allwinner: h616: add Orange Pi Zero 2W support
5795c68b5edc dt-bindings: arm: sunxi: add Orange Pi Zero 2W
a5b7fa02fbde dt-bindings: crypto: qcom,prng: document SM8650
53be5450f8ac dt-bindings: crypto: qcom-qce: document the SM8650 crypto engine
e65dc233e98b dt-bindings: crypto: qcom,inline-crypto-engine: document the SM8650 ICE
d2a2bd80cca6 dt-bindings: net: renesas,etheravb: Document RZ/Five SoC
f491b5315b58 dt-bindings: Document Marvell Aquantia PHY
7b52e889e53f arm64: dts: rockchip: add analog audio to RK3588 EVB1
92de4720f37c spi: dt-bindings: renesas,rspi: Document RZ/Five SoC
6e54c4bd7590 ASoC: dt-bindings: renesas,rz-ssi: Document RZ/Five SoC
87bb03481662 dt-bindings: adis16460: Add 'spi-cs-inactive-delay-ns' property
91e2c8ceb4de dt-bindings: adis16475: Add 'spi-cs-inactive-delay-ns' property
f9fe5526efd5 dt-bindings: iio: Add MCP9600 thermocouple EMF converter
9942ece9d870 dt-bindings: iio: imu: Add Bosch BMI323
49d380d6e152 dt-bindings: adc: provide max34408/9 device tree binding document
895869158303 dt-bindings: media: wave5: add yaml devicetree bindings
77bf61c28407 dt-bindings: arm: Add support for DSB MSR register
18adf91da0ca dt-bindings: arm: Add support for DSB element size
075ac55ca93b dt-bindings: phy: qcom,snps-eusb2: document the SM8650 Synopsys eUSB2 PHY
fda8409f7058 dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: document the SM8650 QMP USB/DP Combo PHY
b0b6815d9143 dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: document the SM8650 QMP PCIe PHYs
db24b834638a dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: document the SM8650 QMP UFS PHY
6a737e056a8b media: dt-bindings: Add JH7110 Camera Subsystem
716cbea9d35a dt-bindings: power: reset: $ref reboot-mode in nvmem-reboot-mode
c8dedfdf167b dt-bindings: power: reset: $ref reboot-mode in syscon-reboot-mode
6c14a95472bb ARM: dts: samsung: s5pv210: fix camera unit addresses/ranges
866767db6bbb ARM: dts: samsung: exynos4: fix camera unit addresses/ranges
f0d3848e2cef ARM: dts: samsung: exynos4x12: replace duplicate pmu node with phandle
dc6ff9889013 dt-bindings: w1: Add AMD AXI w1 host and MAINTAINERS entry
a8a9188e96a6 dt-bindings: power: fsl,scu-pd: Document imx8dl
f06b78172daa dt-bindings: qcom,pdc: Add compatible for SM8550
7a87643120eb dt-bindings: input: samsung,s6sy761: convert to DT schema
e4ccdd770c53 Merge branch 'for-v6.8/samsung-bindings-compatibles' into next/dt64
7b213bd80e13 dt-bindings: hwinfo: samsung,exynos-chipid: add exynosautov920 compatible
892b87e000d2 dt-bindings: arm: samsung: Document exynosautov920 SADK board binding
ce1b89aee7ea dt-bindings: pwm: samsung: add exynosautov920 compatible
5e6bd42714ad dt-bindings: serial: samsung: add exynosautov920-uart compatible
3ea12f0eff84 dt-bindings: samsung: usi: add exynosautov920-usi compatible
5b6e042a72b8 dt-bindings: samsung: exynos-pmu: add exynosautov920 compatible
2dff85192843 dt-bindings: samsung: exynos-sysreg: add exynosautov920 sysreg
3123103c12c0 dt-bindings: pinctrl: samsung: add exynosautov920
5b929ffdc9be arm64: dts: exynos: add gpio-key node for exynosautov9-sadk
6bc5effbe8dd arm64: dts: exynosautov9: add specific compatibles to several blocks
25addf827769 arm64: dts: exynos850: add specific compatibles to several blocks
5ab70c11f08f arm64: dts: exynos7885: add specific compatibles to several blocks
f7c77a1ea95a arm64: dts: exynos7: add specific compatibles to several blocks
56493af64c01 arm64: dts: exynos5433: add specific compatibles to several blocks
3530786802b6 dt-bindings: pwm: samsung: add specific compatibles for existing SoC
97419692fe3c ASoC: dt-bindings: samsung-i2s: add specific compatibles for existing SoC
7081448ca2cf dt-bindings: iio: samsung,exynos-adc: add specific compatibles for existing SoC
973115e1f51f dt-bindings: gpu: arm,mali-midgard: add specific compatibles for existing Exynos SoC
6b99281097f0 dt-bindings: samsung: exynos-pmu: add specific compatibles for existing SoC
a893a294345b dt-bindings: serial: samsung: add specific compatibles for existing SoC
2a3d0691d56f dt-bindings: rtc: s3c-rtc: add specific compatibles for existing SoC
7e49408d51e6 dt-bindings: pinctrl: samsung: add specific compatibles for existing SoC
1bb1eca74ad5 Merge drm/drm-next into drm-misc-next
e9731895ee20 dt-bindings: mmc: samsung,exynos-dw-mshc: add specific compatibles for existing SoC
33b5aa8f7d9a ARM: dts: qcom: mdm9615: drop qcom, prefix from SSBI node name
fa1f536e3df0 ARM: dts: qcom: ipq8064: drop qcom, prefix from SSBI node name
4e5382dc8820 ARM: dts: qcom: apq8060-dragonboard: rename mpp ADC channels to adc-channel
6be6ba7888ef ARM: dts: qcom: pm8921: Disable keypad by default
5917ae72cd70 ARM: dts: qcom: msm8974: move regulators to board files
551cbcd2547c ARM: dts: qcom: msm8960: drop useless rpm regulators node
6d9878cc6a6a ARM: dts: qcom: msm8660: move RPM regulators to board files
d0ed11e33ba0 ARM: dts: qcom: mdm9615: move RPM regulators to board files
1c636116afea ARM: dts: qcom: apq8064: move RPM regulators to board files
b9d11fecae9e ARM: dts: qcom: pm8058: switch to interrupts-extended
e8a26b432fd4 ARM: dts: qcom: pm8018: switch to interrupts-extended
86831cb445f6 ARM: dts: qcom: pm8921: switch to interrupts-extended
6d6c0b95e077 ARM: dts: qcom: pm8058: use defined IRQ flags
9d0903209824 ARM: dts: qcom: pm8921: move reg property
6a63db48b660 ARM: dts: qcom: pm8018: move reg property
9d6af1dd4790 ARM: dts: qcom: pm8921: reorder nodes
5db5515193a6 ARM: dts: qcom: pm8058: reorder nodes
d4df6f1babb5 ARM: dts: qcom: msm8660: split PMIC to separate dtsi files
c56480ffb4b8 ARM: dts: qcom: mdm9615: split PMIC to separate dtsi files
f8574d2c7c62 ARM: dts: qcom: apq8064: split PMICs to separate dtsi files
298695290d90 ARM: dts: qcom: msm8960: split PMIC to separate dtsi files
1c3c930ec46c ARM: dts: qcom: msm8960: move PMIC interrupts to the board files
7f5541db889f ARM: dts: qcom: msm8660: move PMIC interrupts to the board files
812cfe71b26a ARM: dts: qcom: mdm9615: move PMIC interrupts to the board files
f5c8a18b7116 ARM: dts: qcom: apq8064: move PMIC interrupts to the board files
b7510b8da2f6 ARM: dts: qcom: msm8960: fix PMIC node labels
6475671dcca1 ARM: dts: qcom: msm8660: fix PMIC node labels
4dfac4d841ef ARM: dts: qcom: mdm9615: fix PMIC node labels
07091c1b87fb ARM: dts: qcom: apq8064: fix PMIC node labels
155004433670 ARM: dts: qcom: strip prefix from PMIC files
21220b16b281 ARM: dts: qcom: mdm9615-wp8548-mangoh-green: group include clauses
3d3f8059a9f6 ARM: dts: qcom: apq8064-nexus7: move sdcc1 node to proper place
b9d136b033b8 ARM: dts: qcom: msm8660-surf: use keypad label directly
fc4f79da1abe ARM: dts: qcom: msm8960: introduce label for PMIC keypad
0e33f3448e7c ARM: dts: qcom: apq8064: correct XOADC register address
9bed8b24890a ARM: dts: qcom-sdx65: switch USB QMP PHY to new style of bindings
edfbe32172f4 ARM: dts: qcom-sdx55: switch USB QMP PHY to new style of bindings
c709366fb89e arm64: dts: qcom: sm8350: switch USB QMP PHY to new style of bindings
29a99a6d955d arm64: dts: qcom: sm8250: switch USB QMP PHY to new style of bindings
e13f8dc0ea91 arm64: dts: qcom: sm8150: switch USB QMP PHY to new style of bindings
bed6aed8ceec arm64: dts: qcom: sdm845: switch USB QMP PHY to new style of bindings
7cb8dff829b0 arm64: dts: qcom: msm8998: switch USB QMP PHY to new style of bindings
77a8ce42cb30 arm64: dts: qcom: msm8996: switch USB QMP PHY to new style of bindings
b92a18870b3e arm64: dts: qcom: ipq8074: switch USB QMP PHY to new style of bindings
18dd153b1c8f arm64: dts: qcom: ipq6018: switch USB QMP PHY to new style of bindings
ad3769d7933c Merge tag 'qcom-arm64-for-6.7-2' into arm64-for-6.8
8088e683c89b dt-bindings: i2c: samsung,s3c2410-i2c: add specific compatibles for existing SoC
c15df41a0c35 dt-bindings: i2c: exynos5: add specific compatibles for existing SoC
d755df63e9df dt-bindings: hwinfo: samsung,exynos-chipid: add specific compatibles for existing SoC
6f4cb3f40711 arm64: dts: renesas: rzg2lc-smarc-som: Enable 4-bit tx support
5ddba1791b2b arm64: dts: renesas: rzg2l-smarc-som: Enable 4-bit tx support
75b8e7f58abe regulator: add under-voltage support (part 2)
791f1550a798 Add DMIC slew rate controls
e128625eb7cb dt-bindings: pinctrl: document the SM8650 Top Level Mode Multiplexer
c3c85cc965c8 dt-bindings: pinctrl: qcom,sm8650-lpass-lpi-pinctrl: add SM8650 LPASS
6da3c9fd1509 ARM: dts: renesas: marzen: Rename keyboard nodes
2d7a77894ba8 ARM: dts: renesas: iwg22d-sodimm: Fix stmpe node names
f4c62eb4fbd6 arm64: dts: renesas: Add missing ADV751[13] power supply properties
a94c426db9b8 ARM: dts: renesas: Add missing ADV751[13] power supply properties
f213adc3b192 ARM: dts: renesas: rcar-gen2: Fix I2C bus demux node names
127c56414e9f riscv: dts: renesas: Convert isa detection to new properties
9836c1c69324 ARM: dts: renesas: blanche: Add FLASH node
d446795daa00 ARM: dts: renesas: marzen: Add FLASH node
9a4a8a78013a spi: add stm32f7-spi compatible
e74e9793f9c7 regulator: dt-bindings: Add 'regulator-uv-less-critical-window-ms' property
eafbf4f37d51 regulator: dt-bindings: Allow system-critical marking for fixed-regulator
52381ed5b4ac regulator: dt-bindings: Add system-critical-regulator property
ec8f058714a6 dt-bindings: regulator: qcom,smd-rpm-regulator: Document PM8937 IC
cf118cc80e89 dt-bindings: regulator: qcom,spmi-regulator: Document PM8937 PMIC
2ae471b5eeb2 ASoC: dt-bindings: use "soundwire" as controller's node name in examples
caa17228e281 ASoC: dt-bindings: qcom,sm8250: add SM8550 sound card
2d2f997a2bdc dt-bindings: es8328: convert to DT schema format
68e113702391 ASoC: dt-bindings: Simplify port schema
eac536a576c7 ASoC: dt-bindings: nau8821: Add DMIC slew rate.
409f501ee9b2 dt-bindings: gpu: v3d: Add BCM2712's compatible
22f7441e8685 dt-bindings: display: ssd132x: Remove '-' before compatible enum
a3de98e60ec5 ARM: dts: qcom: add device tree for Nokia Lumia 830
9ad6bcd4499d ARM: dts: qcom: add device tree for Nokia Lumia 735
41ee9ea2aefd ARM: dts: qcom: add device tree for Microsoft Lumia 640 XL
0dc127c0d612 ARM: dts: qcom: add device tree for Microsoft Lumia 640
d30c995f440e ARM: dts: qcom: add common dt for MSM8x26 Lumias along with Nokia Lumia 630
ed92546211d5 dt-bindings: arm: qcom: Document MSM8x26-based Lumia phones
d783936fa1dc arm64: dts: qcom: msm8939-longcheer-l9100: Enable RGB LED
b14cb550d720 arm64: dts: qcom: msm8916-longcheer-l8910: Enable RGB LED
183a2f447424 arm64: dts: qcom: msm8939-samsung-a7: Add sound and modem
9b7d68606781 arm64: dts: qcom: msm8916-samsung-j5: Add sound and modem
f382f197e0c5 arm64: dts: qcom: msm8916-samsung-gt5: Add sound and modem
59a815c1572d arm64: dts: qcom: msm8916-longcheer-l8910: Add sound and modem
582b4cfec9a9 ARM: dts: qcom: msm8226: provide dsi phy clocks to mmcc
1703230be2a6 ARM: dts: qcom: msm8974: sort nodes by reg
e23f302820cb ARM: dts: qcom: msm8974: replace incorrect indentation in interconnect
373015625e6b arm64: dts: qcom: msm8916-longcheer-l8150: Add sound and modem
c1a66861dc32 arm64: dts: qcom: msm8916-asus-z00l: Add sound and modem
489f91f0dfcc arm64: dts: qcom: msm8916-alcatel-idol347: Add sound and modem
2f81e02a3b04 arm64: dts: qcom: msm8916-wingtech-wt88047: Add sound and modem
07047876d71e arm64: dts: qcom: msm8916-samsung-serranove: Add sound and modem
1d94420f32b0 arm64: dts: qcom: msm8916-samsung-a2015: Add sound and modem
9334b10d351c arm64: dts: qcom: msm8916: Add common msm8916-modem-qdsp6.dtsi
30b857e0f639 arm64: dts: qcom: msm8939: Add QDSP6
5b210c47425a arm64: dts: qcom: msm8916: Add QDSP6
f1aed61c2c48 arm64: dts: qcom: msm8939: Add BAM-DMUX WWAN
702f57c12856 arm64: dts: qcom: sc8280xp-x13s: add missing camera LED pin config
d21fc2d89cfd arm64: dts: qcom: pm7250b: Use correct node name for gpios
ecc4cb08c0f3 arm64: dts: qcom: sc7280: Add Camera Control Interface busses
c01ef95e3aa7 arm64: dts: qcom: sdm845-xiaomi-beryllium: enable flash led
fe3ccb41dafa arm64: dts: qcom: sdm845-oneplus: enable flash LED
0f6538f89c64 arm64: dts: qcom: sc8280xp-x13s: Use the correct DP PHY compatible
c9e8e85b1afd arm64: dts: qcom: msm8916-*: Fix alphabetic node order
9e38e840740d arm64: dts: qcom: msm8939-longcheer-l9100: Enable wcnss_mem
5cdb05e593ef arm64: dts: qcom: msm8916-samsung-gt5: Enable GPU
0d72dfbbf352 arm64: dts: qcom: ipq5332: include the GPLL0 as clock provider for mailbox
13c545bfe884 arm64: dts: qcom: ipq9574: include the GPLL0 as clock provider for mailbox
8b57686e7ad0 arm64: dts: qcom: ipq6018: include the GPLL0 as clock provider for mailbox
11d8f7a1bf44 arm64: dts: qcom: ipq8074: include the GPLL0 as clock provider for mailbox
9b0b036ea0de arm64: dts: qcom: ipq9574: populate the opp table based on the eFuse
f3636ba1edce arm64: dts: qcom: ipq5332: populate the opp table based on the eFuse
8831b26a6579 arm64: dts: qcom: sdm670: add specific cpufreq compatible
8ce87f299cdb arm64: dts: qcom: sm8150: extend the size of the PDC resource
b3cbe4ff9c30 arm64: dts: qcom: ipq5018: add QUP1 SPI controller
f330c2991aa0 arm64: dts: qcom: qrb4210-rb2: don't force usb peripheral mode
daa68cbafb06 arm64: dts: qcom: Enable tsens and thermal for sa8775p SoC
6232143457ae arm64: dts: qcom: sa8775p: Add RPMh sleep stats
973959c2edf1 arm64: dts: qcom: sc7280: Add ports subnodes in usb/dp qmpphy node
4c021a56b758 arm64: dts: qcom: sm6375-pdx225: Add USBPHY regulators
6fb033b4f60e arm64: dts: qcom: sm6375-pdx225: Enable ATH10K WiFi
fa14ce25949b arm64: dts: qcom: sm6375-pdx225: Enable MSS
e77ac5cceb8e arm64: dts: qcom: sm6375: Add UART1
dec2e7998de5 arm64: dts: qcom: ipq9574: Enable WPS buttons
d3619641203e arm64: dts: qcom: ipq9574: Add common RDP dtsi file
9faa71835343 arm64: dts: qcom: ipq5018: Enable USB
71275274da1f arm64: dts: qcom: ipq5018: Add USB related nodes
af8b25f21479 arm64: dts: qcom: sc7280: add TRNG node
00e1b06bb47a arm64: dts: qcom: sa8775p: add TRNG node
ac7c5d2655a7 arm64: dts: qcom: sm8450: add TRNG node
0087dcd6513a arm64: dts: qcom: sm8550: add TRNG node

git-subtree-dir: dts/upstream
git-subtree-split: b35b9bd1d4eed2acf8bc38ec5b1b6eef6261b4f0

29 files changed, 3570 insertions, 0 deletions

diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h
index f7248348a45..51e0f605941 100644
--- a/include/dt-bindings/arm/qcom,ids.h
+++ b/include/dt-bindings/arm/qcom,ids.h
@@ -255,6 +255,7 @@
 #define QCOM_ID_SA8775P			534
 #define QCOM_ID_QRU1000			539
 #define QCOM_ID_QDU1000			545
+#define QCOM_ID_SM8650			557
 #define QCOM_ID_SM4450			568
 #define QCOM_ID_QDU1010			587
 #define QCOM_ID_QRU1032			588
diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h
index 387767f4e29..fd09819da2e 100644
--- a/include/dt-bindings/clock/g12a-clkc.h
+++ b/include/dt-bindings/clock/g12a-clkc.h
@@ -279,5 +279,13 @@
 #define CLKID_MIPI_DSI_PXCLK_DIV		268
 #define CLKID_MIPI_DSI_PXCLK_SEL		269
 #define CLKID_MIPI_DSI_PXCLK			270
+#define CLKID_CTS_ENCL				271
+#define CLKID_CTS_ENCL_SEL			272
+#define CLKID_MIPI_ISP_DIV			273
+#define CLKID_MIPI_ISP_SEL			274
+#define CLKID_MIPI_ISP				275
+#define CLKID_MIPI_ISP_GATE			276
+#define CLKID_MIPI_ISP_CSI_PHY0			277
+#define CLKID_MIPI_ISP_CSI_PHY1			278
 
 #endif /* __G12A_CLKC_H */
diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h
new file mode 100644
index 00000000000..21adec22387
--- /dev/null
+++ b/include/dt-bindings/clock/google,gs101.h
@@ -0,0 +1,392 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2023 Linaro Ltd.
+ * Author: Peter Griffin <peter.griffin@linaro.org>
+ *
+ * Device Tree binding constants for Google gs101 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_H
+#define _DT_BINDINGS_CLOCK_GOOGLE_GS101_H
+
+/* CMU_TOP PLL */
+#define CLK_FOUT_SHARED0_PLL		1
+#define CLK_FOUT_SHARED1_PLL		2
+#define CLK_FOUT_SHARED2_PLL		3
+#define CLK_FOUT_SHARED3_PLL		4
+#define CLK_FOUT_SPARE_PLL		5
+
+/* CMU_TOP MUX */
+#define CLK_MOUT_PLL_SHARED0		6
+#define CLK_MOUT_PLL_SHARED1		7
+#define CLK_MOUT_PLL_SHARED2		8
+#define CLK_MOUT_PLL_SHARED3		9
+#define CLK_MOUT_PLL_SPARE		10
+#define CLK_MOUT_CMU_BO_BUS		11
+#define CLK_MOUT_CMU_BUS0_BUS		12
+#define CLK_MOUT_CMU_BUS1_BUS		13
+#define CLK_MOUT_CMU_BUS2_BUS		14
+#define CLK_MOUT_CMU_CIS_CLK0		15
+#define CLK_MOUT_CMU_CIS_CLK1		16
+#define CLK_MOUT_CMU_CIS_CLK2		17
+#define CLK_MOUT_CMU_CIS_CLK3		18
+#define CLK_MOUT_CMU_CIS_CLK4		19
+#define CLK_MOUT_CMU_CIS_CLK5		20
+#define CLK_MOUT_CMU_CIS_CLK6		21
+#define CLK_MOUT_CMU_CIS_CLK7		22
+#define CLK_MOUT_CMU_CMU_BOOST		23
+#define CLK_MOUT_CMU_BOOST_OPTION1	24
+#define CLK_MOUT_CMU_CORE_BUS		25
+#define CLK_MOUT_CMU_CPUCL0_DBG		26
+#define CLK_MOUT_CMU_CPUCL0_SWITCH	27
+#define CLK_MOUT_CMU_CPUCL1_SWITCH	28
+#define CLK_MOUT_CMU_CPUCL2_SWITCH	29
+#define CLK_MOUT_CMU_CSIS_BUS		30
+#define CLK_MOUT_CMU_DISP_BUS		31
+#define CLK_MOUT_CMU_DNS_BUS		32
+#define CLK_MOUT_CMU_DPU_BUS		33
+#define CLK_MOUT_CMU_EH_BUS		34
+#define CLK_MOUT_CMU_G2D_G2D		35
+#define CLK_MOUT_CMU_G2D_MSCL		36
+#define CLK_MOUT_CMU_G3AA_G3AA		37
+#define CLK_MOUT_CMU_G3D_BUSD		38
+#define CLK_MOUT_CMU_G3D_GLB		39
+#define CLK_MOUT_CMU_G3D_SWITCH		40
+#define CLK_MOUT_CMU_GDC_GDC0		41
+#define CLK_MOUT_CMU_GDC_GDC1		42
+#define CLK_MOUT_CMU_GDC_SCSC		43
+#define CLK_MOUT_CMU_HPM		44
+#define CLK_MOUT_CMU_HSI0_BUS		45
+#define CLK_MOUT_CMU_HSI0_DPGTC		46
+#define CLK_MOUT_CMU_HSI0_USB31DRD	47
+#define CLK_MOUT_CMU_HSI0_USBDPDBG	48
+#define CLK_MOUT_CMU_HSI1_BUS		49
+#define CLK_MOUT_CMU_HSI1_PCIE		50
+#define CLK_MOUT_CMU_HSI2_BUS		51
+#define CLK_MOUT_CMU_HSI2_MMC_CARD	52
+#define CLK_MOUT_CMU_HSI2_PCIE		53
+#define CLK_MOUT_CMU_HSI2_UFS_EMBD	54
+#define CLK_MOUT_CMU_IPP_BUS		55
+#define CLK_MOUT_CMU_ITP_BUS		56
+#define CLK_MOUT_CMU_MCSC_ITSC		57
+#define CLK_MOUT_CMU_MCSC_MCSC		58
+#define CLK_MOUT_CMU_MFC_MFC		59
+#define CLK_MOUT_CMU_MIF_BUSP		60
+#define CLK_MOUT_CMU_MIF_SWITCH		61
+#define CLK_MOUT_CMU_MISC_BUS		62
+#define CLK_MOUT_CMU_MISC_SSS		63
+#define CLK_MOUT_CMU_PDP_BUS		64
+#define CLK_MOUT_CMU_PDP_VRA		65
+#define CLK_MOUT_CMU_PERIC0_BUS		66
+#define CLK_MOUT_CMU_PERIC0_IP		67
+#define CLK_MOUT_CMU_PERIC1_BUS		68
+#define CLK_MOUT_CMU_PERIC1_IP		69
+#define CLK_MOUT_CMU_TNR_BUS		70
+#define CLK_MOUT_CMU_TOP_BOOST_OPTION1	71
+#define CLK_MOUT_CMU_TOP_CMUREF		72
+#define CLK_MOUT_CMU_TPU_BUS		73
+#define CLK_MOUT_CMU_TPU_TPU		74
+#define CLK_MOUT_CMU_TPU_TPUCTL		75
+#define CLK_MOUT_CMU_TPU_UART		76
+#define CLK_MOUT_CMU_CMUREF		77
+
+/* CMU_TOP Dividers */
+#define CLK_DOUT_CMU_BO_BUS		78
+#define CLK_DOUT_CMU_BUS0_BUS		79
+#define CLK_DOUT_CMU_BUS1_BUS		80
+#define CLK_DOUT_CMU_BUS2_BUS		81
+#define CLK_DOUT_CMU_CIS_CLK0		82
+#define CLK_DOUT_CMU_CIS_CLK1		83
+#define CLK_DOUT_CMU_CIS_CLK2		84
+#define CLK_DOUT_CMU_CIS_CLK3		85
+#define CLK_DOUT_CMU_CIS_CLK4		86
+#define CLK_DOUT_CMU_CIS_CLK5		87
+#define CLK_DOUT_CMU_CIS_CLK6		88
+#define CLK_DOUT_CMU_CIS_CLK7		89
+#define CLK_DOUT_CMU_CORE_BUS		90
+#define CLK_DOUT_CMU_CPUCL0_DBG		91
+#define CLK_DOUT_CMU_CPUCL0_SWITCH	92
+#define CLK_DOUT_CMU_CPUCL1_SWITCH	93
+#define CLK_DOUT_CMU_CPUCL2_SWITCH	94
+#define CLK_DOUT_CMU_CSIS_BUS		95
+#define CLK_DOUT_CMU_DISP_BUS		96
+#define CLK_DOUT_CMU_DNS_BUS		97
+#define CLK_DOUT_CMU_DPU_BUS		98
+#define CLK_DOUT_CMU_EH_BUS		99
+#define CLK_DOUT_CMU_G2D_G2D		100
+#define CLK_DOUT_CMU_G2D_MSCL		101
+#define CLK_DOUT_CMU_G3AA_G3AA		102
+#define CLK_DOUT_CMU_G3D_BUSD		103
+#define CLK_DOUT_CMU_G3D_GLB		104
+#define CLK_DOUT_CMU_G3D_SWITCH		105
+#define CLK_DOUT_CMU_GDC_GDC0		106
+#define CLK_DOUT_CMU_GDC_GDC1		107
+#define CLK_DOUT_CMU_GDC_SCSC		108
+#define CLK_DOUT_CMU_CMU_HPM		109
+#define CLK_DOUT_CMU_HSI0_BUS		110
+#define CLK_DOUT_CMU_HSI0_DPGTC		111
+#define CLK_DOUT_CMU_HSI0_USB31DRD	112
+#define CLK_DOUT_CMU_HSI0_USBDPDBG	113
+#define CLK_DOUT_CMU_HSI1_BUS		114
+#define CLK_DOUT_CMU_HSI1_PCIE		115
+#define CLK_DOUT_CMU_HSI2_BUS		116
+#define CLK_DOUT_CMU_HSI2_MMC_CARD	117
+#define CLK_DOUT_CMU_HSI2_PCIE		118
+#define CLK_DOUT_CMU_HSI2_UFS_EMBD	119
+#define CLK_DOUT_CMU_IPP_BUS		120
+#define CLK_DOUT_CMU_ITP_BUS		121
+#define CLK_DOUT_CMU_MCSC_ITSC		122
+#define CLK_DOUT_CMU_MCSC_MCSC		123
+#define CLK_DOUT_CMU_MFC_MFC		124
+#define CLK_DOUT_CMU_MIF_BUSP		125
+#define CLK_DOUT_CMU_MISC_BUS		126
+#define CLK_DOUT_CMU_MISC_SSS		127
+#define CLK_DOUT_CMU_OTP		128
+#define CLK_DOUT_CMU_PDP_BUS		129
+#define CLK_DOUT_CMU_PDP_VRA		130
+#define CLK_DOUT_CMU_PERIC0_BUS		131
+#define CLK_DOUT_CMU_PERIC0_IP		132
+#define CLK_DOUT_CMU_PERIC1_BUS		133
+#define CLK_DOUT_CMU_PERIC1_IP		134
+#define CLK_DOUT_CMU_TNR_BUS		135
+#define CLK_DOUT_CMU_TPU_BUS		136
+#define CLK_DOUT_CMU_TPU_TPU		137
+#define CLK_DOUT_CMU_TPU_TPUCTL		138
+#define CLK_DOUT_CMU_TPU_UART		139
+#define CLK_DOUT_CMU_CMU_BOOST		140
+#define CLK_DOUT_CMU_CMU_CMUREF		141
+#define CLK_DOUT_CMU_SHARED0_DIV2	142
+#define CLK_DOUT_CMU_SHARED0_DIV3	143
+#define CLK_DOUT_CMU_SHARED0_DIV4	144
+#define CLK_DOUT_CMU_SHARED0_DIV5	145
+#define CLK_DOUT_CMU_SHARED1_DIV2	146
+#define CLK_DOUT_CMU_SHARED1_DIV3	147
+#define CLK_DOUT_CMU_SHARED1_DIV4	148
+#define CLK_DOUT_CMU_SHARED2_DIV2	149
+#define CLK_DOUT_CMU_SHARED3_DIV2	150
+
+/* CMU_TOP Gates */
+#define CLK_GOUT_CMU_BUS0_BOOST		151
+#define CLK_GOUT_CMU_BUS1_BOOST		152
+#define CLK_GOUT_CMU_BUS2_BOOST		153
+#define CLK_GOUT_CMU_CORE_BOOST		154
+#define CLK_GOUT_CMU_CPUCL0_BOOST	155
+#define CLK_GOUT_CMU_CPUCL1_BOOST	156
+#define CLK_GOUT_CMU_CPUCL2_BOOST	157
+#define CLK_GOUT_CMU_MIF_BOOST		158
+#define CLK_GOUT_CMU_MIF_SWITCH		159
+#define CLK_GOUT_CMU_BO_BUS		160
+#define CLK_GOUT_CMU_BUS0_BUS		161
+#define CLK_GOUT_CMU_BUS1_BUS		162
+#define CLK_GOUT_CMU_BUS2_BUS		163
+#define CLK_GOUT_CMU_CIS_CLK0		164
+#define CLK_GOUT_CMU_CIS_CLK1		165
+#define CLK_GOUT_CMU_CIS_CLK2		166
+#define CLK_GOUT_CMU_CIS_CLK3		167
+#define CLK_GOUT_CMU_CIS_CLK4		168
+#define CLK_GOUT_CMU_CIS_CLK5		169
+#define CLK_GOUT_CMU_CIS_CLK6		170
+#define CLK_GOUT_CMU_CIS_CLK7		171
+#define CLK_GOUT_CMU_CMU_BOOST		172
+#define CLK_GOUT_CMU_CORE_BUS		173
+#define CLK_GOUT_CMU_CPUCL0_DBG		174
+#define CLK_GOUT_CMU_CPUCL0_SWITCH	175
+#define CLK_GOUT_CMU_CPUCL1_SWITCH	176
+#define CLK_GOUT_CMU_CPUCL2_SWITCH	177
+#define CLK_GOUT_CMU_CSIS_BUS		178
+#define CLK_GOUT_CMU_DISP_BUS		179
+#define CLK_GOUT_CMU_DNS_BUS		180
+#define CLK_GOUT_CMU_DPU_BUS		181
+#define CLK_GOUT_CMU_EH_BUS		182
+#define CLK_GOUT_CMU_G2D_G2D		183
+#define CLK_GOUT_CMU_G2D_MSCL		184
+#define CLK_GOUT_CMU_G3AA_G3AA		185
+#define CLK_GOUT_CMU_G3D_BUSD		186
+#define CLK_GOUT_CMU_G3D_GLB		187
+#define CLK_GOUT_CMU_G3D_SWITCH		188
+#define CLK_GOUT_CMU_GDC_GDC0		189
+#define CLK_GOUT_CMU_GDC_GDC1		190
+#define CLK_GOUT_CMU_GDC_SCSC		191
+#define CLK_GOUT_CMU_HPM		192
+#define CLK_GOUT_CMU_HSI0_BUS		193
+#define CLK_GOUT_CMU_HSI0_DPGTC		194
+#define CLK_GOUT_CMU_HSI0_USB31DRD	195
+#define CLK_GOUT_CMU_HSI0_USBDPDBG	196
+#define CLK_GOUT_CMU_HSI1_BUS		197
+#define CLK_GOUT_CMU_HSI1_PCIE		198
+#define CLK_GOUT_CMU_HSI2_BUS		199
+#define CLK_GOUT_CMU_HSI2_MMC_CARD	200
+#define CLK_GOUT_CMU_HSI2_PCIE		201
+#define CLK_GOUT_CMU_HSI2_UFS_EMBD	202
+#define CLK_GOUT_CMU_IPP_BUS		203
+#define CLK_GOUT_CMU_ITP_BUS		204
+#define CLK_GOUT_CMU_MCSC_ITSC		205
+#define CLK_GOUT_CMU_MCSC_MCSC		206
+#define CLK_GOUT_CMU_MFC_MFC		207
+#define CLK_GOUT_CMU_MIF_BUSP		208
+#define CLK_GOUT_CMU_MISC_BUS		209
+#define CLK_GOUT_CMU_MISC_SSS		210
+#define CLK_GOUT_CMU_PDP_BUS		211
+#define CLK_GOUT_CMU_PDP_VRA		212
+#define CLK_GOUT_CMU_G3AA		213
+#define CLK_GOUT_CMU_PERIC0_BUS		214
+#define CLK_GOUT_CMU_PERIC0_IP		215
+#define CLK_GOUT_CMU_PERIC1_BUS		216
+#define CLK_GOUT_CMU_PERIC1_IP		217
+#define CLK_GOUT_CMU_TNR_BUS		218
+#define CLK_GOUT_CMU_TOP_CMUREF		219
+#define CLK_GOUT_CMU_TPU_BUS		220
+#define CLK_GOUT_CMU_TPU_TPU		221
+#define CLK_GOUT_CMU_TPU_TPUCTL		222
+#define CLK_GOUT_CMU_TPU_UART		223
+
+/* CMU_APM */
+#define CLK_MOUT_APM_FUNC				1
+#define CLK_MOUT_APM_FUNCSRC				2
+#define CLK_DOUT_APM_BOOST				3
+#define CLK_DOUT_APM_USI0_UART				4
+#define CLK_DOUT_APM_USI0_USI				5
+#define CLK_DOUT_APM_USI1_UART				6
+#define CLK_GOUT_APM_APM_CMU_APM_PCLK			7
+#define CLK_GOUT_BUS0_BOOST_OPTION1			8
+#define CLK_GOUT_CMU_BOOST_OPTION1			9
+#define CLK_GOUT_CORE_BOOST_OPTION1			10
+#define CLK_GOUT_APM_FUNC				11
+#define CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK		12
+#define CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK		13
+#define CLK_GOUT_APM_APBIF_PMU_ALIVE_PCLK		14
+#define CLK_GOUT_APM_APBIF_RTC_PCLK			15
+#define CLK_GOUT_APM_APBIF_TRTC_PCLK			16
+#define CLK_GOUT_APM_APM_USI0_UART_IPCLK		17
+#define CLK_GOUT_APM_APM_USI0_UART_PCLK			18
+#define CLK_GOUT_APM_APM_USI0_USI_IPCLK			19
+#define CLK_GOUT_APM_APM_USI0_USI_PCLK			20
+#define CLK_GOUT_APM_APM_USI1_UART_IPCLK		21
+#define CLK_GOUT_APM_APM_USI1_UART_PCLK			22
+#define CLK_GOUT_APM_D_TZPC_APM_PCLK			23
+#define CLK_GOUT_APM_GPC_APM_PCLK			24
+#define CLK_GOUT_APM_GREBEINTEGRATION_HCLK		25
+#define CLK_GOUT_APM_INTMEM_ACLK			26
+#define CLK_GOUT_APM_INTMEM_PCLK			27
+#define CLK_GOUT_APM_LHM_AXI_G_SWD_I_CLK		28
+#define CLK_GOUT_APM_LHM_AXI_P_AOCAPM_I_CLK		29
+#define CLK_GOUT_APM_LHM_AXI_P_APM_I_CLK		30
+#define CLK_GOUT_APM_LHS_AXI_D_APM_I_CLK		31
+#define CLK_GOUT_APM_LHS_AXI_G_DBGCORE_I_CLK		32
+#define CLK_GOUT_APM_LHS_AXI_G_SCAN2DRAM_I_CLK		33
+#define CLK_GOUT_APM_MAILBOX_APM_AOC_PCLK		34
+#define CLK_GOUT_APM_MAILBOX_APM_AP_PCLK		35
+#define CLK_GOUT_APM_MAILBOX_APM_GSA_PCLK		36
+#define CLK_GOUT_APM_MAILBOX_APM_SWD_PCLK		37
+#define CLK_GOUT_APM_MAILBOX_APM_TPU_PCLK		38
+#define CLK_GOUT_APM_MAILBOX_AP_AOC_PCLK		39
+#define CLK_GOUT_APM_MAILBOX_AP_DBGCORE_PCLK		40
+#define CLK_GOUT_APM_PMU_INTR_GEN_PCLK			41
+#define CLK_GOUT_APM_ROM_CRC32_HOST_ACLK		42
+#define CLK_GOUT_APM_ROM_CRC32_HOST_PCLK		43
+#define CLK_GOUT_APM_CLK_APM_BUS_CLK			44
+#define CLK_GOUT_APM_CLK_APM_USI0_UART_CLK		45
+#define CLK_GOUT_APM_CLK_APM_USI0_USI_CLK		46
+#define CLK_GOUT_APM_CLK_APM_USI1_UART_CLK		47
+#define CLK_GOUT_APM_SPEEDY_APM_PCLK			48
+#define CLK_GOUT_APM_SPEEDY_SUB_APM_PCLK		49
+#define CLK_GOUT_APM_SSMT_D_APM_ACLK			50
+#define CLK_GOUT_APM_SSMT_D_APM_PCLK			51
+#define CLK_GOUT_APM_SSMT_G_DBGCORE_ACLK		52
+#define CLK_GOUT_APM_SSMT_G_DBGCORE_PCLK		53
+#define CLK_GOUT_APM_SS_DBGCORE_SS_DBGCORE_HCLK		54
+#define CLK_GOUT_APM_SYSMMU_D_APM_CLK_S2		55
+#define CLK_GOUT_APM_SYSREG_APM_PCLK			56
+#define CLK_GOUT_APM_UASC_APM_ACLK			57
+#define CLK_GOUT_APM_UASC_APM_PCLK			58
+#define CLK_GOUT_APM_UASC_DBGCORE_ACLK			59
+#define CLK_GOUT_APM_UASC_DBGCORE_PCLK			60
+#define CLK_GOUT_APM_UASC_G_SWD_ACLK			61
+#define CLK_GOUT_APM_UASC_G_SWD_PCLK			62
+#define CLK_GOUT_APM_UASC_P_AOCAPM_ACLK			63
+#define CLK_GOUT_APM_UASC_P_AOCAPM_PCLK			64
+#define CLK_GOUT_APM_UASC_P_APM_ACLK			65
+#define CLK_GOUT_APM_UASC_P_APM_PCLK			66
+#define CLK_GOUT_APM_WDT_APM_PCLK			67
+#define CLK_GOUT_APM_XIU_DP_APM_ACLK			68
+#define CLK_APM_PLL_DIV2_APM				69
+#define CLK_APM_PLL_DIV4_APM				70
+#define CLK_APM_PLL_DIV16_APM				71
+
+/* CMU_MISC */
+#define CLK_MOUT_MISC_BUS_USER				1
+#define CLK_MOUT_MISC_SSS_USER				2
+#define CLK_MOUT_MISC_GIC				3
+#define CLK_DOUT_MISC_BUSP				4
+#define CLK_DOUT_MISC_GIC				5
+#define CLK_GOUT_MISC_MISC_CMU_MISC_PCLK		6
+#define CLK_GOUT_MISC_OTP_CON_BIRA_I_OSCCLK		7
+#define CLK_GOUT_MISC_OTP_CON_BISR_I_OSCCLK		8
+#define CLK_GOUT_MISC_OTP_CON_TOP_I_OSCCLK		9
+#define CLK_GOUT_MISC_CLK_MISC_OSCCLK_CLK		10
+#define CLK_GOUT_MISC_ADM_AHB_SSS_HCLKM			11
+#define CLK_GOUT_MISC_AD_APB_DIT_PCLKM			12
+#define CLK_GOUT_MISC_AD_APB_PUF_PCLKM			13
+#define CLK_GOUT_MISC_DIT_ICLKL2A			14
+#define CLK_GOUT_MISC_D_TZPC_MISC_PCLK			15
+#define CLK_GOUT_MISC_GIC_GICCLK			16
+#define CLK_GOUT_MISC_GPC_MISC_PCLK			17
+#define CLK_GOUT_MISC_LHM_AST_ICC_CPUGIC_I_CLK		18
+#define CLK_GOUT_MISC_LHM_AXI_D_SSS_I_CLK		19
+#define CLK_GOUT_MISC_LHM_AXI_P_GIC_I_CLK		20
+#define CLK_GOUT_MISC_LHM_AXI_P_MISC_I_CLK		21
+#define CLK_GOUT_MISC_LHS_ACEL_D_MISC_I_CLK		22
+#define CLK_GOUT_MISC_LHS_AST_IRI_GICCPU_I_CLK		23
+#define CLK_GOUT_MISC_LHS_AXI_D_SSS_I_CLK		24
+#define CLK_GOUT_MISC_MCT_PCLK				25
+#define CLK_GOUT_MISC_OTP_CON_BIRA_PCLK			26
+#define CLK_GOUT_MISC_OTP_CON_BISR_PCLK			27
+#define CLK_GOUT_MISC_OTP_CON_TOP_PCLK			28
+#define CLK_GOUT_MISC_PDMA_ACLK				29
+#define CLK_GOUT_MISC_PPMU_DMA_ACLK			30
+#define CLK_GOUT_MISC_PPMU_MISC_ACLK			31
+#define CLK_GOUT_MISC_PPMU_MISC_PCLK			32
+#define CLK_GOUT_MISC_PUF_I_CLK				33
+#define CLK_GOUT_MISC_QE_DIT_ACLK			34
+#define CLK_GOUT_MISC_QE_DIT_PCLK			35
+#define CLK_GOUT_MISC_QE_PDMA_ACLK			36
+#define CLK_GOUT_MISC_QE_PDMA_PCLK			37
+#define CLK_GOUT_MISC_QE_PPMU_DMA_ACLK			38
+#define CLK_GOUT_MISC_QE_PPMU_DMA_PCLK			39
+#define CLK_GOUT_MISC_QE_RTIC_ACLK			40
+#define CLK_GOUT_MISC_QE_RTIC_PCLK			41
+#define CLK_GOUT_MISC_QE_SPDMA_ACLK			42
+#define CLK_GOUT_MISC_QE_SPDMA_PCLK			43
+#define CLK_GOUT_MISC_QE_SSS_ACLK			44
+#define CLK_GOUT_MISC_QE_SSS_PCLK			45
+#define CLK_GOUT_MISC_CLK_MISC_BUSD_CLK			46
+#define CLK_GOUT_MISC_CLK_MISC_BUSP_CLK			47
+#define CLK_GOUT_MISC_CLK_MISC_GIC_CLK			48
+#define CLK_GOUT_MISC_CLK_MISC_SSS_CLK			49
+#define CLK_GOUT_MISC_RTIC_I_ACLK			50
+#define CLK_GOUT_MISC_RTIC_I_PCLK			51
+#define CLK_GOUT_MISC_SPDMA_ACLK			52
+#define CLK_GOUT_MISC_SSMT_DIT_ACLK			53
+#define CLK_GOUT_MISC_SSMT_DIT_PCLK			54
+#define CLK_GOUT_MISC_SSMT_PDMA_ACLK			55
+#define CLK_GOUT_MISC_SSMT_PDMA_PCLK			56
+#define CLK_GOUT_MISC_SSMT_PPMU_DMA_ACLK		57
+#define CLK_GOUT_MISC_SSMT_PPMU_DMA_PCLK		58
+#define CLK_GOUT_MISC_SSMT_RTIC_ACLK			59
+#define CLK_GOUT_MISC_SSMT_RTIC_PCLK			60
+#define CLK_GOUT_MISC_SSMT_SPDMA_ACLK			61
+#define CLK_GOUT_MISC_SSMT_SPDMA_PCLK			62
+#define CLK_GOUT_MISC_SSMT_SSS_ACLK			63
+#define CLK_GOUT_MISC_SSMT_SSS_PCLK			64
+#define CLK_GOUT_MISC_SSS_I_ACLK			65
+#define CLK_GOUT_MISC_SSS_I_PCLK			66
+#define CLK_GOUT_MISC_SYSMMU_MISC_CLK_S2		67
+#define CLK_GOUT_MISC_SYSMMU_SSS_CLK_S1			68
+#define CLK_GOUT_MISC_SYSREG_MISC_PCLK			69
+#define CLK_GOUT_MISC_TMU_SUB_PCLK			70
+#define CLK_GOUT_MISC_TMU_TOP_PCLK			71
+#define CLK_GOUT_MISC_WDT_CLUSTER0_PCLK			72
+#define CLK_GOUT_MISC_WDT_CLUSTER1_PCLK			73
+#define CLK_GOUT_MISC_XIU_D_MISC_ACLK			74
+
+#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */
diff --git a/include/dt-bindings/clock/mediatek,mt7988-clk.h b/include/dt-bindings/clock/mediatek,mt7988-clk.h
new file mode 100644
index 00000000000..63376e40f14
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mt7988-clk.h
@@ -0,0 +1,280 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT7988_H
+#define _DT_BINDINGS_CLK_MT7988_H
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_NETSYSPLL			0
+#define CLK_APMIXED_MPLL			1
+#define CLK_APMIXED_MMPLL			2
+#define CLK_APMIXED_APLL2			3
+#define CLK_APMIXED_NET1PLL			4
+#define CLK_APMIXED_NET2PLL			5
+#define CLK_APMIXED_WEDMCUPLL			6
+#define CLK_APMIXED_SGMPLL			7
+#define CLK_APMIXED_ARM_B			8
+#define CLK_APMIXED_CCIPLL2_B			9
+#define CLK_APMIXED_USXGMIIPLL			10
+#define CLK_APMIXED_MSDCPLL			11
+
+/* TOPCKGEN */
+
+#define CLK_TOP_XTAL				0
+#define CLK_TOP_XTAL_D2				1
+#define CLK_TOP_RTC_32K				2
+#define CLK_TOP_RTC_32P7K			3
+#define CLK_TOP_MPLL_D2				4
+#define CLK_TOP_MPLL_D3_D2			5
+#define CLK_TOP_MPLL_D4				6
+#define CLK_TOP_MPLL_D8				7
+#define CLK_TOP_MPLL_D8_D2			8
+#define CLK_TOP_MMPLL_D2			9
+#define CLK_TOP_MMPLL_D3_D5			10
+#define CLK_TOP_MMPLL_D4			11
+#define CLK_TOP_MMPLL_D6_D2			12
+#define CLK_TOP_MMPLL_D8			13
+#define CLK_TOP_APLL2_D4			14
+#define CLK_TOP_NET1PLL_D4			15
+#define CLK_TOP_NET1PLL_D5			16
+#define CLK_TOP_NET1PLL_D5_D2			17
+#define CLK_TOP_NET1PLL_D5_D4			18
+#define CLK_TOP_NET1PLL_D8			19
+#define CLK_TOP_NET1PLL_D8_D2			20
+#define CLK_TOP_NET1PLL_D8_D4			21
+#define CLK_TOP_NET1PLL_D8_D8			22
+#define CLK_TOP_NET1PLL_D8_D16			23
+#define CLK_TOP_NET2PLL_D2			24
+#define CLK_TOP_NET2PLL_D4			25
+#define CLK_TOP_NET2PLL_D4_D4			26
+#define CLK_TOP_NET2PLL_D4_D8			27
+#define CLK_TOP_NET2PLL_D6			28
+#define CLK_TOP_NET2PLL_D8			29
+#define CLK_TOP_NETSYS_SEL			30
+#define CLK_TOP_NETSYS_500M_SEL			31
+#define CLK_TOP_NETSYS_2X_SEL			32
+#define CLK_TOP_NETSYS_GSW_SEL			33
+#define CLK_TOP_ETH_GMII_SEL			34
+#define CLK_TOP_NETSYS_MCU_SEL			35
+#define CLK_TOP_NETSYS_PAO_2X_SEL		36
+#define CLK_TOP_EIP197_SEL			37
+#define CLK_TOP_AXI_INFRA_SEL			38
+#define CLK_TOP_UART_SEL			39
+#define CLK_TOP_EMMC_250M_SEL			40
+#define CLK_TOP_EMMC_400M_SEL			41
+#define CLK_TOP_SPI_SEL				42
+#define CLK_TOP_SPIM_MST_SEL			43
+#define CLK_TOP_NFI1X_SEL			44
+#define CLK_TOP_SPINFI_SEL			45
+#define CLK_TOP_PWM_SEL				46
+#define CLK_TOP_I2C_SEL				47
+#define CLK_TOP_PCIE_MBIST_250M_SEL		48
+#define CLK_TOP_PEXTP_TL_SEL			49
+#define CLK_TOP_PEXTP_TL_P1_SEL			50
+#define CLK_TOP_PEXTP_TL_P2_SEL			51
+#define CLK_TOP_PEXTP_TL_P3_SEL			52
+#define CLK_TOP_USB_SYS_SEL			53
+#define CLK_TOP_USB_SYS_P1_SEL			54
+#define CLK_TOP_USB_XHCI_SEL			55
+#define CLK_TOP_USB_XHCI_P1_SEL			56
+#define CLK_TOP_USB_FRMCNT_SEL			57
+#define CLK_TOP_USB_FRMCNT_P1_SEL		58
+#define CLK_TOP_AUD_SEL				59
+#define CLK_TOP_A1SYS_SEL			60
+#define CLK_TOP_AUD_L_SEL			61
+#define CLK_TOP_A_TUNER_SEL			62
+#define CLK_TOP_SSPXTP_SEL			63
+#define CLK_TOP_USB_PHY_SEL			64
+#define CLK_TOP_USXGMII_SBUS_0_SEL		65
+#define CLK_TOP_USXGMII_SBUS_1_SEL		66
+#define CLK_TOP_SGM_0_SEL			67
+#define CLK_TOP_SGM_SBUS_0_SEL			68
+#define CLK_TOP_SGM_1_SEL			69
+#define CLK_TOP_SGM_SBUS_1_SEL			70
+#define CLK_TOP_XFI_PHY_0_XTAL_SEL		71
+#define CLK_TOP_XFI_PHY_1_XTAL_SEL		72
+#define CLK_TOP_SYSAXI_SEL			73
+#define CLK_TOP_SYSAPB_SEL			74
+#define CLK_TOP_ETH_REFCK_50M_SEL		75
+#define CLK_TOP_ETH_SYS_200M_SEL		76
+#define CLK_TOP_ETH_SYS_SEL			77
+#define CLK_TOP_ETH_XGMII_SEL			78
+#define CLK_TOP_BUS_TOPS_SEL			79
+#define CLK_TOP_NPU_TOPS_SEL			80
+#define CLK_TOP_DRAMC_SEL			81
+#define CLK_TOP_DRAMC_MD32_SEL			82
+#define CLK_TOP_INFRA_F26M_SEL			83
+#define CLK_TOP_PEXTP_P0_SEL			84
+#define CLK_TOP_PEXTP_P1_SEL			85
+#define CLK_TOP_PEXTP_P2_SEL			86
+#define CLK_TOP_PEXTP_P3_SEL			87
+#define CLK_TOP_DA_XTP_GLB_P0_SEL		88
+#define CLK_TOP_DA_XTP_GLB_P1_SEL		89
+#define CLK_TOP_DA_XTP_GLB_P2_SEL		90
+#define CLK_TOP_DA_XTP_GLB_P3_SEL		91
+#define CLK_TOP_CKM_SEL				92
+#define CLK_TOP_DA_SEL				93
+#define CLK_TOP_PEXTP_SEL			94
+#define CLK_TOP_TOPS_P2_26M_SEL			95
+#define CLK_TOP_MCUSYS_BACKUP_625M_SEL		96
+#define CLK_TOP_NETSYS_SYNC_250M_SEL		97
+#define CLK_TOP_MACSEC_SEL			98
+#define CLK_TOP_NETSYS_TOPS_400M_SEL		99
+#define CLK_TOP_NETSYS_PPEFB_250M_SEL		100
+#define CLK_TOP_NETSYS_WARP_SEL			101
+#define CLK_TOP_ETH_MII_SEL			102
+#define CLK_TOP_NPU_SEL				103
+#define CLK_TOP_AUD_I2S_M			104
+
+/* MCUSYS */
+
+#define CLK_MCU_BUS_DIV_SEL			0
+#define CLK_MCU_ARM_DIV_SEL			1
+
+/* INFRACFG_AO */
+
+#define CLK_INFRA_MUX_UART0_SEL			0
+#define CLK_INFRA_MUX_UART1_SEL			1
+#define CLK_INFRA_MUX_UART2_SEL			2
+#define CLK_INFRA_MUX_SPI0_SEL			3
+#define CLK_INFRA_MUX_SPI1_SEL			4
+#define CLK_INFRA_MUX_SPI2_SEL			5
+#define CLK_INFRA_PWM_SEL			6
+#define CLK_INFRA_PWM_CK1_SEL			7
+#define CLK_INFRA_PWM_CK2_SEL			8
+#define CLK_INFRA_PWM_CK3_SEL			9
+#define CLK_INFRA_PWM_CK4_SEL			10
+#define CLK_INFRA_PWM_CK5_SEL			11
+#define CLK_INFRA_PWM_CK6_SEL			12
+#define CLK_INFRA_PWM_CK7_SEL			13
+#define CLK_INFRA_PWM_CK8_SEL			14
+#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL	15
+#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL	16
+#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL	17
+#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL	18
+
+/* INFRACFG */
+
+#define CLK_INFRA_PCIE_PERI_26M_CK_P0		19
+#define CLK_INFRA_PCIE_PERI_26M_CK_P1		20
+#define CLK_INFRA_PCIE_PERI_26M_CK_P2		21
+#define CLK_INFRA_PCIE_PERI_26M_CK_P3		22
+#define CLK_INFRA_66M_GPT_BCK			23
+#define CLK_INFRA_66M_PWM_HCK			24
+#define CLK_INFRA_66M_PWM_BCK			25
+#define CLK_INFRA_66M_PWM_CK1			26
+#define CLK_INFRA_66M_PWM_CK2			27
+#define CLK_INFRA_66M_PWM_CK3			28
+#define CLK_INFRA_66M_PWM_CK4			29
+#define CLK_INFRA_66M_PWM_CK5			30
+#define CLK_INFRA_66M_PWM_CK6			31
+#define CLK_INFRA_66M_PWM_CK7			32
+#define CLK_INFRA_66M_PWM_CK8			33
+#define CLK_INFRA_133M_CQDMA_BCK		34
+#define CLK_INFRA_66M_AUD_SLV_BCK		35
+#define CLK_INFRA_AUD_26M			36
+#define CLK_INFRA_AUD_L				37
+#define CLK_INFRA_AUD_AUD			38
+#define CLK_INFRA_AUD_EG2			39
+#define CLK_INFRA_DRAMC_F26M			40
+#define CLK_INFRA_133M_DBG_ACKM			41
+#define CLK_INFRA_66M_AP_DMA_BCK		42
+#define CLK_INFRA_66M_SEJ_BCK			43
+#define CLK_INFRA_PRE_CK_SEJ_F13M		44
+#define CLK_INFRA_26M_THERM_SYSTEM		45
+#define CLK_INFRA_I2C_BCK			46
+#define CLK_INFRA_52M_UART0_CK			47
+#define CLK_INFRA_52M_UART1_CK			48
+#define CLK_INFRA_52M_UART2_CK			49
+#define CLK_INFRA_NFI				50
+#define CLK_INFRA_SPINFI			51
+#define CLK_INFRA_66M_NFI_HCK			52
+#define CLK_INFRA_104M_SPI0			53
+#define CLK_INFRA_104M_SPI1			54
+#define CLK_INFRA_104M_SPI2_BCK			55
+#define CLK_INFRA_66M_SPI0_HCK			56
+#define CLK_INFRA_66M_SPI1_HCK			57
+#define CLK_INFRA_66M_SPI2_HCK			58
+#define CLK_INFRA_66M_FLASHIF_AXI		59
+#define CLK_INFRA_RTC				60
+#define CLK_INFRA_26M_ADC_BCK			61
+#define CLK_INFRA_RC_ADC			62
+#define CLK_INFRA_MSDC400			63
+#define CLK_INFRA_MSDC2_HCK			64
+#define CLK_INFRA_133M_MSDC_0_HCK		65
+#define CLK_INFRA_66M_MSDC_0_HCK		66
+#define CLK_INFRA_133M_CPUM_BCK			67
+#define CLK_INFRA_BIST2FPC			68
+#define CLK_INFRA_I2C_X16W_MCK_CK_P1		69
+#define CLK_INFRA_I2C_X16W_PCK_CK_P1		70
+#define CLK_INFRA_133M_USB_HCK			71
+#define CLK_INFRA_133M_USB_HCK_CK_P1		72
+#define CLK_INFRA_66M_USB_HCK			73
+#define CLK_INFRA_66M_USB_HCK_CK_P1		74
+#define CLK_INFRA_USB_SYS			75
+#define CLK_INFRA_USB_SYS_CK_P1			76
+#define CLK_INFRA_USB_REF			77
+#define CLK_INFRA_USB_CK_P1			78
+#define CLK_INFRA_USB_FRMCNT			79
+#define CLK_INFRA_USB_FRMCNT_CK_P1		80
+#define CLK_INFRA_USB_PIPE			81
+#define CLK_INFRA_USB_PIPE_CK_P1		82
+#define CLK_INFRA_USB_UTMI			83
+#define CLK_INFRA_USB_UTMI_CK_P1		84
+#define CLK_INFRA_USB_XHCI			85
+#define CLK_INFRA_USB_XHCI_CK_P1		86
+#define CLK_INFRA_PCIE_GFMUX_TL_P0		87
+#define CLK_INFRA_PCIE_GFMUX_TL_P1		88
+#define CLK_INFRA_PCIE_GFMUX_TL_P2		89
+#define CLK_INFRA_PCIE_GFMUX_TL_P3		90
+#define CLK_INFRA_PCIE_PIPE_P0			91
+#define CLK_INFRA_PCIE_PIPE_P1			92
+#define CLK_INFRA_PCIE_PIPE_P2			93
+#define CLK_INFRA_PCIE_PIPE_P3			94
+#define CLK_INFRA_133M_PCIE_CK_P0		95
+#define CLK_INFRA_133M_PCIE_CK_P1		96
+#define CLK_INFRA_133M_PCIE_CK_P2		97
+#define CLK_INFRA_133M_PCIE_CK_P3		98
+
+/* ETHDMA */
+
+#define CLK_ETHDMA_XGP1_EN			0
+#define CLK_ETHDMA_XGP2_EN			1
+#define CLK_ETHDMA_XGP3_EN			2
+#define CLK_ETHDMA_FE_EN			3
+#define CLK_ETHDMA_GP2_EN			4
+#define CLK_ETHDMA_GP1_EN			5
+#define CLK_ETHDMA_GP3_EN			6
+#define CLK_ETHDMA_ESW_EN			7
+#define CLK_ETHDMA_CRYPT0_EN			8
+#define CLK_ETHDMA_NR_CLK			9
+
+/* SGMIISYS_0 */
+
+#define CLK_SGM0_TX_EN				0
+#define CLK_SGM0_RX_EN				1
+#define CLK_SGMII0_NR_CLK			2
+
+/* SGMIISYS_1 */
+
+#define CLK_SGM1_TX_EN				0
+#define CLK_SGM1_RX_EN				1
+#define CLK_SGMII1_NR_CLK			2
+
+/* ETHWARP */
+
+#define CLK_ETHWARP_WOCPU2_EN			0
+#define CLK_ETHWARP_WOCPU1_EN			1
+#define CLK_ETHWARP_WOCPU0_EN			2
+#define CLK_ETHWARP_NR_CLK			3
+
+/* XFIPLL */
+#define CLK_XFIPLL_PLL				0
+#define CLK_XFIPLL_PLL_EN			1
+
+#endif /* _DT_BINDINGS_CLK_MT7988_H */
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8939.h b/include/dt-bindings/clock/qcom,gcc-msm8939.h
index 2d545ed0d35..9a9bc55b49a 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8939.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8939.h
@@ -193,6 +193,12 @@
 #define GCC_VENUS0_CORE1_VCODEC0_CLK		184
 #define GCC_OXILI_TIMER_CLK			185
 #define SYSTEM_MM_NOC_BFDCD_CLK_SRC		186
+#define CSI2_CLK_SRC				187
+#define GCC_CAMSS_CSI2_AHB_CLK			188
+#define GCC_CAMSS_CSI2_CLK			189
+#define GCC_CAMSS_CSI2PHY_CLK			190
+#define GCC_CAMSS_CSI2PIX_CLK			191
+#define GCC_CAMSS_CSI2RDI_CLK			192
 
 /* Indexes for GDSCs */
 #define BIMC_GDSC				0
diff --git a/include/dt-bindings/clock/qcom,qdu1000-ecpricc.h b/include/dt-bindings/clock/qcom,qdu1000-ecpricc.h
new file mode 100644
index 00000000000..731e404a2ce
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,qdu1000-ecpricc.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_ECPRI_CC_QDU1000_H
+#define _DT_BINDINGS_CLK_QCOM_ECPRI_CC_QDU1000_H
+
+/* ECPRI_CC clocks */
+#define ECPRI_CC_PLL0						0
+#define ECPRI_CC_PLL1						1
+#define ECPRI_CC_ECPRI_CG_CLK					2
+#define ECPRI_CC_ECPRI_CLK_SRC					3
+#define ECPRI_CC_ECPRI_DMA_CLK					4
+#define ECPRI_CC_ECPRI_DMA_CLK_SRC				5
+#define ECPRI_CC_ECPRI_DMA_NOC_CLK				6
+#define ECPRI_CC_ECPRI_FAST_CLK					7
+#define ECPRI_CC_ECPRI_FAST_CLK_SRC				8
+#define ECPRI_CC_ECPRI_FAST_DIV2_CLK				9
+#define ECPRI_CC_ECPRI_FAST_DIV2_CLK_SRC			10
+#define ECPRI_CC_ECPRI_FAST_DIV2_NOC_CLK			11
+#define ECPRI_CC_ECPRI_FR_CLK					12
+#define ECPRI_CC_ECPRI_ORAN_CLK_SRC				13
+#define ECPRI_CC_ECPRI_ORAN_DIV2_CLK				14
+#define ECPRI_CC_ETH_100G_C2C0_HM_FF_CLK_SRC			15
+#define ECPRI_CC_ETH_100G_C2C0_UDP_FIFO_CLK			16
+#define ECPRI_CC_ETH_100G_C2C1_UDP_FIFO_CLK			17
+#define ECPRI_CC_ETH_100G_C2C_0_HM_FF_0_CLK			18
+#define ECPRI_CC_ETH_100G_C2C_0_HM_FF_1_CLK			19
+#define ECPRI_CC_ETH_100G_C2C_HM_FF_0_DIV_CLK_SRC		20
+#define ECPRI_CC_ETH_100G_C2C_HM_FF_1_DIV_CLK_SRC		21
+#define ECPRI_CC_ETH_100G_C2C_HM_MACSEC_CLK			22
+#define ECPRI_CC_ETH_100G_C2C_HM_MACSEC_CLK_SRC			23
+#define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_0_CLK			24
+#define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_0_DIV_CLK_SRC		25
+#define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_1_CLK			26
+#define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_1_DIV_CLK_SRC		27
+#define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_CLK_SRC			28
+#define ECPRI_CC_ETH_100G_DBG_C2C_UDP_FIFO_CLK			29
+#define ECPRI_CC_ETH_100G_FH0_HM_FF_CLK_SRC			30
+#define ECPRI_CC_ETH_100G_FH0_MACSEC_CLK_SRC			31
+#define ECPRI_CC_ETH_100G_FH1_HM_FF_CLK_SRC			32
+#define ECPRI_CC_ETH_100G_FH1_MACSEC_CLK_SRC			33
+#define ECPRI_CC_ETH_100G_FH2_HM_FF_CLK_SRC			34
+#define ECPRI_CC_ETH_100G_FH2_MACSEC_CLK_SRC			35
+#define ECPRI_CC_ETH_100G_FH_0_HM_FF_0_CLK			36
+#define ECPRI_CC_ETH_100G_FH_0_HM_FF_0_DIV_CLK_SRC		37
+#define ECPRI_CC_ETH_100G_FH_0_HM_FF_1_CLK			38
+#define ECPRI_CC_ETH_100G_FH_0_HM_FF_1_DIV_CLK_SRC		39
+#define ECPRI_CC_ETH_100G_FH_0_HM_FF_2_CLK			40
+#define ECPRI_CC_ETH_100G_FH_0_HM_FF_2_DIV_CLK_SRC		41
+#define ECPRI_CC_ETH_100G_FH_0_HM_FF_3_CLK			42
+#define ECPRI_CC_ETH_100G_FH_0_HM_FF_3_DIV_CLK_SRC		43
+#define ECPRI_CC_ETH_100G_FH_0_UDP_FIFO_CLK			44
+#define ECPRI_CC_ETH_100G_FH_1_HM_FF_0_CLK			45
+#define ECPRI_CC_ETH_100G_FH_1_HM_FF_0_DIV_CLK_SRC		46
+#define ECPRI_CC_ETH_100G_FH_1_HM_FF_1_CLK			47
+#define ECPRI_CC_ETH_100G_FH_1_HM_FF_1_DIV_CLK_SRC		48
+#define ECPRI_CC_ETH_100G_FH_1_HM_FF_2_CLK			49
+#define ECPRI_CC_ETH_100G_FH_1_HM_FF_2_DIV_CLK_SRC		50
+#define ECPRI_CC_ETH_100G_FH_1_HM_FF_3_CLK			51
+#define ECPRI_CC_ETH_100G_FH_1_HM_FF_3_DIV_CLK_SRC		52
+#define ECPRI_CC_ETH_100G_FH_1_UDP_FIFO_CLK			53
+#define ECPRI_CC_ETH_100G_FH_2_HM_FF_0_CLK			54
+#define ECPRI_CC_ETH_100G_FH_2_HM_FF_0_DIV_CLK_SRC		55
+#define ECPRI_CC_ETH_100G_FH_2_HM_FF_1_CLK			56
+#define ECPRI_CC_ETH_100G_FH_2_HM_FF_1_DIV_CLK_SRC		57
+#define ECPRI_CC_ETH_100G_FH_2_HM_FF_2_CLK			58
+#define ECPRI_CC_ETH_100G_FH_2_HM_FF_2_DIV_CLK_SRC		59
+#define ECPRI_CC_ETH_100G_FH_2_HM_FF_3_CLK			60
+#define ECPRI_CC_ETH_100G_FH_2_HM_FF_3_DIV_CLK_SRC		61
+#define ECPRI_CC_ETH_100G_FH_2_UDP_FIFO_CLK			62
+#define ECPRI_CC_ETH_100G_FH_MACSEC_0_CLK			63
+#define ECPRI_CC_ETH_100G_FH_MACSEC_1_CLK			64
+#define ECPRI_CC_ETH_100G_FH_MACSEC_2_CLK			65
+#define ECPRI_CC_ETH_100G_MAC_C2C_HM_REF_CLK			66
+#define ECPRI_CC_ETH_100G_MAC_C2C_HM_REF_CLK_SRC		67
+#define ECPRI_CC_ETH_100G_MAC_DBG_C2C_HM_REF_CLK		68
+#define ECPRI_CC_ETH_100G_MAC_DBG_C2C_HM_REF_CLK_SRC		69
+#define ECPRI_CC_ETH_100G_MAC_FH0_HM_REF_CLK			70
+#define ECPRI_CC_ETH_100G_MAC_FH0_HM_REF_CLK_SRC		71
+#define ECPRI_CC_ETH_100G_MAC_FH1_HM_REF_CLK			72
+#define ECPRI_CC_ETH_100G_MAC_FH1_HM_REF_CLK_SRC		73
+#define ECPRI_CC_ETH_100G_MAC_FH2_HM_REF_CLK			74
+#define ECPRI_CC_ETH_100G_MAC_FH2_HM_REF_CLK_SRC		75
+#define ECPRI_CC_ETH_DBG_NFAPI_AXI_CLK				76
+#define ECPRI_CC_ETH_DBG_NOC_AXI_CLK				77
+#define ECPRI_CC_ETH_PHY_0_OCK_SRAM_CLK				78
+#define ECPRI_CC_ETH_PHY_1_OCK_SRAM_CLK				79
+#define ECPRI_CC_ETH_PHY_2_OCK_SRAM_CLK				80
+#define ECPRI_CC_ETH_PHY_3_OCK_SRAM_CLK				81
+#define ECPRI_CC_ETH_PHY_4_OCK_SRAM_CLK				82
+#define ECPRI_CC_MSS_EMAC_CLK					83
+#define ECPRI_CC_MSS_EMAC_CLK_SRC				84
+#define ECPRI_CC_MSS_ORAN_CLK					85
+#define ECPRI_CC_PHY0_LANE0_RX_CLK				86
+#define ECPRI_CC_PHY0_LANE0_TX_CLK				87
+#define ECPRI_CC_PHY0_LANE1_RX_CLK				88
+#define ECPRI_CC_PHY0_LANE1_TX_CLK				89
+#define ECPRI_CC_PHY0_LANE2_RX_CLK				90
+#define ECPRI_CC_PHY0_LANE2_TX_CLK				91
+#define ECPRI_CC_PHY0_LANE3_RX_CLK				92
+#define ECPRI_CC_PHY0_LANE3_TX_CLK				93
+#define ECPRI_CC_PHY1_LANE0_RX_CLK				94
+#define ECPRI_CC_PHY1_LANE0_TX_CLK				95
+#define ECPRI_CC_PHY1_LANE1_RX_CLK				96
+#define ECPRI_CC_PHY1_LANE1_TX_CLK				97
+#define ECPRI_CC_PHY1_LANE2_RX_CLK				98
+#define ECPRI_CC_PHY1_LANE2_TX_CLK				99
+#define ECPRI_CC_PHY1_LANE3_RX_CLK				100
+#define ECPRI_CC_PHY1_LANE3_TX_CLK				101
+#define ECPRI_CC_PHY2_LANE0_RX_CLK				102
+#define ECPRI_CC_PHY2_LANE0_TX_CLK				103
+#define ECPRI_CC_PHY2_LANE1_RX_CLK				104
+#define ECPRI_CC_PHY2_LANE1_TX_CLK				105
+#define ECPRI_CC_PHY2_LANE2_RX_CLK				106
+#define ECPRI_CC_PHY2_LANE2_TX_CLK				107
+#define ECPRI_CC_PHY2_LANE3_RX_CLK				108
+#define ECPRI_CC_PHY2_LANE3_TX_CLK				109
+#define ECPRI_CC_PHY3_LANE0_RX_CLK				110
+#define ECPRI_CC_PHY3_LANE0_TX_CLK				111
+#define ECPRI_CC_PHY3_LANE1_RX_CLK				112
+#define ECPRI_CC_PHY3_LANE1_TX_CLK				113
+#define ECPRI_CC_PHY3_LANE2_RX_CLK				114
+#define ECPRI_CC_PHY3_LANE2_TX_CLK				115
+#define ECPRI_CC_PHY3_LANE3_RX_CLK				116
+#define ECPRI_CC_PHY3_LANE3_TX_CLK				117
+#define ECPRI_CC_PHY4_LANE0_RX_CLK				118
+#define ECPRI_CC_PHY4_LANE0_TX_CLK				119
+#define ECPRI_CC_PHY4_LANE1_RX_CLK				120
+#define ECPRI_CC_PHY4_LANE1_TX_CLK				121
+#define ECPRI_CC_PHY4_LANE2_RX_CLK				122
+#define ECPRI_CC_PHY4_LANE2_TX_CLK				123
+#define ECPRI_CC_PHY4_LANE3_RX_CLK				124
+#define ECPRI_CC_PHY4_LANE3_TX_CLK				125
+
+/* ECPRI_CC resets */
+#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ECPRI_SS_BCR		0
+#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_C2C_BCR		1
+#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH0_BCR		2
+#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH1_BCR		3
+#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH2_BCR		4
+#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_WRAPPER_TOP_BCR	5
+#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_MODEM_BCR			6
+#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_NOC_BCR			7
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,sc8280xp-camcc.h b/include/dt-bindings/clock/qcom,sc8280xp-camcc.h
new file mode 100644
index 00000000000..ea5ec73c8c6
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sc8280xp-camcc.h
@@ -0,0 +1,179 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Linaro Ltd.
+ */
+
+#ifndef __DT_BINDINGS_CLK_QCOM_CAMCC_SC8280XP_H__
+#define __DT_BINDINGS_CLK_QCOM_CAMCC_SC8280XP_H__
+
+/* CAMCC clocks */
+#define CAMCC_PLL0					0
+#define CAMCC_PLL0_OUT_EVEN				1
+#define CAMCC_PLL0_OUT_ODD				2
+#define CAMCC_PLL1					3
+#define CAMCC_PLL1_OUT_EVEN				4
+#define CAMCC_PLL2					5
+#define CAMCC_PLL3					6
+#define CAMCC_PLL3_OUT_EVEN				7
+#define CAMCC_PLL4					8
+#define CAMCC_PLL4_OUT_EVEN				9
+#define CAMCC_PLL5					10
+#define CAMCC_PLL5_OUT_EVEN				11
+#define CAMCC_PLL6					12
+#define CAMCC_PLL6_OUT_EVEN				13
+#define CAMCC_PLL7					14
+#define CAMCC_PLL7_OUT_EVEN				15
+#define CAMCC_PLL7_OUT_ODD				16
+#define CAMCC_BPS_AHB_CLK				17
+#define CAMCC_BPS_AREG_CLK				18
+#define CAMCC_BPS_AXI_CLK				19
+#define CAMCC_BPS_CLK					20
+#define CAMCC_BPS_CLK_SRC				21
+#define CAMCC_CAMNOC_AXI_CLK				22
+#define CAMCC_CAMNOC_AXI_CLK_SRC			23
+#define CAMCC_CAMNOC_DCD_XO_CLK				24
+#define CAMCC_CCI_0_CLK					25
+#define CAMCC_CCI_0_CLK_SRC				26
+#define CAMCC_CCI_1_CLK					27
+#define CAMCC_CCI_1_CLK_SRC				28
+#define CAMCC_CCI_2_CLK					29
+#define CAMCC_CCI_2_CLK_SRC				30
+#define CAMCC_CCI_3_CLK					31
+#define CAMCC_CCI_3_CLK_SRC				32
+#define CAMCC_CORE_AHB_CLK				33
+#define CAMCC_CPAS_AHB_CLK				34
+#define CAMCC_CPHY_RX_CLK_SRC				35
+#define CAMCC_CSI0PHYTIMER_CLK				36
+#define CAMCC_CSI0PHYTIMER_CLK_SRC			37
+#define CAMCC_CSI1PHYTIMER_CLK				38
+#define CAMCC_CSI1PHYTIMER_CLK_SRC			39
+#define CAMCC_CSI2PHYTIMER_CLK				40
+#define CAMCC_CSI2PHYTIMER_CLK_SRC			41
+#define CAMCC_CSI3PHYTIMER_CLK				42
+#define CAMCC_CSI3PHYTIMER_CLK_SRC			43
+#define CAMCC_CSIPHY0_CLK				44
+#define CAMCC_CSIPHY1_CLK				45
+#define CAMCC_CSIPHY2_CLK				46
+#define CAMCC_CSIPHY3_CLK				47
+#define CAMCC_FAST_AHB_CLK_SRC				48
+#define CAMCC_GDSC_CLK					49
+#define CAMCC_ICP_AHB_CLK				50
+#define CAMCC_ICP_CLK					51
+#define CAMCC_ICP_CLK_SRC				52
+#define CAMCC_IFE_0_AXI_CLK				53
+#define CAMCC_IFE_0_CLK					54
+#define CAMCC_IFE_0_CLK_SRC				55
+#define CAMCC_IFE_0_CPHY_RX_CLK				56
+#define CAMCC_IFE_0_CSID_CLK				57
+#define CAMCC_IFE_0_CSID_CLK_SRC			58
+#define CAMCC_IFE_0_DSP_CLK				59
+#define CAMCC_IFE_1_AXI_CLK				60
+#define CAMCC_IFE_1_CLK					61
+#define CAMCC_IFE_1_CLK_SRC				62
+#define CAMCC_IFE_1_CPHY_RX_CLK				63
+#define CAMCC_IFE_1_CSID_CLK				64
+#define CAMCC_IFE_1_CSID_CLK_SRC			65
+#define CAMCC_IFE_1_DSP_CLK				66
+#define CAMCC_IFE_2_AXI_CLK				67
+#define CAMCC_IFE_2_CLK					68
+#define CAMCC_IFE_2_CLK_SRC				69
+#define CAMCC_IFE_2_CPHY_RX_CLK				70
+#define CAMCC_IFE_2_CSID_CLK				71
+#define CAMCC_IFE_2_CSID_CLK_SRC			72
+#define CAMCC_IFE_2_DSP_CLK				73
+#define CAMCC_IFE_3_AXI_CLK				74
+#define CAMCC_IFE_3_CLK					75
+#define CAMCC_IFE_3_CLK_SRC				76
+#define CAMCC_IFE_3_CPHY_RX_CLK				77
+#define CAMCC_IFE_3_CSID_CLK				78
+#define CAMCC_IFE_3_CSID_CLK_SRC			79
+#define CAMCC_IFE_3_DSP_CLK				80
+#define CAMCC_IFE_LITE_0_CLK				81
+#define CAMCC_IFE_LITE_0_CLK_SRC			82
+#define CAMCC_IFE_LITE_0_CPHY_RX_CLK			83
+#define CAMCC_IFE_LITE_0_CSID_CLK			84
+#define CAMCC_IFE_LITE_0_CSID_CLK_SRC			85
+#define CAMCC_IFE_LITE_1_CLK				86
+#define CAMCC_IFE_LITE_1_CLK_SRC			87
+#define CAMCC_IFE_LITE_1_CPHY_RX_CLK			88
+#define CAMCC_IFE_LITE_1_CSID_CLK			89
+#define CAMCC_IFE_LITE_1_CSID_CLK_SRC			90
+#define CAMCC_IFE_LITE_2_CLK				91
+#define CAMCC_IFE_LITE_2_CLK_SRC			92
+#define CAMCC_IFE_LITE_2_CPHY_RX_CLK			93
+#define CAMCC_IFE_LITE_2_CSID_CLK			94
+#define CAMCC_IFE_LITE_2_CSID_CLK_SRC			95
+#define CAMCC_IFE_LITE_3_CLK				96
+#define CAMCC_IFE_LITE_3_CLK_SRC			97
+#define CAMCC_IFE_LITE_3_CPHY_RX_CLK			98
+#define CAMCC_IFE_LITE_3_CSID_CLK			99
+#define CAMCC_IFE_LITE_3_CSID_CLK_SRC			100
+#define CAMCC_IPE_0_AHB_CLK				101
+#define CAMCC_IPE_0_AREG_CLK				102
+#define CAMCC_IPE_0_AXI_CLK				103
+#define CAMCC_IPE_0_CLK					104
+#define CAMCC_IPE_0_CLK_SRC				105
+#define CAMCC_IPE_1_AHB_CLK				106
+#define CAMCC_IPE_1_AREG_CLK				107
+#define CAMCC_IPE_1_AXI_CLK				108
+#define CAMCC_IPE_1_CLK					109
+#define CAMCC_JPEG_CLK					110
+#define CAMCC_JPEG_CLK_SRC				111
+#define CAMCC_LRME_CLK					112
+#define CAMCC_LRME_CLK_SRC				113
+#define CAMCC_MCLK0_CLK					114
+#define CAMCC_MCLK0_CLK_SRC				115
+#define CAMCC_MCLK1_CLK					116
+#define CAMCC_MCLK1_CLK_SRC				117
+#define CAMCC_MCLK2_CLK					118
+#define CAMCC_MCLK2_CLK_SRC				119
+#define CAMCC_MCLK3_CLK					120
+#define CAMCC_MCLK3_CLK_SRC				121
+#define CAMCC_MCLK4_CLK					122
+#define CAMCC_MCLK4_CLK_SRC				123
+#define CAMCC_MCLK5_CLK					124
+#define CAMCC_MCLK5_CLK_SRC				125
+#define CAMCC_MCLK6_CLK					126
+#define CAMCC_MCLK6_CLK_SRC				127
+#define CAMCC_MCLK7_CLK					128
+#define CAMCC_MCLK7_CLK_SRC				129
+#define CAMCC_SLEEP_CLK					130
+#define CAMCC_SLEEP_CLK_SRC				131
+#define CAMCC_SLOW_AHB_CLK_SRC				132
+#define CAMCC_XO_CLK_SRC				133
+
+/* CAMCC resets */
+#define CAMCC_BPS_BCR					0
+#define CAMCC_CAMNOC_BCR				1
+#define CAMCC_CCI_BCR					2
+#define CAMCC_CPAS_BCR					3
+#define CAMCC_CSI0PHY_BCR				4
+#define CAMCC_CSI1PHY_BCR				5
+#define CAMCC_CSI2PHY_BCR				6
+#define CAMCC_CSI3PHY_BCR				7
+#define CAMCC_ICP_BCR					8
+#define CAMCC_IFE_0_BCR					9
+#define CAMCC_IFE_1_BCR					10
+#define CAMCC_IFE_2_BCR					11
+#define CAMCC_IFE_3_BCR					12
+#define CAMCC_IFE_LITE_0_BCR				13
+#define CAMCC_IFE_LITE_1_BCR				14
+#define CAMCC_IFE_LITE_2_BCR				15
+#define CAMCC_IFE_LITE_3_BCR				16
+#define CAMCC_IPE_0_BCR					17
+#define CAMCC_IPE_1_BCR					18
+#define CAMCC_JPEG_BCR					19
+#define CAMCC_LRME_BCR					20
+
+/* CAMCC GDSCRs */
+#define BPS_GDSC					0
+#define IFE_0_GDSC					1
+#define IFE_1_GDSC					2
+#define IFE_2_GDSC					3
+#define IFE_3_GDSC					4
+#define IPE_0_GDSC					5
+#define IPE_1_GDSC					6
+#define TITAN_TOP_GDSC					7
+
+#endif /* __DT_BINDINGS_CLK_QCOM_CAMCC_SC8280XP_H__ */
diff --git a/include/dt-bindings/clock/qcom,sm8650-dispcc.h b/include/dt-bindings/clock/qcom,sm8650-dispcc.h
new file mode 100644
index 00000000000..b0a668b395a
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sm8650-dispcc.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved
+ * Copyright (c) 2023, Linaro Ltd.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_SM8650_DISP_CC_H
+#define _DT_BINDINGS_CLK_QCOM_SM8650_DISP_CC_H
+
+/* DISP_CC clocks */
+#define DISP_CC_MDSS_ACCU_CLK					0
+#define DISP_CC_MDSS_AHB1_CLK					1
+#define DISP_CC_MDSS_AHB_CLK					2
+#define DISP_CC_MDSS_AHB_CLK_SRC				3
+#define DISP_CC_MDSS_BYTE0_CLK					4
+#define DISP_CC_MDSS_BYTE0_CLK_SRC				5
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC				6
+#define DISP_CC_MDSS_BYTE0_INTF_CLK				7
+#define DISP_CC_MDSS_BYTE1_CLK					8
+#define DISP_CC_MDSS_BYTE1_CLK_SRC				9
+#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC				10
+#define DISP_CC_MDSS_BYTE1_INTF_CLK				11
+#define DISP_CC_MDSS_DPTX0_AUX_CLK				12
+#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC				13
+#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK				14
+#define DISP_CC_MDSS_DPTX0_LINK_CLK				15
+#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC				16
+#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC			17
+#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK			18
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK				19
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC			20
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK				21
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC			22
+#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK		23
+#define DISP_CC_MDSS_DPTX1_AUX_CLK				24
+#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC				25
+#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK				26
+#define DISP_CC_MDSS_DPTX1_LINK_CLK				27
+#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC				28
+#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC			29
+#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK			30
+#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK				31
+#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC			32
+#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK				33
+#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC			34
+#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK		35
+#define DISP_CC_MDSS_DPTX2_AUX_CLK				36
+#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC				37
+#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK				38
+#define DISP_CC_MDSS_DPTX2_LINK_CLK				39
+#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC				40
+#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC			41
+#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK			42
+#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK				43
+#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC			44
+#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK				45
+#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC			46
+#define DISP_CC_MDSS_DPTX3_AUX_CLK				47
+#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC				48
+#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK				49
+#define DISP_CC_MDSS_DPTX3_LINK_CLK				50
+#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC				51
+#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC			52
+#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK			53
+#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK				54
+#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC			55
+#define DISP_CC_MDSS_ESC0_CLK					56
+#define DISP_CC_MDSS_ESC0_CLK_SRC				57
+#define DISP_CC_MDSS_ESC1_CLK					58
+#define DISP_CC_MDSS_ESC1_CLK_SRC				59
+#define DISP_CC_MDSS_MDP1_CLK					60
+#define DISP_CC_MDSS_MDP_CLK					61
+#define DISP_CC_MDSS_MDP_CLK_SRC				62
+#define DISP_CC_MDSS_MDP_LUT1_CLK				63
+#define DISP_CC_MDSS_MDP_LUT_CLK				64
+#define DISP_CC_MDSS_NON_GDSC_AHB_CLK				65
+#define DISP_CC_MDSS_PCLK0_CLK					66
+#define DISP_CC_MDSS_PCLK0_CLK_SRC				67
+#define DISP_CC_MDSS_PCLK1_CLK					68
+#define DISP_CC_MDSS_PCLK1_CLK_SRC				69
+#define DISP_CC_MDSS_RSCC_AHB_CLK				70
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK				71
+#define DISP_CC_MDSS_VSYNC1_CLK					72
+#define DISP_CC_MDSS_VSYNC_CLK					73
+#define DISP_CC_MDSS_VSYNC_CLK_SRC				74
+#define DISP_CC_PLL0						75
+#define DISP_CC_PLL1						76
+#define DISP_CC_SLEEP_CLK					77
+#define DISP_CC_SLEEP_CLK_SRC					78
+#define DISP_CC_XO_CLK						79
+#define DISP_CC_XO_CLK_SRC					80
+
+/* DISP_CC resets */
+#define DISP_CC_MDSS_CORE_BCR					0
+#define DISP_CC_MDSS_CORE_INT2_BCR				1
+#define DISP_CC_MDSS_RSCC_BCR					2
+
+/* DISP_CC GDSCR */
+#define MDSS_GDSC						0
+#define MDSS_INT2_GDSC						1
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,sm8650-gcc.h b/include/dt-bindings/clock/qcom,sm8650-gcc.h
new file mode 100644
index 00000000000..0c543ba4607
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sm8650-gcc.h
@@ -0,0 +1,254 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8650_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_SM8650_H
+
+/* GCC clocks */
+#define GCC_AGGRE_NOC_PCIE_AXI_CLK				0
+#define GCC_AGGRE_UFS_PHY_AXI_CLK				1
+#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK			2
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK				3
+#define GCC_BOOT_ROM_AHB_CLK					4
+#define GCC_CAMERA_AHB_CLK					5
+#define GCC_CAMERA_HF_AXI_CLK					6
+#define GCC_CAMERA_SF_AXI_CLK					7
+#define GCC_CAMERA_XO_CLK					8
+#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK				9
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				10
+#define GCC_CNOC_PCIE_SF_AXI_CLK				11
+#define GCC_DDRSS_GPU_AXI_CLK					12
+#define GCC_DDRSS_PCIE_SF_QTB_CLK				13
+#define GCC_DISP_AHB_CLK					14
+#define GCC_DISP_HF_AXI_CLK					15
+#define GCC_DISP_XO_CLK						16
+#define GCC_GP1_CLK						17
+#define GCC_GP1_CLK_SRC						18
+#define GCC_GP2_CLK						19
+#define GCC_GP2_CLK_SRC						20
+#define GCC_GP3_CLK						21
+#define GCC_GP3_CLK_SRC						22
+#define GCC_GPLL0						23
+#define GCC_GPLL0_OUT_EVEN					24
+#define GCC_GPLL1						25
+#define GCC_GPLL3						26
+#define GCC_GPLL4						27
+#define GCC_GPLL6						28
+#define GCC_GPLL7						29
+#define GCC_GPLL9						30
+#define GCC_GPU_CFG_AHB_CLK					31
+#define GCC_GPU_GPLL0_CLK_SRC					32
+#define GCC_GPU_GPLL0_DIV_CLK_SRC				33
+#define GCC_GPU_MEMNOC_GFX_CLK					34
+#define GCC_GPU_SNOC_DVM_GFX_CLK				35
+#define GCC_PCIE_0_AUX_CLK					36
+#define GCC_PCIE_0_AUX_CLK_SRC					37
+#define GCC_PCIE_0_CFG_AHB_CLK					38
+#define GCC_PCIE_0_MSTR_AXI_CLK					39
+#define GCC_PCIE_0_PHY_RCHNG_CLK				40
+#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC				41
+#define GCC_PCIE_0_PIPE_CLK					42
+#define GCC_PCIE_0_PIPE_CLK_SRC					43
+#define GCC_PCIE_0_SLV_AXI_CLK					44
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				45
+#define GCC_PCIE_1_AUX_CLK					46
+#define GCC_PCIE_1_AUX_CLK_SRC					47
+#define GCC_PCIE_1_CFG_AHB_CLK					48
+#define GCC_PCIE_1_MSTR_AXI_CLK					49
+#define GCC_PCIE_1_PHY_AUX_CLK					50
+#define GCC_PCIE_1_PHY_AUX_CLK_SRC				51
+#define GCC_PCIE_1_PHY_RCHNG_CLK				52
+#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC				53
+#define GCC_PCIE_1_PIPE_CLK					54
+#define GCC_PCIE_1_PIPE_CLK_SRC					55
+#define GCC_PCIE_1_SLV_AXI_CLK					56
+#define GCC_PCIE_1_SLV_Q2A_AXI_CLK				57
+#define GCC_PDM2_CLK						58
+#define GCC_PDM2_CLK_SRC					59
+#define GCC_PDM_AHB_CLK						60
+#define GCC_PDM_XO4_CLK						61
+#define GCC_QMIP_CAMERA_NRT_AHB_CLK				62
+#define GCC_QMIP_CAMERA_RT_AHB_CLK				63
+#define GCC_QMIP_DISP_AHB_CLK					64
+#define GCC_QMIP_GPU_AHB_CLK					65
+#define GCC_QMIP_PCIE_AHB_CLK					66
+#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK				67
+#define GCC_QMIP_VIDEO_CVP_AHB_CLK				68
+#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK				69
+#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				70
+#define GCC_QUPV3_I2C_CORE_CLK					71
+#define GCC_QUPV3_I2C_S0_CLK					72
+#define GCC_QUPV3_I2C_S0_CLK_SRC				73
+#define GCC_QUPV3_I2C_S1_CLK					74
+#define GCC_QUPV3_I2C_S1_CLK_SRC				75
+#define GCC_QUPV3_I2C_S2_CLK					76
+#define GCC_QUPV3_I2C_S2_CLK_SRC				77
+#define GCC_QUPV3_I2C_S3_CLK					78
+#define GCC_QUPV3_I2C_S3_CLK_SRC				79
+#define GCC_QUPV3_I2C_S4_CLK					80
+#define GCC_QUPV3_I2C_S4_CLK_SRC				81
+#define GCC_QUPV3_I2C_S5_CLK					82
+#define GCC_QUPV3_I2C_S5_CLK_SRC				83
+#define GCC_QUPV3_I2C_S6_CLK					84
+#define GCC_QUPV3_I2C_S6_CLK_SRC				85
+#define GCC_QUPV3_I2C_S7_CLK					86
+#define GCC_QUPV3_I2C_S7_CLK_SRC				87
+#define GCC_QUPV3_I2C_S8_CLK					88
+#define GCC_QUPV3_I2C_S8_CLK_SRC				89
+#define GCC_QUPV3_I2C_S9_CLK					90
+#define GCC_QUPV3_I2C_S9_CLK_SRC				91
+#define GCC_QUPV3_I2C_S_AHB_CLK					92
+#define GCC_QUPV3_WRAP1_CORE_2X_CLK				93
+#define GCC_QUPV3_WRAP1_CORE_CLK				94
+#define GCC_QUPV3_WRAP1_QSPI_REF_CLK				95
+#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC			96
+#define GCC_QUPV3_WRAP1_S0_CLK					97
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC				98
+#define GCC_QUPV3_WRAP1_S1_CLK					99
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC				100
+#define GCC_QUPV3_WRAP1_S2_CLK					101
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC				102
+#define GCC_QUPV3_WRAP1_S3_CLK					103
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC				104
+#define GCC_QUPV3_WRAP1_S4_CLK					105
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC				106
+#define GCC_QUPV3_WRAP1_S5_CLK					107
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC				108
+#define GCC_QUPV3_WRAP1_S6_CLK					109
+#define GCC_QUPV3_WRAP1_S6_CLK_SRC				110
+#define GCC_QUPV3_WRAP1_S7_CLK					111
+#define GCC_QUPV3_WRAP1_S7_CLK_SRC				112
+#define GCC_QUPV3_WRAP2_CORE_2X_CLK				113
+#define GCC_QUPV3_WRAP2_CORE_CLK				114
+#define GCC_QUPV3_WRAP2_IBI_CTRL_0_CLK_SRC			115
+#define GCC_QUPV3_WRAP2_IBI_CTRL_2_CLK				116
+#define GCC_QUPV3_WRAP2_IBI_CTRL_3_CLK				117
+#define GCC_QUPV3_WRAP2_S0_CLK					118
+#define GCC_QUPV3_WRAP2_S0_CLK_SRC				119
+#define GCC_QUPV3_WRAP2_S1_CLK					120
+#define GCC_QUPV3_WRAP2_S1_CLK_SRC				121
+#define GCC_QUPV3_WRAP2_S2_CLK					122
+#define GCC_QUPV3_WRAP2_S2_CLK_SRC				123
+#define GCC_QUPV3_WRAP2_S3_CLK					124
+#define GCC_QUPV3_WRAP2_S3_CLK_SRC				125
+#define GCC_QUPV3_WRAP2_S4_CLK					126
+#define GCC_QUPV3_WRAP2_S4_CLK_SRC				127
+#define GCC_QUPV3_WRAP2_S5_CLK					128
+#define GCC_QUPV3_WRAP2_S5_CLK_SRC				129
+#define GCC_QUPV3_WRAP2_S6_CLK					130
+#define GCC_QUPV3_WRAP2_S6_CLK_SRC				131
+#define GCC_QUPV3_WRAP2_S7_CLK					132
+#define GCC_QUPV3_WRAP2_S7_CLK_SRC				133
+#define GCC_QUPV3_WRAP3_CORE_2X_CLK				134
+#define GCC_QUPV3_WRAP3_CORE_CLK				135
+#define GCC_QUPV3_WRAP3_QSPI_REF_CLK				136
+#define GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC			137
+#define GCC_QUPV3_WRAP3_S0_CLK					138
+#define GCC_QUPV3_WRAP3_S0_CLK_SRC				139
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK				140
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK				141
+#define GCC_QUPV3_WRAP_2_IBI_2_AHB_CLK				142
+#define GCC_QUPV3_WRAP_2_IBI_3_AHB_CLK				143
+#define GCC_QUPV3_WRAP_2_M_AHB_CLK				144
+#define GCC_QUPV3_WRAP_2_S_AHB_CLK				145
+#define GCC_QUPV3_WRAP_3_M_AHB_CLK				146
+#define GCC_QUPV3_WRAP_3_S_AHB_CLK				147
+#define GCC_SDCC2_AHB_CLK					148
+#define GCC_SDCC2_APPS_CLK					149
+#define GCC_SDCC2_APPS_CLK_SRC					150
+#define GCC_SDCC4_AHB_CLK					151
+#define GCC_SDCC4_APPS_CLK					152
+#define GCC_SDCC4_APPS_CLK_SRC					153
+#define GCC_UFS_PHY_AHB_CLK					154
+#define GCC_UFS_PHY_AXI_CLK					155
+#define GCC_UFS_PHY_AXI_CLK_SRC					156
+#define GCC_UFS_PHY_AXI_HW_CTL_CLK				157
+#define GCC_UFS_PHY_ICE_CORE_CLK				158
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				159
+#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK				160
+#define GCC_UFS_PHY_PHY_AUX_CLK					161
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				162
+#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK				163
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				164
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC				165
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				166
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC				167
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				168
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC				169
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK				170
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				171
+#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK			172
+#define GCC_USB30_PRIM_MASTER_CLK				173
+#define GCC_USB30_PRIM_MASTER_CLK_SRC				174
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK				175
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			176
+#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC		177
+#define GCC_USB30_PRIM_SLEEP_CLK				178
+#define GCC_USB3_PRIM_PHY_AUX_CLK				179
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				180
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				181
+#define GCC_USB3_PRIM_PHY_PIPE_CLK				182
+#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC				183
+#define GCC_VIDEO_AHB_CLK					184
+#define GCC_VIDEO_AXI0_CLK					185
+#define GCC_VIDEO_AXI1_CLK					186
+#define GCC_VIDEO_XO_CLK					187
+#define GCC_GPLL0_AO						188
+#define GCC_GPLL0_OUT_EVEN_AO					189
+#define GCC_GPLL1_AO						190
+#define GCC_GPLL3_AO						191
+#define GCC_GPLL4_AO						192
+#define GCC_GPLL6_AO						193
+
+/* GCC resets */
+#define GCC_CAMERA_BCR						0
+#define GCC_DISPLAY_BCR						1
+#define GCC_GPU_BCR						2
+#define GCC_PCIE_0_BCR						3
+#define GCC_PCIE_0_LINK_DOWN_BCR				4
+#define GCC_PCIE_0_NOCSR_COM_PHY_BCR				5
+#define GCC_PCIE_0_PHY_BCR					6
+#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR			7
+#define GCC_PCIE_1_BCR						8
+#define GCC_PCIE_1_LINK_DOWN_BCR				9
+#define GCC_PCIE_1_NOCSR_COM_PHY_BCR				10
+#define GCC_PCIE_1_PHY_BCR					11
+#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR			12
+#define GCC_PCIE_PHY_BCR					13
+#define GCC_PCIE_PHY_CFG_AHB_BCR				14
+#define GCC_PCIE_PHY_COM_BCR					15
+#define GCC_PDM_BCR						16
+#define GCC_QUPV3_WRAPPER_1_BCR					17
+#define GCC_QUPV3_WRAPPER_2_BCR					18
+#define GCC_QUPV3_WRAPPER_3_BCR					19
+#define GCC_QUPV3_WRAPPER_I2C_BCR				20
+#define GCC_QUSB2PHY_PRIM_BCR					21
+#define GCC_QUSB2PHY_SEC_BCR					22
+#define GCC_SDCC2_BCR						23
+#define GCC_SDCC4_BCR						24
+#define GCC_UFS_PHY_BCR						25
+#define GCC_USB30_PRIM_BCR					26
+#define GCC_USB3_DP_PHY_PRIM_BCR				27
+#define GCC_USB3_DP_PHY_SEC_BCR					28
+#define GCC_USB3_PHY_PRIM_BCR					29
+#define GCC_USB3_PHY_SEC_BCR					30
+#define GCC_USB3PHY_PHY_PRIM_BCR				31
+#define GCC_USB3PHY_PHY_SEC_BCR					32
+#define GCC_VIDEO_AXI0_CLK_ARES					33
+#define GCC_VIDEO_AXI1_CLK_ARES					34
+#define GCC_VIDEO_BCR						35
+
+/* GCC power domains */
+#define PCIE_0_GDSC						0
+#define PCIE_0_PHY_GDSC						1
+#define PCIE_1_GDSC						2
+#define PCIE_1_PHY_GDSC						3
+#define UFS_PHY_GDSC						4
+#define UFS_MEM_PHY_GDSC					5
+#define USB30_PRIM_GDSC						6
+#define USB3_PHY_GDSC						7
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,sm8650-gpucc.h b/include/dt-bindings/clock/qcom,sm8650-gpucc.h
new file mode 100644
index 00000000000..d0dc457cfe7
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sm8650-gpucc.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8650_H
+#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8650_H
+
+/* GPU_CC clocks */
+#define GPU_CC_AHB_CLK				0
+#define GPU_CC_CRC_AHB_CLK			1
+#define GPU_CC_CX_ACCU_SHIFT_CLK		2
+#define GPU_CC_CX_FF_CLK			3
+#define GPU_CC_CX_GMU_CLK			4
+#define GPU_CC_CXO_AON_CLK			5
+#define GPU_CC_CXO_CLK				6
+#define GPU_CC_DEMET_CLK			7
+#define GPU_CC_DPM_CLK				8
+#define GPU_CC_FF_CLK_SRC			9
+#define GPU_CC_FREQ_MEASURE_CLK			10
+#define GPU_CC_GMU_CLK_SRC			11
+#define GPU_CC_GX_ACCU_SHIFT_CLK		12
+#define GPU_CC_GX_FF_CLK			13
+#define GPU_CC_GX_GFX3D_CLK			14
+#define GPU_CC_GX_GFX3D_RDVM_CLK		15
+#define GPU_CC_GX_GMU_CLK			16
+#define GPU_CC_GX_VSENSE_CLK			17
+#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK		18
+#define GPU_CC_HUB_AON_CLK			19
+#define GPU_CC_HUB_CLK_SRC			20
+#define GPU_CC_HUB_CX_INT_CLK			21
+#define GPU_CC_HUB_DIV_CLK_SRC			22
+#define GPU_CC_MEMNOC_GFX_CLK			23
+#define GPU_CC_PLL0				24
+#define GPU_CC_PLL1				25
+#define GPU_CC_SLEEP_CLK			26
+
+/* GDSCs */
+#define GPU_GX_GDSC				0
+#define GPU_CX_GDSC				1
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,sm8650-tcsr.h b/include/dt-bindings/clock/qcom,sm8650-tcsr.h
new file mode 100644
index 00000000000..b2c72d492f1
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sm8650-tcsr.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8650_H
+#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8650_H
+
+/* TCSR CC clocks */
+#define TCSR_PCIE_0_CLKREF_EN					0
+#define TCSR_PCIE_1_CLKREF_EN					1
+#define TCSR_UFS_CLKREF_EN					2
+#define TCSR_UFS_PAD_CLKREF_EN					3
+#define TCSR_USB2_CLKREF_EN					4
+#define TCSR_USB3_CLKREF_EN					5
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,videocc-sm8150.h b/include/dt-bindings/clock/qcom,videocc-sm8150.h
index e24ee840cfd..c557b78dc57 100644
--- a/include/dt-bindings/clock/qcom,videocc-sm8150.h
+++ b/include/dt-bindings/clock/qcom,videocc-sm8150.h
@@ -16,6 +16,10 @@
 
 /* VIDEO_CC Resets */
 #define VIDEO_CC_MVSC_CORE_CLK_BCR	0
+#define VIDEO_CC_INTERFACE_BCR		1
+#define VIDEO_CC_MVS0_BCR		2
+#define VIDEO_CC_MVS1_BCR		3
+#define VIDEO_CC_MVSC_BCR		4
 
 /* VIDEO_CC GDSCRs */
 #define VENUS_GDSC			0
diff --git a/include/dt-bindings/clock/qcom,x1e80100-gcc.h b/include/dt-bindings/clock/qcom,x1e80100-gcc.h
new file mode 100644
index 00000000000..24ba9e2a5cf
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,x1e80100-gcc.h
@@ -0,0 +1,485 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_X1E80100_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_X1E80100_H
+
+/* GCC clocks */
+#define GCC_AGGRE_NOC_USB_NORTH_AXI_CLK				0
+#define GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK				1
+#define GCC_AGGRE_UFS_PHY_AXI_CLK				2
+#define GCC_AGGRE_USB2_PRIM_AXI_CLK				3
+#define GCC_AGGRE_USB3_MP_AXI_CLK				4
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK				5
+#define GCC_AGGRE_USB3_SEC_AXI_CLK				6
+#define GCC_AGGRE_USB3_TERT_AXI_CLK				7
+#define GCC_AGGRE_USB4_0_AXI_CLK				8
+#define GCC_AGGRE_USB4_1_AXI_CLK				9
+#define GCC_AGGRE_USB4_2_AXI_CLK				10
+#define GCC_AGGRE_USB_NOC_AXI_CLK				11
+#define GCC_AV1E_AHB_CLK					12
+#define GCC_AV1E_AXI_CLK					13
+#define GCC_AV1E_XO_CLK						14
+#define GCC_BOOT_ROM_AHB_CLK					15
+#define GCC_CAMERA_AHB_CLK					16
+#define GCC_CAMERA_HF_AXI_CLK					17
+#define GCC_CAMERA_SF_AXI_CLK					18
+#define GCC_CAMERA_XO_CLK					19
+#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK				20
+#define GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK			21
+#define GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK			22
+#define GCC_CFG_NOC_USB2_PRIM_AXI_CLK				23
+#define GCC_CFG_NOC_USB3_MP_AXI_CLK				24
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				25
+#define GCC_CFG_NOC_USB3_SEC_AXI_CLK				26
+#define GCC_CFG_NOC_USB3_TERT_AXI_CLK				27
+#define GCC_CFG_NOC_USB_ANOC_AHB_CLK				28
+#define GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK			29
+#define GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK			30
+#define GCC_CNOC_PCIE1_TUNNEL_CLK				31
+#define GCC_CNOC_PCIE2_TUNNEL_CLK				32
+#define GCC_CNOC_PCIE_NORTH_SF_AXI_CLK				33
+#define GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK				34
+#define GCC_CNOC_PCIE_TUNNEL_CLK				35
+#define GCC_DDRSS_GPU_AXI_CLK					36
+#define GCC_DISP_AHB_CLK					37
+#define GCC_DISP_HF_AXI_CLK					38
+#define GCC_DISP_XO_CLK						39
+#define GCC_GP1_CLK						40
+#define GCC_GP1_CLK_SRC						41
+#define GCC_GP2_CLK						42
+#define GCC_GP2_CLK_SRC						43
+#define GCC_GP3_CLK						44
+#define GCC_GP3_CLK_SRC						45
+#define GCC_GPLL0						46
+#define GCC_GPLL0_OUT_EVEN					47
+#define GCC_GPLL4						48
+#define GCC_GPLL7						49
+#define GCC_GPLL8						50
+#define GCC_GPLL9						51
+#define GCC_GPU_CFG_AHB_CLK					52
+#define GCC_GPU_GPLL0_CPH_CLK_SRC				53
+#define GCC_GPU_GPLL0_DIV_CPH_CLK_SRC				54
+#define GCC_GPU_MEMNOC_GFX_CLK					55
+#define GCC_GPU_SNOC_DVM_GFX_CLK				56
+#define GCC_PCIE0_PHY_RCHNG_CLK					57
+#define GCC_PCIE1_PHY_RCHNG_CLK					58
+#define GCC_PCIE2_PHY_RCHNG_CLK					59
+#define GCC_PCIE_0_AUX_CLK					60
+#define GCC_PCIE_0_AUX_CLK_SRC					61
+#define GCC_PCIE_0_CFG_AHB_CLK					62
+#define GCC_PCIE_0_MSTR_AXI_CLK					63
+#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC				64
+#define GCC_PCIE_0_PIPE_CLK					65
+#define GCC_PCIE_0_SLV_AXI_CLK					66
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				67
+#define GCC_PCIE_1_AUX_CLK					68
+#define GCC_PCIE_1_AUX_CLK_SRC					69
+#define GCC_PCIE_1_CFG_AHB_CLK					70
+#define GCC_PCIE_1_MSTR_AXI_CLK					71
+#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC				72
+#define GCC_PCIE_1_PIPE_CLK					73
+#define GCC_PCIE_1_SLV_AXI_CLK					74
+#define GCC_PCIE_1_SLV_Q2A_AXI_CLK				75
+#define GCC_PCIE_2_AUX_CLK					76
+#define GCC_PCIE_2_AUX_CLK_SRC					77
+#define GCC_PCIE_2_CFG_AHB_CLK					78
+#define GCC_PCIE_2_MSTR_AXI_CLK					79
+#define GCC_PCIE_2_PHY_RCHNG_CLK_SRC				80
+#define GCC_PCIE_2_PIPE_CLK					81
+#define GCC_PCIE_2_SLV_AXI_CLK					82
+#define GCC_PCIE_2_SLV_Q2A_AXI_CLK				83
+#define GCC_PCIE_3_AUX_CLK					84
+#define GCC_PCIE_3_AUX_CLK_SRC					85
+#define GCC_PCIE_3_CFG_AHB_CLK					86
+#define GCC_PCIE_3_MSTR_AXI_CLK					87
+#define GCC_PCIE_3_PHY_AUX_CLK					88
+#define GCC_PCIE_3_PHY_RCHNG_CLK				89
+#define GCC_PCIE_3_PHY_RCHNG_CLK_SRC				90
+#define GCC_PCIE_3_PIPE_CLK					91
+#define GCC_PCIE_3_PIPE_DIV_CLK_SRC				92
+#define GCC_PCIE_3_PIPEDIV2_CLK					93
+#define GCC_PCIE_3_SLV_AXI_CLK					94
+#define GCC_PCIE_3_SLV_Q2A_AXI_CLK				95
+#define GCC_PCIE_4_AUX_CLK					96
+#define GCC_PCIE_4_AUX_CLK_SRC					97
+#define GCC_PCIE_4_CFG_AHB_CLK					98
+#define GCC_PCIE_4_MSTR_AXI_CLK					99
+#define GCC_PCIE_4_PHY_RCHNG_CLK				100
+#define GCC_PCIE_4_PHY_RCHNG_CLK_SRC				101
+#define GCC_PCIE_4_PIPE_CLK					102
+#define GCC_PCIE_4_PIPE_DIV_CLK_SRC				103
+#define GCC_PCIE_4_PIPEDIV2_CLK					104
+#define GCC_PCIE_4_SLV_AXI_CLK					105
+#define GCC_PCIE_4_SLV_Q2A_AXI_CLK				106
+#define GCC_PCIE_5_AUX_CLK					107
+#define GCC_PCIE_5_AUX_CLK_SRC					108
+#define GCC_PCIE_5_CFG_AHB_CLK					109
+#define GCC_PCIE_5_MSTR_AXI_CLK					110
+#define GCC_PCIE_5_PHY_RCHNG_CLK				111
+#define GCC_PCIE_5_PHY_RCHNG_CLK_SRC				112
+#define GCC_PCIE_5_PIPE_CLK					113
+#define GCC_PCIE_5_PIPE_DIV_CLK_SRC				114
+#define GCC_PCIE_5_PIPEDIV2_CLK					115
+#define GCC_PCIE_5_SLV_AXI_CLK					116
+#define GCC_PCIE_5_SLV_Q2A_AXI_CLK				117
+#define GCC_PCIE_6A_AUX_CLK					118
+#define GCC_PCIE_6A_AUX_CLK_SRC					119
+#define GCC_PCIE_6A_CFG_AHB_CLK					120
+#define GCC_PCIE_6A_MSTR_AXI_CLK				121
+#define GCC_PCIE_6A_PHY_AUX_CLK					122
+#define GCC_PCIE_6A_PHY_RCHNG_CLK				123
+#define GCC_PCIE_6A_PHY_RCHNG_CLK_SRC				124
+#define GCC_PCIE_6A_PIPE_CLK					125
+#define GCC_PCIE_6A_PIPE_DIV_CLK_SRC				126
+#define GCC_PCIE_6A_PIPEDIV2_CLK				127
+#define GCC_PCIE_6A_SLV_AXI_CLK					128
+#define GCC_PCIE_6A_SLV_Q2A_AXI_CLK				129
+#define GCC_PCIE_6B_AUX_CLK					130
+#define GCC_PCIE_6B_AUX_CLK_SRC					131
+#define GCC_PCIE_6B_CFG_AHB_CLK					132
+#define GCC_PCIE_6B_MSTR_AXI_CLK				133
+#define GCC_PCIE_6B_PHY_AUX_CLK					134
+#define GCC_PCIE_6B_PHY_RCHNG_CLK				135
+#define GCC_PCIE_6B_PHY_RCHNG_CLK_SRC				136
+#define GCC_PCIE_6B_PIPE_CLK					137
+#define GCC_PCIE_6B_PIPE_DIV_CLK_SRC				138
+#define GCC_PCIE_6B_PIPEDIV2_CLK				139
+#define GCC_PCIE_6B_SLV_AXI_CLK					140
+#define GCC_PCIE_6B_SLV_Q2A_AXI_CLK				141
+#define GCC_PCIE_RSCC_AHB_CLK					142
+#define GCC_PCIE_RSCC_XO_CLK					143
+#define GCC_PCIE_RSCC_XO_CLK_SRC				144
+#define GCC_PDM2_CLK						145
+#define GCC_PDM2_CLK_SRC					146
+#define GCC_PDM_AHB_CLK						147
+#define GCC_PDM_XO4_CLK						148
+#define GCC_QMIP_AV1E_AHB_CLK					149
+#define GCC_QMIP_CAMERA_NRT_AHB_CLK				150
+#define GCC_QMIP_CAMERA_RT_AHB_CLK				151
+#define GCC_QMIP_DISP_AHB_CLK					152
+#define GCC_QMIP_GPU_AHB_CLK					153
+#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK				154
+#define GCC_QMIP_VIDEO_CVP_AHB_CLK				155
+#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK				156
+#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				157
+#define GCC_QUPV3_WRAP0_CORE_2X_CLK				158
+#define GCC_QUPV3_WRAP0_CORE_CLK				159
+#define GCC_QUPV3_WRAP0_QSPI_S2_CLK				160
+#define GCC_QUPV3_WRAP0_QSPI_S3_CLK				161
+#define GCC_QUPV3_WRAP0_S0_CLK					162
+#define GCC_QUPV3_WRAP0_S0_CLK_SRC				163
+#define GCC_QUPV3_WRAP0_S1_CLK					164
+#define GCC_QUPV3_WRAP0_S1_CLK_SRC				165
+#define GCC_QUPV3_WRAP0_S2_CLK					166
+#define GCC_QUPV3_WRAP0_S2_CLK_SRC				167
+#define GCC_QUPV3_WRAP0_S2_DIV_CLK_SRC				168
+#define GCC_QUPV3_WRAP0_S3_CLK					169
+#define GCC_QUPV3_WRAP0_S3_CLK_SRC				170
+#define GCC_QUPV3_WRAP0_S3_DIV_CLK_SRC				171
+#define GCC_QUPV3_WRAP0_S4_CLK					172
+#define GCC_QUPV3_WRAP0_S4_CLK_SRC				173
+#define GCC_QUPV3_WRAP0_S5_CLK					174
+#define GCC_QUPV3_WRAP0_S5_CLK_SRC				175
+#define GCC_QUPV3_WRAP0_S6_CLK					176
+#define GCC_QUPV3_WRAP0_S6_CLK_SRC				177
+#define GCC_QUPV3_WRAP0_S7_CLK					178
+#define GCC_QUPV3_WRAP0_S7_CLK_SRC				179
+#define GCC_QUPV3_WRAP1_CORE_2X_CLK				180
+#define GCC_QUPV3_WRAP1_CORE_CLK				181
+#define GCC_QUPV3_WRAP1_QSPI_S2_CLK				182
+#define GCC_QUPV3_WRAP1_QSPI_S3_CLK				183
+#define GCC_QUPV3_WRAP1_S0_CLK					184
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC				185
+#define GCC_QUPV3_WRAP1_S1_CLK					186
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC				187
+#define GCC_QUPV3_WRAP1_S2_CLK					188
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC				189
+#define GCC_QUPV3_WRAP1_S2_DIV_CLK_SRC				190
+#define GCC_QUPV3_WRAP1_S3_CLK					191
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC				192
+#define GCC_QUPV3_WRAP1_S3_DIV_CLK_SRC				193
+#define GCC_QUPV3_WRAP1_S4_CLK					194
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC				195
+#define GCC_QUPV3_WRAP1_S5_CLK					196
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC				197
+#define GCC_QUPV3_WRAP1_S6_CLK					198
+#define GCC_QUPV3_WRAP1_S6_CLK_SRC				199
+#define GCC_QUPV3_WRAP1_S7_CLK					200
+#define GCC_QUPV3_WRAP1_S7_CLK_SRC				201
+#define GCC_QUPV3_WRAP2_CORE_2X_CLK				202
+#define GCC_QUPV3_WRAP2_CORE_CLK				203
+#define GCC_QUPV3_WRAP2_QSPI_S2_CLK				204
+#define GCC_QUPV3_WRAP2_QSPI_S3_CLK				205
+#define GCC_QUPV3_WRAP2_S0_CLK					206
+#define GCC_QUPV3_WRAP2_S0_CLK_SRC				207
+#define GCC_QUPV3_WRAP2_S1_CLK					208
+#define GCC_QUPV3_WRAP2_S1_CLK_SRC				209
+#define GCC_QUPV3_WRAP2_S2_CLK					210
+#define GCC_QUPV3_WRAP2_S2_CLK_SRC				211
+#define GCC_QUPV3_WRAP2_S2_DIV_CLK_SRC				212
+#define GCC_QUPV3_WRAP2_S3_CLK					213
+#define GCC_QUPV3_WRAP2_S3_CLK_SRC				214
+#define GCC_QUPV3_WRAP2_S3_DIV_CLK_SRC				215
+#define GCC_QUPV3_WRAP2_S4_CLK					216
+#define GCC_QUPV3_WRAP2_S4_CLK_SRC				217
+#define GCC_QUPV3_WRAP2_S5_CLK					218
+#define GCC_QUPV3_WRAP2_S5_CLK_SRC				219
+#define GCC_QUPV3_WRAP2_S6_CLK					220
+#define GCC_QUPV3_WRAP2_S6_CLK_SRC				221
+#define GCC_QUPV3_WRAP2_S7_CLK					222
+#define GCC_QUPV3_WRAP2_S7_CLK_SRC				223
+#define GCC_QUPV3_WRAP_0_M_AHB_CLK				224
+#define GCC_QUPV3_WRAP_0_S_AHB_CLK				225
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK				226
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK				227
+#define GCC_QUPV3_WRAP_2_M_AHB_CLK				228
+#define GCC_QUPV3_WRAP_2_S_AHB_CLK				229
+#define GCC_SDCC2_AHB_CLK					230
+#define GCC_SDCC2_APPS_CLK					231
+#define GCC_SDCC2_APPS_CLK_SRC					232
+#define GCC_SDCC4_AHB_CLK					233
+#define GCC_SDCC4_APPS_CLK					234
+#define GCC_SDCC4_APPS_CLK_SRC					235
+#define GCC_SYS_NOC_USB_AXI_CLK					236
+#define GCC_UFS_PHY_AHB_CLK					237
+#define GCC_UFS_PHY_AXI_CLK					238
+#define GCC_UFS_PHY_AXI_CLK_SRC					239
+#define GCC_UFS_PHY_ICE_CORE_CLK				240
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				241
+#define GCC_UFS_PHY_PHY_AUX_CLK					242
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				243
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				244
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				245
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				246
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK				247
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				248
+#define GCC_USB20_MASTER_CLK					249
+#define GCC_USB20_MASTER_CLK_SRC				250
+#define GCC_USB20_MOCK_UTMI_CLK					251
+#define GCC_USB20_MOCK_UTMI_CLK_SRC				252
+#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC			253
+#define GCC_USB20_SLEEP_CLK					254
+#define GCC_USB30_MP_MASTER_CLK					255
+#define GCC_USB30_MP_MASTER_CLK_SRC				256
+#define GCC_USB30_MP_MOCK_UTMI_CLK				257
+#define GCC_USB30_MP_MOCK_UTMI_CLK_SRC				258
+#define GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC			259
+#define GCC_USB30_MP_SLEEP_CLK					260
+#define GCC_USB30_PRIM_MASTER_CLK				261
+#define GCC_USB30_PRIM_MASTER_CLK_SRC				262
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK				263
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			264
+#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC		265
+#define GCC_USB30_PRIM_SLEEP_CLK				266
+#define GCC_USB30_SEC_MASTER_CLK				267
+#define GCC_USB30_SEC_MASTER_CLK_SRC				268
+#define GCC_USB30_SEC_MOCK_UTMI_CLK				269
+#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC				270
+#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC			271
+#define GCC_USB30_SEC_SLEEP_CLK					272
+#define GCC_USB30_TERT_MASTER_CLK				273
+#define GCC_USB30_TERT_MASTER_CLK_SRC				274
+#define GCC_USB30_TERT_MOCK_UTMI_CLK				275
+#define GCC_USB30_TERT_MOCK_UTMI_CLK_SRC			276
+#define GCC_USB30_TERT_MOCK_UTMI_POSTDIV_CLK_SRC		277
+#define GCC_USB30_TERT_SLEEP_CLK				278
+#define GCC_USB3_MP_PHY_AUX_CLK					279
+#define GCC_USB3_MP_PHY_AUX_CLK_SRC				280
+#define GCC_USB3_MP_PHY_COM_AUX_CLK				281
+#define GCC_USB3_MP_PHY_PIPE_0_CLK				282
+#define GCC_USB3_MP_PHY_PIPE_1_CLK				283
+#define GCC_USB3_PRIM_PHY_AUX_CLK				284
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				285
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				286
+#define GCC_USB3_PRIM_PHY_PIPE_CLK				287
+#define GCC_USB3_SEC_PHY_AUX_CLK				288
+#define GCC_USB3_SEC_PHY_AUX_CLK_SRC				289
+#define GCC_USB3_SEC_PHY_COM_AUX_CLK				290
+#define GCC_USB3_SEC_PHY_PIPE_CLK				291
+#define GCC_USB3_TERT_PHY_AUX_CLK				292
+#define GCC_USB3_TERT_PHY_AUX_CLK_SRC				293
+#define GCC_USB3_TERT_PHY_COM_AUX_CLK				294
+#define GCC_USB3_TERT_PHY_PIPE_CLK				295
+#define GCC_USB4_0_CFG_AHB_CLK					296
+#define GCC_USB4_0_DP0_CLK					297
+#define GCC_USB4_0_DP1_CLK					298
+#define GCC_USB4_0_MASTER_CLK					299
+#define GCC_USB4_0_MASTER_CLK_SRC				300
+#define GCC_USB4_0_PHY_P2RR2P_PIPE_CLK				301
+#define GCC_USB4_0_PHY_PCIE_PIPE_CLK				302
+#define GCC_USB4_0_PHY_PCIE_PIPE_CLK_SRC			303
+#define GCC_USB4_0_PHY_RX0_CLK					304
+#define GCC_USB4_0_PHY_RX1_CLK					305
+#define GCC_USB4_0_PHY_USB_PIPE_CLK				306
+#define GCC_USB4_0_SB_IF_CLK					307
+#define GCC_USB4_0_SB_IF_CLK_SRC				308
+#define GCC_USB4_0_SYS_CLK					309
+#define GCC_USB4_0_TMU_CLK					310
+#define GCC_USB4_0_TMU_CLK_SRC					311
+#define GCC_USB4_1_CFG_AHB_CLK					312
+#define GCC_USB4_1_DP0_CLK					313
+#define GCC_USB4_1_DP1_CLK					314
+#define GCC_USB4_1_MASTER_CLK					315
+#define GCC_USB4_1_MASTER_CLK_SRC				316
+#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK				317
+#define GCC_USB4_1_PHY_PCIE_PIPE_CLK				318
+#define GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC			319
+#define GCC_USB4_1_PHY_RX0_CLK					320
+#define GCC_USB4_1_PHY_RX1_CLK					321
+#define GCC_USB4_1_PHY_USB_PIPE_CLK				322
+#define GCC_USB4_1_SB_IF_CLK					323
+#define GCC_USB4_1_SB_IF_CLK_SRC				324
+#define GCC_USB4_1_SYS_CLK					325
+#define GCC_USB4_1_TMU_CLK					326
+#define GCC_USB4_1_TMU_CLK_SRC					327
+#define GCC_USB4_2_CFG_AHB_CLK					328
+#define GCC_USB4_2_DP0_CLK					329
+#define GCC_USB4_2_DP1_CLK					330
+#define GCC_USB4_2_MASTER_CLK					331
+#define GCC_USB4_2_MASTER_CLK_SRC				332
+#define GCC_USB4_2_PHY_P2RR2P_PIPE_CLK				333
+#define GCC_USB4_2_PHY_PCIE_PIPE_CLK				334
+#define GCC_USB4_2_PHY_PCIE_PIPE_CLK_SRC			335
+#define GCC_USB4_2_PHY_RX0_CLK					336
+#define GCC_USB4_2_PHY_RX1_CLK					337
+#define GCC_USB4_2_PHY_USB_PIPE_CLK				338
+#define GCC_USB4_2_SB_IF_CLK					339
+#define GCC_USB4_2_SB_IF_CLK_SRC				340
+#define GCC_USB4_2_SYS_CLK					341
+#define GCC_USB4_2_TMU_CLK					342
+#define GCC_USB4_2_TMU_CLK_SRC					343
+#define GCC_VIDEO_AHB_CLK					344
+#define GCC_VIDEO_AXI0_CLK					345
+#define GCC_VIDEO_AXI1_CLK					346
+#define GCC_VIDEO_XO_CLK					347
+#define GCC_PCIE_3_PIPE_CLK_SRC					348
+#define GCC_PCIE_4_PIPE_CLK_SRC					349
+#define GCC_PCIE_5_PIPE_CLK_SRC					350
+#define GCC_PCIE_6A_PIPE_CLK_SRC				351
+#define GCC_PCIE_6B_PIPE_CLK_SRC				352
+#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC				353
+#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC				354
+#define GCC_USB3_TERT_PHY_PIPE_CLK_SRC				355
+
+/* GCC power domains */
+#define GCC_PCIE_0_TUNNEL_GDSC					0
+#define GCC_PCIE_1_TUNNEL_GDSC					1
+#define GCC_PCIE_2_TUNNEL_GDSC					2
+#define GCC_PCIE_3_GDSC						3
+#define GCC_PCIE_3_PHY_GDSC					4
+#define GCC_PCIE_4_GDSC						5
+#define GCC_PCIE_4_PHY_GDSC					6
+#define GCC_PCIE_5_GDSC						7
+#define GCC_PCIE_5_PHY_GDSC					8
+#define GCC_PCIE_6_PHY_GDSC					9
+#define GCC_PCIE_6A_GDSC					10
+#define GCC_PCIE_6B_GDSC					11
+#define GCC_UFS_MEM_PHY_GDSC					12
+#define GCC_UFS_PHY_GDSC					13
+#define GCC_USB20_PRIM_GDSC					14
+#define GCC_USB30_MP_GDSC					15
+#define GCC_USB30_PRIM_GDSC					16
+#define GCC_USB30_SEC_GDSC					17
+#define GCC_USB30_TERT_GDSC					18
+#define GCC_USB3_MP_SS0_PHY_GDSC				19
+#define GCC_USB3_MP_SS1_PHY_GDSC				20
+#define GCC_USB4_0_GDSC						21
+#define GCC_USB4_1_GDSC						22
+#define GCC_USB4_2_GDSC						23
+#define GCC_USB_0_PHY_GDSC					24
+#define GCC_USB_1_PHY_GDSC					25
+#define GCC_USB_2_PHY_GDSC					26
+
+/* GCC resets */
+#define GCC_AV1E_BCR						0
+#define GCC_CAMERA_BCR						1
+#define GCC_DISPLAY_BCR						2
+#define GCC_GPU_BCR						3
+#define GCC_PCIE_0_LINK_DOWN_BCR				4
+#define GCC_PCIE_0_NOCSR_COM_PHY_BCR				5
+#define GCC_PCIE_0_PHY_BCR					6
+#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR			7
+#define GCC_PCIE_0_TUNNEL_BCR					8
+#define GCC_PCIE_1_LINK_DOWN_BCR				9
+#define GCC_PCIE_1_NOCSR_COM_PHY_BCR				10
+#define GCC_PCIE_1_PHY_BCR					11
+#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR			12
+#define GCC_PCIE_1_TUNNEL_BCR					13
+#define GCC_PCIE_2_LINK_DOWN_BCR				14
+#define GCC_PCIE_2_NOCSR_COM_PHY_BCR				15
+#define GCC_PCIE_2_PHY_BCR					16
+#define GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR			17
+#define GCC_PCIE_2_TUNNEL_BCR					18
+#define GCC_PCIE_3_BCR						19
+#define GCC_PCIE_3_LINK_DOWN_BCR				20
+#define GCC_PCIE_3_NOCSR_COM_PHY_BCR				21
+#define GCC_PCIE_3_PHY_BCR					22
+#define GCC_PCIE_3_PHY_NOCSR_COM_PHY_BCR			23
+#define GCC_PCIE_4_BCR						24
+#define GCC_PCIE_4_LINK_DOWN_BCR				25
+#define GCC_PCIE_4_NOCSR_COM_PHY_BCR				26
+#define GCC_PCIE_4_PHY_BCR					27
+#define GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR			28
+#define GCC_PCIE_5_BCR						29
+#define GCC_PCIE_5_LINK_DOWN_BCR				30
+#define GCC_PCIE_5_NOCSR_COM_PHY_BCR				31
+#define GCC_PCIE_5_PHY_BCR					32
+#define GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR			33
+#define GCC_PCIE_6A_BCR						34
+#define GCC_PCIE_6A_LINK_DOWN_BCR				35
+#define GCC_PCIE_6A_NOCSR_COM_PHY_BCR				36
+#define GCC_PCIE_6A_PHY_BCR					37
+#define GCC_PCIE_6A_PHY_NOCSR_COM_PHY_BCR			38
+#define GCC_PCIE_6B_BCR						39
+#define GCC_PCIE_6B_LINK_DOWN_BCR				40
+#define GCC_PCIE_6B_NOCSR_COM_PHY_BCR				41
+#define GCC_PCIE_6B_PHY_BCR					42
+#define GCC_PCIE_6B_PHY_NOCSR_COM_PHY_BCR			43
+#define GCC_PCIE_PHY_BCR					44
+#define GCC_PCIE_PHY_CFG_AHB_BCR				45
+#define GCC_PCIE_PHY_COM_BCR					46
+#define GCC_PCIE_RSCC_BCR					47
+#define GCC_PDM_BCR						48
+#define GCC_QUPV3_WRAPPER_0_BCR					49
+#define GCC_QUPV3_WRAPPER_1_BCR					50
+#define GCC_QUPV3_WRAPPER_2_BCR					51
+#define GCC_QUSB2PHY_HS0_MP_BCR					52
+#define GCC_QUSB2PHY_HS1_MP_BCR					53
+#define GCC_QUSB2PHY_PRIM_BCR					54
+#define GCC_QUSB2PHY_SEC_BCR					55
+#define GCC_QUSB2PHY_TERT_BCR					56
+#define GCC_QUSB2PHY_USB20_HS_BCR				57
+#define GCC_SDCC2_BCR						58
+#define GCC_SDCC4_BCR						59
+#define GCC_UFS_PHY_BCR						60
+#define GCC_USB20_PRIM_BCR					61
+#define GCC_USB30_MP_BCR					62
+#define GCC_USB30_PRIM_BCR					63
+#define GCC_USB30_SEC_BCR					64
+#define GCC_USB30_TERT_BCR					65
+#define GCC_USB3_MP_SS0_PHY_BCR					66
+#define GCC_USB3_MP_SS1_PHY_BCR					67
+#define GCC_USB3_PHY_PRIM_BCR					68
+#define GCC_USB3_PHY_SEC_BCR					69
+#define GCC_USB3_PHY_TERT_BCR					70
+#define GCC_USB3_UNIPHY_MP0_BCR					71
+#define GCC_USB3_UNIPHY_MP1_BCR					72
+#define GCC_USB3PHY_PHY_PRIM_BCR				73
+#define GCC_USB3PHY_PHY_SEC_BCR					74
+#define GCC_USB3PHY_PHY_TERT_BCR				75
+#define GCC_USB3UNIPHY_PHY_MP0_BCR				76
+#define GCC_USB3UNIPHY_PHY_MP1_BCR				77
+#define GCC_USB4_0_BCR						78
+#define GCC_USB4_0_DP0_PHY_PRIM_BCR				79
+#define GCC_USB4_1_DP0_PHY_SEC_BCR				80
+#define GCC_USB4_2_DP0_PHY_TERT_BCR				81
+#define GCC_USB4_1_BCR						82
+#define GCC_USB4_2_BCR						83
+#define GCC_USB_0_PHY_BCR					84
+#define GCC_USB_1_PHY_BCR					85
+#define GCC_USB_2_PHY_BCR					86
+#define GCC_VIDEO_BCR						87
+#endif
diff --git a/include/dt-bindings/clock/sophgo,cv1800.h b/include/dt-bindings/clock/sophgo,cv1800.h
new file mode 100644
index 00000000000..cfbeca25a65
--- /dev/null
+++ b/include/dt-bindings/clock/sophgo,cv1800.h
@@ -0,0 +1,176 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (C) 2023 Sophgo Ltd.
+ */
+
+#ifndef __DT_BINDINGS_SOPHGO_CV1800_CLK_H__
+#define __DT_BINDINGS_SOPHGO_CV1800_CLK_H__
+
+#define CLK_MPLL			0
+#define CLK_TPLL			1
+#define CLK_FPLL			2
+#define CLK_MIPIMPLL			3
+#define CLK_A0PLL			4
+#define CLK_DISPPLL			5
+#define CLK_CAM0PLL			6
+#define CLK_CAM1PLL			7
+
+#define CLK_MIPIMPLL_D3			8
+#define CLK_CAM0PLL_D2			9
+#define CLK_CAM0PLL_D3			10
+
+#define CLK_TPU				11
+#define CLK_TPU_FAB			12
+#define CLK_AHB_ROM			13
+#define CLK_DDR_AXI_REG			14
+#define CLK_RTC_25M			15
+#define CLK_SRC_RTC_SYS_0		16
+#define CLK_TEMPSEN			17
+#define CLK_SARADC			18
+#define CLK_EFUSE			19
+#define CLK_APB_EFUSE			20
+#define CLK_DEBUG			21
+#define CLK_AP_DEBUG			22
+#define CLK_XTAL_MISC			23
+#define CLK_AXI4_EMMC			24
+#define CLK_EMMC			25
+#define CLK_EMMC_100K			26
+#define CLK_AXI4_SD0			27
+#define CLK_SD0				28
+#define CLK_SD0_100K			29
+#define CLK_AXI4_SD1			30
+#define CLK_SD1				31
+#define CLK_SD1_100K			32
+#define CLK_SPI_NAND			33
+#define CLK_ETH0_500M			34
+#define CLK_AXI4_ETH0			35
+#define CLK_ETH1_500M			36
+#define CLK_AXI4_ETH1			37
+#define CLK_APB_GPIO			38
+#define CLK_APB_GPIO_INTR		39
+#define CLK_GPIO_DB			40
+#define CLK_AHB_SF			41
+#define CLK_AHB_SF1			42
+#define CLK_A24M			43
+#define CLK_AUDSRC			44
+#define CLK_APB_AUDSRC			45
+#define CLK_SDMA_AXI			46
+#define CLK_SDMA_AUD0			47
+#define CLK_SDMA_AUD1			48
+#define CLK_SDMA_AUD2			49
+#define CLK_SDMA_AUD3			50
+#define CLK_I2C				51
+#define CLK_APB_I2C			52
+#define CLK_APB_I2C0			53
+#define CLK_APB_I2C1			54
+#define CLK_APB_I2C2			55
+#define CLK_APB_I2C3			56
+#define CLK_APB_I2C4			57
+#define CLK_APB_WDT			58
+#define CLK_PWM_SRC			59
+#define CLK_PWM				60
+#define CLK_SPI				61
+#define CLK_APB_SPI0			62
+#define CLK_APB_SPI1			63
+#define CLK_APB_SPI2			64
+#define CLK_APB_SPI3			65
+#define CLK_1M				66
+#define CLK_CAM0_200			67
+#define CLK_PM				68
+#define CLK_TIMER0			69
+#define CLK_TIMER1			70
+#define CLK_TIMER2			71
+#define CLK_TIMER3			72
+#define CLK_TIMER4			73
+#define CLK_TIMER5			74
+#define CLK_TIMER6			75
+#define CLK_TIMER7			76
+#define CLK_UART0			77
+#define CLK_APB_UART0			78
+#define CLK_UART1			79
+#define CLK_APB_UART1			80
+#define CLK_UART2			81
+#define CLK_APB_UART2			82
+#define CLK_UART3			83
+#define CLK_APB_UART3			84
+#define CLK_UART4			85
+#define CLK_APB_UART4			86
+#define CLK_APB_I2S0			87
+#define CLK_APB_I2S1			88
+#define CLK_APB_I2S2			89
+#define CLK_APB_I2S3			90
+#define CLK_AXI4_USB			91
+#define CLK_APB_USB			92
+#define CLK_USB_125M			93
+#define CLK_USB_33K			94
+#define CLK_USB_12M			95
+#define CLK_AXI4			96
+#define CLK_AXI6			97
+#define CLK_DSI_ESC			98
+#define CLK_AXI_VIP			99
+#define CLK_SRC_VIP_SYS_0		100
+#define CLK_SRC_VIP_SYS_1		101
+#define CLK_SRC_VIP_SYS_2		102
+#define CLK_SRC_VIP_SYS_3		103
+#define CLK_SRC_VIP_SYS_4		104
+#define CLK_CSI_BE_VIP			105
+#define CLK_CSI_MAC0_VIP		106
+#define CLK_CSI_MAC1_VIP		107
+#define CLK_CSI_MAC2_VIP		108
+#define CLK_CSI0_RX_VIP			109
+#define CLK_CSI1_RX_VIP			110
+#define CLK_ISP_TOP_VIP			111
+#define CLK_IMG_D_VIP			112
+#define CLK_IMG_V_VIP			113
+#define CLK_SC_TOP_VIP			114
+#define CLK_SC_D_VIP			115
+#define CLK_SC_V1_VIP			116
+#define CLK_SC_V2_VIP			117
+#define CLK_SC_V3_VIP			118
+#define CLK_DWA_VIP			119
+#define CLK_BT_VIP			120
+#define CLK_DISP_VIP			121
+#define CLK_DSI_MAC_VIP			122
+#define CLK_LVDS0_VIP			123
+#define CLK_LVDS1_VIP			124
+#define CLK_PAD_VI_VIP			125
+#define CLK_PAD_VI1_VIP			126
+#define CLK_PAD_VI2_VIP			127
+#define CLK_CFG_REG_VIP			128
+#define CLK_VIP_IP0			129
+#define CLK_VIP_IP1			130
+#define CLK_VIP_IP2			131
+#define CLK_VIP_IP3			132
+#define CLK_IVE_VIP			133
+#define CLK_RAW_VIP			134
+#define CLK_OSDC_VIP			135
+#define CLK_CAM0_VIP			136
+#define CLK_AXI_VIDEO_CODEC		137
+#define CLK_VC_SRC0			138
+#define CLK_VC_SRC1			139
+#define CLK_VC_SRC2			140
+#define CLK_H264C			141
+#define CLK_APB_H264C			142
+#define CLK_H265C			143
+#define CLK_APB_H265C			144
+#define CLK_JPEG			145
+#define CLK_APB_JPEG			146
+#define CLK_CAM0			147
+#define CLK_CAM1			148
+#define CLK_WGN				149
+#define CLK_WGN0			150
+#define CLK_WGN1			151
+#define CLK_WGN2			152
+#define CLK_KEYSCAN			153
+#define CLK_CFG_REG_VC			154
+#define CLK_C906_0			155
+#define CLK_C906_1			156
+#define CLK_A53				157
+#define CLK_CPU_AXI0			158
+#define CLK_CPU_GIC			159
+#define CLK_XTAL_AP			160
+
+// Only for CV181x
+#define CLK_DISP_SRC_VIP		161
+
+#endif /* __DT_BINDINGS_SOPHGO_CV1800_CLK_H__ */
diff --git a/include/dt-bindings/clock/st,stm32mp25-rcc.h b/include/dt-bindings/clock/st,stm32mp25-rcc.h
new file mode 100644
index 00000000000..b6cf05ad4be
--- /dev/null
+++ b/include/dt-bindings/clock/st,stm32mp25-rcc.h
@@ -0,0 +1,492 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
+ */
+
+#ifndef _DT_BINDINGS_STM32MP25_CLKS_H_
+#define _DT_BINDINGS_STM32MP25_CLKS_H_
+
+/* INTERNAL/EXTERNAL OSCILLATORS */
+#define HSI_CK			0
+#define HSE_CK			1
+#define MSI_CK			2
+#define LSI_CK			3
+#define LSE_CK			4
+#define I2S_CK			5
+#define RTC_CK			6
+#define SPDIF_CK_SYMB		7
+
+/* PLL CLOCKS */
+#define PLL1_CK			8
+#define PLL2_CK			9
+#define PLL3_CK			10
+#define PLL4_CK			11
+#define PLL5_CK			12
+#define PLL6_CK			13
+#define PLL7_CK			14
+#define PLL8_CK			15
+
+#define CK_CPU1			16
+
+/* APB DIV CLOCKS */
+#define CK_ICN_APB1		17
+#define CK_ICN_APB2		18
+#define CK_ICN_APB3		19
+#define CK_ICN_APB4		20
+#define CK_ICN_APBDBG		21
+
+/* GLOBAL TIMER */
+#define TIMG1_CK		22
+#define TIMG2_CK		23
+
+/* FLEXGEN CLOCKS */
+#define CK_ICN_HS_MCU		24
+#define CK_ICN_SDMMC		25
+#define CK_ICN_DDR		26
+#define CK_ICN_DISPLAY		27
+#define CK_ICN_HSL		28
+#define CK_ICN_NIC		29
+#define CK_ICN_VID		30
+#define CK_FLEXGEN_07		31
+#define CK_FLEXGEN_08		32
+#define CK_FLEXGEN_09		33
+#define CK_FLEXGEN_10		34
+#define CK_FLEXGEN_11		35
+#define CK_FLEXGEN_12		36
+#define CK_FLEXGEN_13		37
+#define CK_FLEXGEN_14		38
+#define CK_FLEXGEN_15		39
+#define CK_FLEXGEN_16		40
+#define CK_FLEXGEN_17		41
+#define CK_FLEXGEN_18		42
+#define CK_FLEXGEN_19		43
+#define CK_FLEXGEN_20		44
+#define CK_FLEXGEN_21		45
+#define CK_FLEXGEN_22		46
+#define CK_FLEXGEN_23		47
+#define CK_FLEXGEN_24		48
+#define CK_FLEXGEN_25		49
+#define CK_FLEXGEN_26		50
+#define CK_FLEXGEN_27		51
+#define CK_FLEXGEN_28		52
+#define CK_FLEXGEN_29		53
+#define CK_FLEXGEN_30		54
+#define CK_FLEXGEN_31		55
+#define CK_FLEXGEN_32		56
+#define CK_FLEXGEN_33		57
+#define CK_FLEXGEN_34		58
+#define CK_FLEXGEN_35		59
+#define CK_FLEXGEN_36		60
+#define CK_FLEXGEN_37		61
+#define CK_FLEXGEN_38		62
+#define CK_FLEXGEN_39		63
+#define CK_FLEXGEN_40		64
+#define CK_FLEXGEN_41		65
+#define CK_FLEXGEN_42		66
+#define CK_FLEXGEN_43		67
+#define CK_FLEXGEN_44		68
+#define CK_FLEXGEN_45		69
+#define CK_FLEXGEN_46		70
+#define CK_FLEXGEN_47		71
+#define CK_FLEXGEN_48		72
+#define CK_FLEXGEN_49		73
+#define CK_FLEXGEN_50		74
+#define CK_FLEXGEN_51		75
+#define CK_FLEXGEN_52		76
+#define CK_FLEXGEN_53		77
+#define CK_FLEXGEN_54		78
+#define CK_FLEXGEN_55		79
+#define CK_FLEXGEN_56		80
+#define CK_FLEXGEN_57		81
+#define CK_FLEXGEN_58		82
+#define CK_FLEXGEN_59		83
+#define CK_FLEXGEN_60		84
+#define CK_FLEXGEN_61		85
+#define CK_FLEXGEN_62		86
+#define CK_FLEXGEN_63		87
+
+/* LOW SPEED MCU CLOCK */
+#define CK_ICN_LS_MCU		88
+
+#define CK_BUS_STM500		89
+#define CK_BUS_FMC		90
+#define CK_BUS_GPU		91
+#define CK_BUS_ETH1		92
+#define CK_BUS_ETH2		93
+#define CK_BUS_PCIE		94
+#define CK_BUS_DDRPHYC		95
+#define CK_BUS_SYSCPU1		96
+#define CK_BUS_ETHSW		97
+#define CK_BUS_HPDMA1		98
+#define CK_BUS_HPDMA2		99
+#define CK_BUS_HPDMA3		100
+#define CK_BUS_ADC12		101
+#define CK_BUS_ADC3		102
+#define CK_BUS_IPCC1		103
+#define CK_BUS_CCI		104
+#define CK_BUS_CRC		105
+#define CK_BUS_MDF1		106
+#define CK_BUS_OSPIIOM		107
+#define CK_BUS_BKPSRAM		108
+#define CK_BUS_HASH		109
+#define CK_BUS_RNG		110
+#define CK_BUS_CRYP1		111
+#define CK_BUS_CRYP2		112
+#define CK_BUS_SAES		113
+#define CK_BUS_PKA		114
+#define CK_BUS_GPIOA		115
+#define CK_BUS_GPIOB		116
+#define CK_BUS_GPIOC		117
+#define CK_BUS_GPIOD		118
+#define CK_BUS_GPIOE		119
+#define CK_BUS_GPIOF		120
+#define CK_BUS_GPIOG		121
+#define CK_BUS_GPIOH		122
+#define CK_BUS_GPIOI		123
+#define CK_BUS_GPIOJ		124
+#define CK_BUS_GPIOK		125
+#define CK_BUS_LPSRAM1		126
+#define CK_BUS_LPSRAM2		127
+#define CK_BUS_LPSRAM3		128
+#define CK_BUS_GPIOZ		129
+#define CK_BUS_LPDMA		130
+#define CK_BUS_HSEM		131
+#define CK_BUS_IPCC2		132
+#define CK_BUS_RTC		133
+#define CK_BUS_SPI8		134
+#define CK_BUS_LPUART1		135
+#define CK_BUS_I2C8		136
+#define CK_BUS_LPTIM3		137
+#define CK_BUS_LPTIM4		138
+#define CK_BUS_LPTIM5		139
+#define CK_BUS_IWDG5		140
+#define CK_BUS_WWDG2		141
+#define CK_BUS_I3C4		142
+#define CK_BUS_TIM2		143
+#define CK_BUS_TIM3		144
+#define CK_BUS_TIM4		145
+#define CK_BUS_TIM5		146
+#define CK_BUS_TIM6		147
+#define CK_BUS_TIM7		148
+#define CK_BUS_TIM10		149
+#define CK_BUS_TIM11		150
+#define CK_BUS_TIM12		151
+#define CK_BUS_TIM13		152
+#define CK_BUS_TIM14		153
+#define CK_BUS_LPTIM1		154
+#define CK_BUS_LPTIM2		155
+#define CK_BUS_SPI2		156
+#define CK_BUS_SPI3		157
+#define CK_BUS_SPDIFRX		158
+#define CK_BUS_USART2		159
+#define CK_BUS_USART3		160
+#define CK_BUS_UART4		161
+#define CK_BUS_UART5		162
+#define CK_BUS_I2C1		163
+#define CK_BUS_I2C2		164
+#define CK_BUS_I2C3		165
+#define CK_BUS_I2C4		166
+#define CK_BUS_I2C5		167
+#define CK_BUS_I2C6		168
+#define CK_BUS_I2C7		169
+#define CK_BUS_I3C1		170
+#define CK_BUS_I3C2		171
+#define CK_BUS_I3C3		172
+#define CK_BUS_TIM1		173
+#define CK_BUS_TIM8		174
+#define CK_BUS_TIM15		175
+#define CK_BUS_TIM16		176
+#define CK_BUS_TIM17		177
+#define CK_BUS_TIM20		178
+#define CK_BUS_SAI1		179
+#define CK_BUS_SAI2		180
+#define CK_BUS_SAI3		181
+#define CK_BUS_SAI4		182
+#define CK_BUS_USART1		183
+#define CK_BUS_USART6		184
+#define CK_BUS_UART7		185
+#define CK_BUS_UART8		186
+#define CK_BUS_UART9		187
+#define CK_BUS_FDCAN		188
+#define CK_BUS_SPI1		189
+#define CK_BUS_SPI4		190
+#define CK_BUS_SPI5		191
+#define CK_BUS_SPI6		192
+#define CK_BUS_SPI7		193
+#define CK_BUS_BSEC		194
+#define CK_BUS_IWDG1		195
+#define CK_BUS_IWDG2		196
+#define CK_BUS_IWDG3		197
+#define CK_BUS_IWDG4		198
+#define CK_BUS_WWDG1		199
+#define CK_BUS_VREF		200
+#define CK_BUS_DTS		201
+#define CK_BUS_SERC		202
+#define CK_BUS_HDP		203
+#define CK_BUS_IS2M		204
+#define CK_BUS_DSI		205
+#define CK_BUS_LTDC		206
+#define CK_BUS_CSI		207
+#define CK_BUS_DCMIPP		208
+#define CK_BUS_DDRC		209
+#define CK_BUS_DDRCFG		210
+#define CK_BUS_GICV2M		211
+#define CK_BUS_USBTC		212
+#define CK_BUS_USB3PCIEPHY	214
+#define CK_BUS_STGEN		215
+#define CK_BUS_VDEC		216
+#define CK_BUS_VENC		217
+#define CK_SYSDBG		218
+#define CK_KER_TIM2		219
+#define CK_KER_TIM3		220
+#define CK_KER_TIM4		221
+#define CK_KER_TIM5		222
+#define CK_KER_TIM6		223
+#define CK_KER_TIM7		224
+#define CK_KER_TIM10		225
+#define CK_KER_TIM11		226
+#define CK_KER_TIM12		227
+#define CK_KER_TIM13		228
+#define CK_KER_TIM14		229
+#define CK_KER_TIM1		230
+#define CK_KER_TIM8		231
+#define CK_KER_TIM15		232
+#define CK_KER_TIM16		233
+#define CK_KER_TIM17		234
+#define CK_KER_TIM20		235
+#define CK_BUS_SYSRAM		236
+#define CK_BUS_VDERAM		237
+#define CK_BUS_RETRAM		238
+#define CK_BUS_OSPI1		239
+#define CK_BUS_OSPI2		240
+#define CK_BUS_OTFD1		241
+#define CK_BUS_OTFD2		242
+#define CK_BUS_SRAM1		243
+#define CK_BUS_SRAM2		244
+#define CK_BUS_SDMMC1		245
+#define CK_BUS_SDMMC2		246
+#define CK_BUS_SDMMC3		247
+#define CK_BUS_DDR		248
+#define CK_BUS_RISAF4		249
+#define CK_BUS_USB2OHCI		250
+#define CK_BUS_USB2EHCI		251
+#define CK_BUS_USB3DR		252
+#define CK_KER_LPTIM1		253
+#define CK_KER_LPTIM2		254
+#define CK_KER_USART2		255
+#define CK_KER_UART4		256
+#define CK_KER_USART3		257
+#define CK_KER_UART5		258
+#define CK_KER_SPI2		259
+#define CK_KER_SPI3		260
+#define CK_KER_SPDIFRX		261
+#define CK_KER_I2C1		262
+#define CK_KER_I2C2		263
+#define CK_KER_I3C1		264
+#define CK_KER_I3C2		265
+#define CK_KER_I2C3		266
+#define CK_KER_I2C5		267
+#define CK_KER_I3C3		268
+#define CK_KER_I2C4		269
+#define CK_KER_I2C6		270
+#define CK_KER_I2C7		271
+#define CK_KER_SPI1		272
+#define CK_KER_SPI4		273
+#define CK_KER_SPI5		274
+#define CK_KER_SPI6		275
+#define CK_KER_SPI7		276
+#define CK_KER_USART1		277
+#define CK_KER_USART6		278
+#define CK_KER_UART7		279
+#define CK_KER_UART8		280
+#define CK_KER_UART9		281
+#define CK_KER_MDF1		282
+#define CK_KER_SAI1		283
+#define CK_KER_SAI2		284
+#define CK_KER_SAI3		285
+#define CK_KER_SAI4		286
+#define CK_KER_FDCAN		287
+#define CK_KER_DSIBLANE		288
+#define CK_KER_DSIPHY		289
+#define CK_KER_CSI		290
+#define CK_KER_CSITXESC		291
+#define CK_KER_CSIPHY		292
+#define CK_KER_LVDSPHY		293
+#define CK_KER_STGEN		294
+#define CK_KER_USB3PCIEPHY	295
+#define CK_KER_USB2PHY2EN	296
+#define CK_KER_I3C4		297
+#define CK_KER_SPI8		298
+#define CK_KER_I2C8		299
+#define CK_KER_LPUART1		300
+#define CK_KER_LPTIM3		301
+#define CK_KER_LPTIM4		302
+#define CK_KER_LPTIM5		303
+#define CK_KER_TSDBG		304
+#define CK_KER_TPIU		305
+#define CK_BUS_ETR		306
+#define CK_BUS_SYSATB		307
+#define CK_KER_ADC12		308
+#define CK_KER_ADC3		309
+#define CK_KER_OSPI1		310
+#define CK_KER_OSPI2		311
+#define CK_KER_FMC		312
+#define CK_KER_SDMMC1		313
+#define CK_KER_SDMMC2		314
+#define CK_KER_SDMMC3		315
+#define CK_KER_ETH1		316
+#define CK_KER_ETH2		317
+#define CK_KER_ETH1PTP		318
+#define CK_KER_ETH2PTP		319
+#define CK_KER_USB2PHY1		320
+#define CK_KER_USB2PHY2		321
+#define CK_KER_ETHSW		322
+#define CK_KER_ETHSWREF		323
+#define CK_MCO1			324
+#define CK_MCO2			325
+#define CK_KER_DTS		326
+#define CK_ETH1_RX		327
+#define CK_ETH1_TX		328
+#define CK_ETH1_MAC		329
+#define CK_ETH2_RX		330
+#define CK_ETH2_TX		331
+#define CK_ETH2_MAC		332
+#define CK_ETH1_STP		333
+#define CK_ETH2_STP		334
+#define CK_KER_USBTC		335
+#define CK_BUS_ADF1		336
+#define CK_KER_ADF1		337
+#define CK_BUS_LVDS		338
+#define CK_KER_LTDC		339
+#define CK_KER_GPU		340
+#define CK_BUS_ETHSWACMCFG	341
+#define CK_BUS_ETHSWACMMSG	342
+#define HSE_DIV2_CK		343
+
+#define STM32MP25_LAST_CLK	344
+
+#define CK_SCMI_ICN_HS_MCU	0
+#define CK_SCMI_ICN_SDMMC	1
+#define CK_SCMI_ICN_DDR		2
+#define CK_SCMI_ICN_DISPLAY	3
+#define CK_SCMI_ICN_HSL		4
+#define CK_SCMI_ICN_NIC		5
+#define CK_SCMI_ICN_VID		6
+#define CK_SCMI_FLEXGEN_07	7
+#define CK_SCMI_FLEXGEN_08	8
+#define CK_SCMI_FLEXGEN_09	9
+#define CK_SCMI_FLEXGEN_10	10
+#define CK_SCMI_FLEXGEN_11	11
+#define CK_SCMI_FLEXGEN_12	12
+#define CK_SCMI_FLEXGEN_13	13
+#define CK_SCMI_FLEXGEN_14	14
+#define CK_SCMI_FLEXGEN_15	15
+#define CK_SCMI_FLEXGEN_16	16
+#define CK_SCMI_FLEXGEN_17	17
+#define CK_SCMI_FLEXGEN_18	18
+#define CK_SCMI_FLEXGEN_19	19
+#define CK_SCMI_FLEXGEN_20	20
+#define CK_SCMI_FLEXGEN_21	21
+#define CK_SCMI_FLEXGEN_22	22
+#define CK_SCMI_FLEXGEN_23	23
+#define CK_SCMI_FLEXGEN_24	24
+#define CK_SCMI_FLEXGEN_25	25
+#define CK_SCMI_FLEXGEN_26	26
+#define CK_SCMI_FLEXGEN_27	27
+#define CK_SCMI_FLEXGEN_28	28
+#define CK_SCMI_FLEXGEN_29	29
+#define CK_SCMI_FLEXGEN_30	30
+#define CK_SCMI_FLEXGEN_31	31
+#define CK_SCMI_FLEXGEN_32	32
+#define CK_SCMI_FLEXGEN_33	33
+#define CK_SCMI_FLEXGEN_34	34
+#define CK_SCMI_FLEXGEN_35	35
+#define CK_SCMI_FLEXGEN_36	36
+#define CK_SCMI_FLEXGEN_37	37
+#define CK_SCMI_FLEXGEN_38	38
+#define CK_SCMI_FLEXGEN_39	39
+#define CK_SCMI_FLEXGEN_40	40
+#define CK_SCMI_FLEXGEN_41	41
+#define CK_SCMI_FLEXGEN_42	42
+#define CK_SCMI_FLEXGEN_43	43
+#define CK_SCMI_FLEXGEN_44	44
+#define CK_SCMI_FLEXGEN_45	45
+#define CK_SCMI_FLEXGEN_46	46
+#define CK_SCMI_FLEXGEN_47	47
+#define CK_SCMI_FLEXGEN_48	48
+#define CK_SCMI_FLEXGEN_49	49
+#define CK_SCMI_FLEXGEN_50	50
+#define CK_SCMI_FLEXGEN_51	51
+#define CK_SCMI_FLEXGEN_52	52
+#define CK_SCMI_FLEXGEN_53	53
+#define CK_SCMI_FLEXGEN_54	54
+#define CK_SCMI_FLEXGEN_55	55
+#define CK_SCMI_FLEXGEN_56	56
+#define CK_SCMI_FLEXGEN_57	57
+#define CK_SCMI_FLEXGEN_58	58
+#define CK_SCMI_FLEXGEN_59	59
+#define CK_SCMI_FLEXGEN_60	60
+#define CK_SCMI_FLEXGEN_61	61
+#define CK_SCMI_FLEXGEN_62	62
+#define CK_SCMI_FLEXGEN_63	63
+#define CK_SCMI_ICN_LS_MCU	64
+#define CK_SCMI_HSE		65
+#define CK_SCMI_LSE		66
+#define CK_SCMI_HSI		67
+#define CK_SCMI_LSI		68
+#define CK_SCMI_MSI		69
+#define CK_SCMI_HSE_DIV2	70
+#define CK_SCMI_CPU1		71
+#define CK_SCMI_SYSCPU1		72
+#define CK_SCMI_PLL2		73
+#define CK_SCMI_PLL3		74
+#define CK_SCMI_RTC		75
+#define CK_SCMI_RTCCK		76
+#define CK_SCMI_ICN_APB1	77
+#define CK_SCMI_ICN_APB2	78
+#define CK_SCMI_ICN_APB3	79
+#define CK_SCMI_ICN_APB4	80
+#define CK_SCMI_ICN_APBDBG	81
+#define CK_SCMI_TIMG1		82
+#define CK_SCMI_TIMG2		83
+#define CK_SCMI_BKPSRAM		84
+#define CK_SCMI_BSEC		85
+#define CK_SCMI_ETR		87
+#define CK_SCMI_FMC		88
+#define CK_SCMI_GPIOA		89
+#define CK_SCMI_GPIOB		90
+#define CK_SCMI_GPIOC		91
+#define CK_SCMI_GPIOD		92
+#define CK_SCMI_GPIOE		93
+#define CK_SCMI_GPIOF		94
+#define CK_SCMI_GPIOG		95
+#define CK_SCMI_GPIOH		96
+#define CK_SCMI_GPIOI		97
+#define CK_SCMI_GPIOJ		98
+#define CK_SCMI_GPIOK		99
+#define CK_SCMI_GPIOZ		100
+#define CK_SCMI_HPDMA1		101
+#define CK_SCMI_HPDMA2		102
+#define CK_SCMI_HPDMA3		103
+#define CK_SCMI_HSEM		104
+#define CK_SCMI_IPCC1		105
+#define CK_SCMI_IPCC2		106
+#define CK_SCMI_LPDMA		107
+#define CK_SCMI_RETRAM		108
+#define CK_SCMI_SRAM1		109
+#define CK_SCMI_SRAM2		110
+#define CK_SCMI_LPSRAM1		111
+#define CK_SCMI_LPSRAM2		112
+#define CK_SCMI_LPSRAM3		113
+#define CK_SCMI_VDERAM		114
+#define CK_SCMI_SYSRAM		115
+#define CK_SCMI_OSPI1		116
+#define CK_SCMI_OSPI2		117
+#define CK_SCMI_TPIU		118
+#define CK_SCMI_SYSDBG		119
+#define CK_SCMI_SYSATB		120
+#define CK_SCMI_TSDBG		121
+#define CK_SCMI_STM500		122
+
+#endif /* _DT_BINDINGS_STM32MP25_CLKS_H_ */
diff --git a/include/dt-bindings/dma/fsl-edma.h b/include/dt-bindings/dma/fsl-edma.h
new file mode 100644
index 00000000000..fd11478cfe9
--- /dev/null
+++ b/include/dt-bindings/dma/fsl-edma.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+
+#ifndef _FSL_EDMA_DT_BINDING_H_
+#define _FSL_EDMA_DT_BINDING_H_
+
+/* Receive Channel */
+#define FSL_EDMA_RX		0x1
+
+/* iMX8 audio remote DMA */
+#define FSL_EDMA_REMOTE		0x2
+
+/* FIFO is continue memory region */
+#define FSL_EDMA_MULTI_FIFO	0x4
+
+/* Channel need stick to even channel */
+#define FSL_EDMA_EVEN_CH	0x8
+
+/* Channel need stick to odd channel */
+#define FSL_EDMA_ODD_CH		0x10
+
+#endif
diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pm7325.h b/include/dt-bindings/iio/qcom,spmi-adc7-pm7325.h
new file mode 100644
index 00000000000..96908014e09
--- /dev/null
+++ b/include/dt-bindings/iio/qcom,spmi-adc7-pm7325.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM7325_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_PM7325_H
+
+#ifndef PM7325_SID
+#define PM7325_SID					1
+#endif
+
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+
+/* ADC channels for PM7325_ADC for PMIC7 */
+#define PM7325_ADC7_REF_GND			(PM7325_SID << 8 | ADC7_REF_GND)
+#define PM7325_ADC7_1P25VREF			(PM7325_SID << 8 | ADC7_1P25VREF)
+#define PM7325_ADC7_VREF_VADC			(PM7325_SID << 8 | ADC7_VREF_VADC)
+#define PM7325_ADC7_DIE_TEMP			(PM7325_SID << 8 | ADC7_DIE_TEMP)
+
+#define PM7325_ADC7_AMUX_THM1			(PM7325_SID << 8 | ADC7_AMUX_THM1)
+#define PM7325_ADC7_AMUX_THM2			(PM7325_SID << 8 | ADC7_AMUX_THM2)
+#define PM7325_ADC7_AMUX_THM3			(PM7325_SID << 8 | ADC7_AMUX_THM3)
+#define PM7325_ADC7_AMUX_THM4			(PM7325_SID << 8 | ADC7_AMUX_THM4)
+#define PM7325_ADC7_AMUX_THM5			(PM7325_SID << 8 | ADC7_AMUX_THM5)
+#define PM7325_ADC7_GPIO1			(PM7325_SID << 8 | ADC7_GPIO1)
+#define PM7325_ADC7_GPIO2			(PM7325_SID << 8 | ADC7_GPIO2)
+#define PM7325_ADC7_GPIO3			(PM7325_SID << 8 | ADC7_GPIO3)
+#define PM7325_ADC7_GPIO4			(PM7325_SID << 8 | ADC7_GPIO4)
+
+/* 30k pull-up1 */
+#define PM7325_ADC7_AMUX_THM1_30K_PU		(PM7325_SID << 8 | ADC7_AMUX_THM1_30K_PU)
+#define PM7325_ADC7_AMUX_THM2_30K_PU		(PM7325_SID << 8 | ADC7_AMUX_THM2_30K_PU)
+#define PM7325_ADC7_AMUX_THM3_30K_PU		(PM7325_SID << 8 | ADC7_AMUX_THM3_30K_PU)
+#define PM7325_ADC7_AMUX_THM4_30K_PU		(PM7325_SID << 8 | ADC7_AMUX_THM4_30K_PU)
+#define PM7325_ADC7_AMUX_THM5_30K_PU		(PM7325_SID << 8 | ADC7_AMUX_THM5_30K_PU)
+#define PM7325_ADC7_GPIO1_30K_PU		(PM7325_SID << 8 | ADC7_GPIO1_30K_PU)
+#define PM7325_ADC7_GPIO2_30K_PU		(PM7325_SID << 8 | ADC7_GPIO2_30K_PU)
+#define PM7325_ADC7_GPIO3_30K_PU		(PM7325_SID << 8 | ADC7_GPIO3_30K_PU)
+#define PM7325_ADC7_GPIO4_30K_PU		(PM7325_SID << 8 | ADC7_GPIO4_30K_PU)
+
+/* 100k pull-up2 */
+#define PM7325_ADC7_AMUX_THM1_100K_PU		(PM7325_SID << 8 | ADC7_AMUX_THM1_100K_PU)
+#define PM7325_ADC7_AMUX_THM2_100K_PU		(PM7325_SID << 8 | ADC7_AMUX_THM2_100K_PU)
+#define PM7325_ADC7_AMUX_THM3_100K_PU		(PM7325_SID << 8 | ADC7_AMUX_THM3_100K_PU)
+#define PM7325_ADC7_AMUX_THM4_100K_PU		(PM7325_SID << 8 | ADC7_AMUX_THM4_100K_PU)
+#define PM7325_ADC7_AMUX_THM5_100K_PU		(PM7325_SID << 8 | ADC7_AMUX_THM5_100K_PU)
+#define PM7325_ADC7_GPIO1_100K_PU		(PM7325_SID << 8 | ADC7_GPIO1_100K_PU)
+#define PM7325_ADC7_GPIO2_100K_PU		(PM7325_SID << 8 | ADC7_GPIO2_100K_PU)
+#define PM7325_ADC7_GPIO3_100K_PU		(PM7325_SID << 8 | ADC7_GPIO3_100K_PU)
+#define PM7325_ADC7_GPIO4_100K_PU		(PM7325_SID << 8 | ADC7_GPIO4_100K_PU)
+
+/* 400k pull-up3 */
+#define PM7325_ADC7_AMUX_THM1_400K_PU		(PM7325_SID << 8 | ADC7_AMUX_THM1_400K_PU)
+#define PM7325_ADC7_AMUX_THM2_400K_PU		(PM7325_SID << 8 | ADC7_AMUX_THM2_400K_PU)
+#define PM7325_ADC7_AMUX_THM3_400K_PU		(PM7325_SID << 8 | ADC7_AMUX_THM3_400K_PU)
+#define PM7325_ADC7_AMUX_THM4_400K_PU		(PM7325_SID << 8 | ADC7_AMUX_THM4_400K_PU)
+#define PM7325_ADC7_AMUX_THM5_400K_PU		(PM7325_SID << 8 | ADC7_AMUX_THM5_400K_PU)
+#define PM7325_ADC7_GPIO1_400K_PU		(PM7325_SID << 8 | ADC7_GPIO1_400K_PU)
+#define PM7325_ADC7_GPIO2_400K_PU		(PM7325_SID << 8 | ADC7_GPIO2_400K_PU)
+#define PM7325_ADC7_GPIO3_400K_PU		(PM7325_SID << 8 | ADC7_GPIO3_400K_PU)
+#define PM7325_ADC7_GPIO4_400K_PU		(PM7325_SID << 8 | ADC7_GPIO4_400K_PU)
+
+/* 1/3 Divider */
+#define PM7325_ADC7_GPIO4_DIV3			(PM7325_SID << 8 | ADC7_GPIO4_DIV3)
+
+#define PM7325_ADC7_VPH_PWR			(PM7325_SID << 8 | ADC7_VPH_PWR)
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM7325_H */
diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-smb139x.h b/include/dt-bindings/iio/qcom,spmi-adc7-smb139x.h
new file mode 100644
index 00000000000..c0680d1285c
--- /dev/null
+++ b/include/dt-bindings/iio/qcom,spmi-adc7-smb139x.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
+/*
+ * Copyright (c) 2020 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_SMB139X_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_SMB139X_H
+
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+
+#define SMB139x_1_ADC7_SMB_TEMP			(SMB139x_1_SID << 8 | ADC7_SMB_TEMP)
+#define SMB139x_1_ADC7_ICHG_SMB			(SMB139x_1_SID << 8 | ADC7_ICHG_SMB)
+#define SMB139x_1_ADC7_IIN_SMB			(SMB139x_1_SID << 8 | ADC7_IIN_SMB)
+
+#define SMB139x_2_ADC7_SMB_TEMP			(SMB139x_2_SID << 8 | ADC7_SMB_TEMP)
+#define SMB139x_2_ADC7_ICHG_SMB			(SMB139x_2_SID << 8 | ADC7_ICHG_SMB)
+#define SMB139x_2_ADC7_IIN_SMB			(SMB139x_2_SID << 8 | ADC7_IIN_SMB)
+
+#endif
diff --git a/include/dt-bindings/iio/qcom,spmi-vadc.h b/include/dt-bindings/iio/qcom,spmi-vadc.h
index 08adfe25964..ef07ecd4d58 100644
--- a/include/dt-bindings/iio/qcom,spmi-vadc.h
+++ b/include/dt-bindings/iio/qcom,spmi-vadc.h
@@ -239,12 +239,15 @@
 #define ADC7_GPIO3				0x0c
 #define ADC7_GPIO4				0x0d
 
+#define ADC7_SMB_TEMP				0x06
 #define ADC7_CHG_TEMP				0x10
 #define ADC7_USB_IN_V_16			0x11
 #define ADC7_VDC_16				0x12
 #define ADC7_CC1_ID				0x13
 #define ADC7_VREF_BAT_THERM			0x15
 #define ADC7_IIN_FB				0x17
+#define ADC7_ICHG_SMB				0x18
+#define ADC7_IIN_SMB				0x19
 
 /* 30k pull-up1 */
 #define ADC7_AMUX_THM1_30K_PU			0x24
diff --git a/include/dt-bindings/interconnect/qcom,sm6115.h b/include/dt-bindings/interconnect/qcom,sm6115.h
new file mode 100644
index 00000000000..21090e585f0
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,sm6115.h
@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM6115_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_SM6115_H
+
+/* BIMC */
+#define MASTER_AMPSS_M0				0
+#define MASTER_SNOC_BIMC_RT			1
+#define MASTER_SNOC_BIMC_NRT			2
+#define SNOC_BIMC_MAS				3
+#define MASTER_GRAPHICS_3D			4
+#define MASTER_TCU_0				5
+#define SLAVE_EBI_CH0				6
+#define BIMC_SNOC_SLV				7
+
+/* CNOC */
+#define SNOC_CNOC_MAS				0
+#define MASTER_QDSS_DAP				1
+#define SLAVE_AHB2PHY_USB			2
+#define SLAVE_APSS_THROTTLE_CFG			3
+#define SLAVE_BIMC_CFG				4
+#define SLAVE_BOOT_ROM				5
+#define SLAVE_CAMERA_NRT_THROTTLE_CFG		6
+#define SLAVE_CAMERA_RT_THROTTLE_CFG		7
+#define SLAVE_CAMERA_CFG			8
+#define SLAVE_CLK_CTL				9
+#define SLAVE_RBCPR_CX_CFG			10
+#define SLAVE_RBCPR_MX_CFG			11
+#define SLAVE_CRYPTO_0_CFG			12
+#define SLAVE_DCC_CFG				13
+#define SLAVE_DDR_PHY_CFG			14
+#define SLAVE_DDR_SS_CFG			15
+#define SLAVE_DISPLAY_CFG			16
+#define SLAVE_DISPLAY_THROTTLE_CFG		17
+#define SLAVE_GPU_CFG				18
+#define SLAVE_GPU_THROTTLE_CFG			19
+#define SLAVE_HWKM_CORE				20
+#define SLAVE_IMEM_CFG				21
+#define SLAVE_IPA_CFG				22
+#define SLAVE_LPASS				23
+#define SLAVE_MAPSS				24
+#define SLAVE_MDSP_MPU_CFG			25
+#define SLAVE_MESSAGE_RAM			26
+#define SLAVE_CNOC_MSS				27
+#define SLAVE_PDM				28
+#define SLAVE_PIMEM_CFG				29
+#define SLAVE_PKA_CORE				30
+#define SLAVE_PMIC_ARB				31
+#define SLAVE_QDSS_CFG				32
+#define SLAVE_QM_CFG				33
+#define SLAVE_QM_MPU_CFG			34
+#define SLAVE_QPIC				35
+#define SLAVE_QUP_0				36
+#define SLAVE_RPM				37
+#define SLAVE_SDCC_1				38
+#define SLAVE_SDCC_2				39
+#define SLAVE_SECURITY				40
+#define SLAVE_SNOC_CFG				41
+#define SLAVE_TCSR				42
+#define SLAVE_TLMM				43
+#define SLAVE_USB3				44
+#define SLAVE_VENUS_CFG				45
+#define SLAVE_VENUS_THROTTLE_CFG		46
+#define SLAVE_VSENSE_CTRL_CFG			47
+#define SLAVE_SERVICE_CNOC			48
+
+/* SNOC */
+#define MASTER_CRYPTO_CORE0			0
+#define MASTER_SNOC_CFG				1
+#define MASTER_TIC				2
+#define MASTER_ANOC_SNOC			3
+#define BIMC_SNOC_MAS				4
+#define MASTER_PIMEM				5
+#define MASTER_QDSS_BAM				6
+#define MASTER_QPIC				7
+#define MASTER_QUP_0				8
+#define MASTER_IPA				9
+#define MASTER_QDSS_ETR				10
+#define MASTER_SDCC_1				11
+#define MASTER_SDCC_2				12
+#define MASTER_USB3				13
+#define SLAVE_APPSS				14
+#define SNOC_CNOC_SLV				15
+#define SLAVE_OCIMEM				16
+#define SLAVE_PIMEM				17
+#define SNOC_BIMC_SLV				18
+#define SLAVE_SERVICE_SNOC			19
+#define SLAVE_QDSS_STM				20
+#define SLAVE_TCU				21
+#define SLAVE_ANOC_SNOC				22
+
+/* CLK Virtual */
+#define MASTER_QUP_CORE_0			0
+#define SLAVE_QUP_CORE_0			1
+
+/* MMRT Virtual */
+#define MASTER_CAMNOC_HF			0
+#define MASTER_MDP_PORT0			1
+#define SLAVE_SNOC_BIMC_RT			2
+
+/* MMNRT Virtual */
+#define MASTER_CAMNOC_SF			0
+#define MASTER_VIDEO_P0				1
+#define MASTER_VIDEO_PROC			2
+#define SLAVE_SNOC_BIMC_NRT			3
+
+#endif
diff --git a/include/dt-bindings/interconnect/qcom,sm8650-rpmh.h b/include/dt-bindings/interconnect/qcom,sm8650-rpmh.h
new file mode 100644
index 00000000000..6c1eaf04e24
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,sm8650-rpmh.h
@@ -0,0 +1,154 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8650_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8650_H
+
+#define MASTER_QSPI_0				0
+#define MASTER_QUP_1				1
+#define MASTER_QUP_3				2
+#define MASTER_SDCC_4				3
+#define MASTER_UFS_MEM				4
+#define MASTER_USB3_0				5
+#define SLAVE_A1NOC_SNOC			6
+
+#define MASTER_QDSS_BAM				0
+#define MASTER_QUP_2				1
+#define MASTER_CRYPTO				2
+#define MASTER_IPA				3
+#define MASTER_SP				4
+#define MASTER_QDSS_ETR				5
+#define MASTER_QDSS_ETR_1			6
+#define MASTER_SDCC_2				7
+#define SLAVE_A2NOC_SNOC			8
+
+#define MASTER_QUP_CORE_0			0
+#define MASTER_QUP_CORE_1			1
+#define MASTER_QUP_CORE_2			2
+#define SLAVE_QUP_CORE_0			3
+#define SLAVE_QUP_CORE_1			4
+#define SLAVE_QUP_CORE_2			5
+
+#define MASTER_CNOC_CFG				0
+#define SLAVE_AHB2PHY_SOUTH			1
+#define SLAVE_AHB2PHY_NORTH			2
+#define SLAVE_CAMERA_CFG			3
+#define SLAVE_CLK_CTL				4
+#define SLAVE_RBCPR_CX_CFG			5
+#define SLAVE_CPR_HMX				6
+#define SLAVE_RBCPR_MMCX_CFG			7
+#define SLAVE_RBCPR_MXA_CFG			8
+#define SLAVE_RBCPR_MXC_CFG			9
+#define SLAVE_CPR_NSPCX				10
+#define SLAVE_CRYPTO_0_CFG			11
+#define SLAVE_CX_RDPM				12
+#define SLAVE_DISPLAY_CFG			13
+#define SLAVE_GFX3D_CFG				14
+#define SLAVE_I2C				15
+#define SLAVE_I3C_IBI0_CFG			16
+#define SLAVE_I3C_IBI1_CFG			17
+#define SLAVE_IMEM_CFG				18
+#define SLAVE_CNOC_MSS				19
+#define SLAVE_MX_2_RDPM				20
+#define SLAVE_MX_RDPM				21
+#define SLAVE_PCIE_0_CFG			22
+#define SLAVE_PCIE_1_CFG			23
+#define SLAVE_PCIE_RSCC				24
+#define SLAVE_PDM				25
+#define SLAVE_PRNG				26
+#define SLAVE_QDSS_CFG				27
+#define SLAVE_QSPI_0				28
+#define SLAVE_QUP_3				29
+#define SLAVE_QUP_1				30
+#define SLAVE_QUP_2				31
+#define SLAVE_SDCC_2				32
+#define SLAVE_SDCC_4				33
+#define SLAVE_SPSS_CFG				34
+#define SLAVE_TCSR				35
+#define SLAVE_TLMM				36
+#define SLAVE_UFS_MEM_CFG			37
+#define SLAVE_USB3_0				38
+#define SLAVE_VENUS_CFG				39
+#define SLAVE_VSENSE_CTRL_CFG			40
+#define SLAVE_CNOC_MNOC_CFG			41
+#define SLAVE_NSP_QTB_CFG			42
+#define SLAVE_PCIE_ANOC_CFG			43
+#define SLAVE_SERVICE_CNOC_CFG			44
+#define SLAVE_QDSS_STM				45
+#define SLAVE_TCU				46
+
+#define MASTER_GEM_NOC_CNOC			0
+#define MASTER_GEM_NOC_PCIE_SNOC		1
+#define SLAVE_AOSS				2
+#define SLAVE_IPA_CFG				3
+#define SLAVE_IPC_ROUTER_CFG			4
+#define SLAVE_TME_CFG				5
+#define SLAVE_APPSS				6
+#define SLAVE_CNOC_CFG				7
+#define SLAVE_DDRSS_CFG				8
+#define SLAVE_IMEM				9
+#define SLAVE_SERVICE_CNOC			10
+#define SLAVE_PCIE_0				11
+#define SLAVE_PCIE_1				12
+
+#define MASTER_GPU_TCU				0
+#define MASTER_SYS_TCU				1
+#define MASTER_UBWC_P_TCU			2
+#define MASTER_APPSS_PROC			3
+#define MASTER_GFX3D				4
+#define MASTER_LPASS_GEM_NOC			5
+#define MASTER_MSS_PROC				6
+#define MASTER_MNOC_HF_MEM_NOC			7
+#define MASTER_MNOC_SF_MEM_NOC			8
+#define MASTER_COMPUTE_NOC			9
+#define MASTER_ANOC_PCIE_GEM_NOC		10
+#define MASTER_SNOC_SF_MEM_NOC			11
+#define MASTER_UBWC_P				12
+#define MASTER_GIC				13
+#define SLAVE_GEM_NOC_CNOC			14
+#define SLAVE_LLCC				15
+#define SLAVE_MEM_NOC_PCIE_SNOC			16
+
+#define MASTER_LPIAON_NOC			0
+#define SLAVE_LPASS_GEM_NOC			1
+
+#define MASTER_LPASS_LPINOC			0
+#define SLAVE_LPIAON_NOC_LPASS_AG_NOC		1
+
+#define MASTER_LPASS_PROC			0
+#define SLAVE_LPICX_NOC_LPIAON_NOC		1
+
+#define MASTER_LLCC				0
+#define SLAVE_EBI1				1
+
+#define MASTER_CAMNOC_HF			0
+#define MASTER_CAMNOC_ICP			1
+#define MASTER_CAMNOC_SF			2
+#define MASTER_MDP				3
+#define MASTER_CDSP_HCP				4
+#define MASTER_VIDEO				5
+#define MASTER_VIDEO_CV_PROC			6
+#define MASTER_VIDEO_PROC			7
+#define MASTER_VIDEO_V_PROC			8
+#define MASTER_CNOC_MNOC_CFG			9
+#define SLAVE_MNOC_HF_MEM_NOC			10
+#define SLAVE_MNOC_SF_MEM_NOC			11
+#define SLAVE_SERVICE_MNOC			12
+
+#define MASTER_CDSP_PROC			0
+#define SLAVE_CDSP_MEM_NOC			1
+
+#define MASTER_PCIE_ANOC_CFG			0
+#define MASTER_PCIE_0				1
+#define MASTER_PCIE_1				2
+#define SLAVE_ANOC_PCIE_GEM_NOC			3
+#define SLAVE_SERVICE_PCIE_ANOC			4
+
+#define MASTER_A1NOC_SNOC			0
+#define MASTER_A2NOC_SNOC			1
+#define SLAVE_SNOC_GEM_NOC_SF			2
+
+#endif
diff --git a/include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h b/include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h
new file mode 100644
index 00000000000..a38c3472698
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h
@@ -0,0 +1,207 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_X1E80100_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_X1E80100_H
+
+#define MASTER_QSPI_0				0
+#define MASTER_QUP_1				1
+#define MASTER_SDCC_4				2
+#define MASTER_UFS_MEM				3
+#define SLAVE_A1NOC_SNOC			4
+
+#define MASTER_QUP_0				0
+#define MASTER_QUP_2				1
+#define MASTER_CRYPTO				2
+#define MASTER_SP				3
+#define MASTER_QDSS_ETR				4
+#define MASTER_QDSS_ETR_1			5
+#define MASTER_SDCC_2				6
+#define SLAVE_A2NOC_SNOC			7
+
+#define MASTER_DDR_PERF_MODE			0
+#define MASTER_QUP_CORE_0			1
+#define MASTER_QUP_CORE_1			2
+#define MASTER_QUP_CORE_2			3
+#define SLAVE_DDR_PERF_MODE			4
+#define SLAVE_QUP_CORE_0			5
+#define SLAVE_QUP_CORE_1			6
+#define SLAVE_QUP_CORE_2			7
+
+#define MASTER_CNOC_CFG				0
+#define SLAVE_AHB2PHY_SOUTH			1
+#define SLAVE_AHB2PHY_NORTH			2
+#define SLAVE_AHB2PHY_2				3
+#define SLAVE_AV1_ENC_CFG			4
+#define SLAVE_CAMERA_CFG			5
+#define SLAVE_CLK_CTL				6
+#define SLAVE_CRYPTO_0_CFG			7
+#define SLAVE_DISPLAY_CFG			8
+#define SLAVE_GFX3D_CFG				9
+#define SLAVE_IMEM_CFG				10
+#define SLAVE_IPC_ROUTER_CFG			11
+#define SLAVE_PCIE_0_CFG			12
+#define SLAVE_PCIE_1_CFG			13
+#define SLAVE_PCIE_2_CFG			14
+#define SLAVE_PCIE_3_CFG			15
+#define SLAVE_PCIE_4_CFG			16
+#define SLAVE_PCIE_5_CFG			17
+#define SLAVE_PCIE_6A_CFG			18
+#define SLAVE_PCIE_6B_CFG			19
+#define SLAVE_PCIE_RSC_CFG			20
+#define SLAVE_PDM				21
+#define SLAVE_PRNG				22
+#define SLAVE_QDSS_CFG				23
+#define SLAVE_QSPI_0				24
+#define SLAVE_QUP_0				25
+#define SLAVE_QUP_1				26
+#define SLAVE_QUP_2				27
+#define SLAVE_SDCC_2				28
+#define SLAVE_SDCC_4				29
+#define SLAVE_SMMUV3_CFG			30
+#define SLAVE_TCSR				31
+#define SLAVE_TLMM				32
+#define SLAVE_UFS_MEM_CFG			33
+#define SLAVE_USB2				34
+#define SLAVE_USB3_0				35
+#define SLAVE_USB3_1				36
+#define SLAVE_USB3_2				37
+#define SLAVE_USB3_MP				38
+#define SLAVE_USB4_0				39
+#define SLAVE_USB4_1				40
+#define SLAVE_USB4_2				41
+#define SLAVE_VENUS_CFG				42
+#define SLAVE_LPASS_QTB_CFG			43
+#define SLAVE_CNOC_MNOC_CFG			44
+#define SLAVE_NSP_QTB_CFG			45
+#define SLAVE_QDSS_STM				46
+#define SLAVE_TCU				47
+
+#define MASTER_GEM_NOC_CNOC			0
+#define MASTER_GEM_NOC_PCIE_SNOC		1
+#define SLAVE_AOSS				2
+#define SLAVE_TME_CFG				3
+#define SLAVE_APPSS				4
+#define SLAVE_CNOC_CFG				5
+#define SLAVE_BOOT_IMEM				6
+#define SLAVE_IMEM				7
+#define SLAVE_PCIE_0				8
+#define SLAVE_PCIE_1				9
+#define SLAVE_PCIE_2				10
+#define SLAVE_PCIE_3				11
+#define SLAVE_PCIE_4				12
+#define SLAVE_PCIE_5				13
+#define SLAVE_PCIE_6A				14
+#define SLAVE_PCIE_6B				15
+
+#define MASTER_GPU_TCU				0
+#define MASTER_PCIE_TCU				1
+#define MASTER_SYS_TCU				2
+#define MASTER_APPSS_PROC			3
+#define MASTER_GFX3D				4
+#define MASTER_LPASS_GEM_NOC			5
+#define MASTER_MNOC_HF_MEM_NOC			6
+#define MASTER_MNOC_SF_MEM_NOC			7
+#define MASTER_COMPUTE_NOC			8
+#define MASTER_ANOC_PCIE_GEM_NOC		9
+#define MASTER_SNOC_SF_MEM_NOC			10
+#define MASTER_GIC2				11
+#define SLAVE_GEM_NOC_CNOC			12
+#define SLAVE_LLCC				13
+#define SLAVE_MEM_NOC_PCIE_SNOC			14
+#define MASTER_MNOC_HF_MEM_NOC_DISP		15
+#define MASTER_ANOC_PCIE_GEM_NOC_DISP		16
+#define SLAVE_LLCC_DISP				17
+#define MASTER_ANOC_PCIE_GEM_NOC_PCIE		18
+#define SLAVE_LLCC_PCIE				19
+
+#define MASTER_LPIAON_NOC			0
+#define SLAVE_LPASS_GEM_NOC			1
+
+#define MASTER_LPASS_LPINOC			0
+#define SLAVE_LPIAON_NOC_LPASS_AG_NOC		1
+
+#define MASTER_LPASS_PROC			0
+#define SLAVE_LPICX_NOC_LPIAON_NOC		1
+
+#define MASTER_LLCC				0
+#define SLAVE_EBI1				1
+#define MASTER_LLCC_DISP			2
+#define SLAVE_EBI1_DISP				3
+#define MASTER_LLCC_PCIE			4
+#define SLAVE_EBI1_PCIE				5
+
+#define MASTER_AV1_ENC				0
+#define MASTER_CAMNOC_HF			1
+#define MASTER_CAMNOC_ICP			2
+#define MASTER_CAMNOC_SF			3
+#define MASTER_EVA				4
+#define MASTER_MDP				5
+#define MASTER_VIDEO				6
+#define MASTER_VIDEO_CV_PROC			7
+#define MASTER_VIDEO_V_PROC			8
+#define MASTER_CNOC_MNOC_CFG			9
+#define SLAVE_MNOC_HF_MEM_NOC			10
+#define SLAVE_MNOC_SF_MEM_NOC			11
+#define SLAVE_SERVICE_MNOC			12
+#define MASTER_MDP_DISP				13
+#define SLAVE_MNOC_HF_MEM_NOC_DISP		14
+
+#define MASTER_CDSP_PROC			0
+#define SLAVE_CDSP_MEM_NOC			1
+
+#define MASTER_PCIE_NORTH			0
+#define MASTER_PCIE_SOUTH			1
+#define SLAVE_ANOC_PCIE_GEM_NOC			2
+#define MASTER_PCIE_NORTH_PCIE			3
+#define MASTER_PCIE_SOUTH_PCIE			4
+#define SLAVE_ANOC_PCIE_GEM_NOC_PCIE		5
+
+#define MASTER_PCIE_3				0
+#define MASTER_PCIE_4				1
+#define MASTER_PCIE_5				2
+#define SLAVE_PCIE_NORTH			3
+#define MASTER_PCIE_3_PCIE			4
+#define MASTER_PCIE_4_PCIE			5
+#define MASTER_PCIE_5_PCIE			6
+#define SLAVE_PCIE_NORTH_PCIE			7
+
+#define MASTER_PCIE_0				0
+#define MASTER_PCIE_1				1
+#define MASTER_PCIE_2				2
+#define MASTER_PCIE_6A				3
+#define MASTER_PCIE_6B				4
+#define SLAVE_PCIE_SOUTH			5
+#define MASTER_PCIE_0_PCIE			6
+#define MASTER_PCIE_1_PCIE			7
+#define MASTER_PCIE_2_PCIE			8
+#define MASTER_PCIE_6A_PCIE			9
+#define MASTER_PCIE_6B_PCIE			10
+#define SLAVE_PCIE_SOUTH_PCIE			11
+
+#define MASTER_A1NOC_SNOC			0
+#define MASTER_A2NOC_SNOC			1
+#define MASTER_GIC1				2
+#define MASTER_USB_NOC_SNOC			3
+#define SLAVE_SNOC_GEM_NOC_SF			4
+
+#define MASTER_AGGRE_USB_NORTH			0
+#define MASTER_AGGRE_USB_SOUTH			1
+#define SLAVE_USB_NOC_SNOC			2
+
+#define MASTER_USB2				0
+#define MASTER_USB3_MP				1
+#define SLAVE_AGGRE_USB_NORTH			2
+
+#define MASTER_USB3_0				0
+#define MASTER_USB3_1				1
+#define MASTER_USB3_2				2
+#define MASTER_USB4_0				3
+#define MASTER_USB4_1				4
+#define MASTER_USB4_2				5
+#define SLAVE_AGGRE_USB_SOUTH			6
+
+#endif
diff --git a/include/dt-bindings/power/meson-g12a-power.h b/include/dt-bindings/power/meson-g12a-power.h
index 44ec0c50e34..01fd0ac4dd0 100644
--- a/include/dt-bindings/power/meson-g12a-power.h
+++ b/include/dt-bindings/power/meson-g12a-power.h
@@ -10,5 +10,6 @@
 #define PWRC_G12A_VPU_ID		0
 #define PWRC_G12A_ETH_ID		1
 #define PWRC_G12A_NNA_ID		2
+#define PWRC_G12A_ISP_ID		3
 
 #endif
diff --git a/include/dt-bindings/reset/amlogic,c3-reset.h b/include/dt-bindings/reset/amlogic,c3-reset.h
new file mode 100644
index 00000000000..d9127863f60
--- /dev/null
+++ b/include/dt-bindings/reset/amlogic,c3-reset.h
@@ -0,0 +1,119 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2023 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_C3_RESET_H
+#define _DT_BINDINGS_AMLOGIC_C3_RESET_H
+
+/* RESET0 */
+/*						0-3 */
+#define RESET_USBCTRL				4
+/*						5-7 */
+#define RESET_USBPHY20				8
+/*						9 */
+#define RESET_USB2DRD				10
+#define RESET_MIPI_DSI_HOST			11
+#define RESET_MIPI_DSI_PHY			12
+/*						13-20 */
+#define RESET_GE2D				21
+#define RESET_DWAP				22
+/*						23-31 */
+
+/* RESET1 */
+#define RESET_AUDIO				32
+/*						33-34 */
+#define RESET_DDRAPB				35
+#define RESET_DDR				36
+#define RESET_DOS_CAPB3				37
+#define RESET_DOS				38
+/*						39-46 */
+#define RESET_NNA				47
+#define RESET_ETHERNET				48
+#define RESET_ISP				49
+#define RESET_VC9000E_APB			50
+#define RESET_VC9000E_A				51
+/*						52 */
+#define RESET_VC9000E_CORE			53
+/*						54-63 */
+
+/* RESET2 */
+#define RESET_ABUS_ARB				64
+#define RESET_IRCTRL				65
+/*						66 */
+#define RESET_TEMP_PII				67
+/*						68-72 */
+#define RESET_SPICC_0				73
+#define RESET_SPICC_1				74
+#define RESET_RSA				75
+
+/*						76-79 */
+#define RESET_MSR_CLK				80
+#define RESET_SPIFC				81
+#define RESET_SAR_ADC				82
+/*						83-87 */
+#define RESET_ACODEC				88
+/*						89-90 */
+#define RESET_WATCHDOG				91
+/*						92-95 */
+
+/* RESET3 */
+#define RESET_ISP_NIC_GPV			96
+#define RESET_ISP_NIC_MAIN			97
+#define RESET_ISP_NIC_VCLK			98
+#define RESET_ISP_NIC_VOUT			99
+#define RESET_ISP_NIC_ALL			100
+#define RESET_VOUT				101
+#define RESET_VOUT_VENC				102
+/*						103 */
+#define RESET_CVE_NIC_GPV			104
+#define RESET_CVE_NIC_MAIN			105
+#define RESET_CVE_NIC_GE2D			106
+#define RESET_CVE_NIC_DW			106
+#define RESET_CVE_NIC_CVE			108
+#define RESET_CVE_NIC_ALL			109
+#define RESET_CVE				110
+/*						112-127 */
+
+/* RESET4 */
+#define RESET_RTC				128
+#define RESET_PWM_AB				129
+#define RESET_PWM_CD				130
+#define RESET_PWM_EF				131
+#define RESET_PWM_GH				132
+#define RESET_PWM_IJ				133
+#define RESET_PWM_KL				134
+#define RESET_PWM_MN				135
+/*						136-137 */
+#define RESET_UART_A				138
+#define RESET_UART_B				139
+#define RESET_UART_C				140
+#define RESET_UART_D				141
+#define RESET_UART_E				142
+#define RESET_UART_F				143
+#define RESET_I2C_S_A				144
+#define RESET_I2C_M_A				145
+#define RESET_I2C_M_B				146
+#define RESET_I2C_M_C				147
+#define RESET_I2C_M_D				148
+/*						149-151 */
+#define RESET_SD_EMMC_A				152
+#define RESET_SD_EMMC_B				153
+#define RESET_SD_EMMC_C				154
+
+/* RESET5 */
+/*						160-172 */
+#define RESET_BRG_NIC_NNA			173
+#define RESET_BRG_MUX_NIC_MAIN			174
+#define RESET_BRG_AO_NIC_ALL			175
+/*						176-183 */
+#define RESET_BRG_NIC_VAPB			184
+#define RESET_BRG_NIC_SDIO_B			185
+#define RESET_BRG_NIC_SDIO_A			186
+#define RESET_BRG_NIC_EMMC			187
+#define RESET_BRG_NIC_DSU			188
+#define RESET_BRG_NIC_SYSCLK			189
+#define RESET_BRG_NIC_MAIN			190
+#define RESET_BRG_NIC_ALL			191
+
+#endif
diff --git a/include/dt-bindings/reset/mediatek,mt7988-resets.h b/include/dt-bindings/reset/mediatek,mt7988-resets.h
new file mode 100644
index 00000000000..49330197136
--- /dev/null
+++ b/include/dt-bindings/reset/mediatek,mt7988-resets.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023 Daniel Golle <daniel@makrotopia.org>
+ * Author: Daniel Golle <daniel@makrotopia.org>
+ */
+
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7988
+#define _DT_BINDINGS_RESET_CONTROLLER_MT7988
+
+/* ETHWARP resets */
+#define MT7988_ETHWARP_RST_SWITCH		0
+
+#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */
diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h
index ba9a5e9b889..5a58c54e7d2 100644
--- a/include/dt-bindings/reset/mt8188-resets.h
+++ b/include/dt-bindings/reset/mt8188-resets.h
@@ -38,4 +38,79 @@
 #define MT8188_INFRA_RST1_THERMAL_CTRL_RST         1
 #define MT8188_INFRA_RST3_PTP_CTRL_RST             2
 
+#define MT8188_VDO0_RST_DISP_OVL0		0
+#define MT8188_VDO0_RST_FAKE_ENG0		1
+#define MT8188_VDO0_RST_DISP_CCORR0		2
+#define MT8188_VDO0_RST_DISP_MUTEX0		3
+#define MT8188_VDO0_RST_DISP_GAMMA0		4
+#define MT8188_VDO0_RST_DISP_DITHER0		5
+#define MT8188_VDO0_RST_DISP_WDMA0		6
+#define MT8188_VDO0_RST_DISP_RDMA0		7
+#define MT8188_VDO0_RST_DSI0			8
+#define MT8188_VDO0_RST_DSI1			9
+#define MT8188_VDO0_RST_DSC_WRAP0		10
+#define MT8188_VDO0_RST_VPP_MERGE0		11
+#define MT8188_VDO0_RST_DP_INTF0		12
+#define MT8188_VDO0_RST_DISP_AAL0		13
+#define MT8188_VDO0_RST_INLINEROT0		14
+#define MT8188_VDO0_RST_APB_BUS			15
+#define MT8188_VDO0_RST_DISP_COLOR0		16
+#define MT8188_VDO0_RST_MDP_WROT0		17
+#define MT8188_VDO0_RST_DISP_RSZ0		18
+
+#define MT8188_VDO1_RST_SMI_LARB2		0
+#define MT8188_VDO1_RST_SMI_LARB3		1
+#define MT8188_VDO1_RST_GALS			2
+#define MT8188_VDO1_RST_FAKE_ENG0		3
+#define MT8188_VDO1_RST_FAKE_ENG1		4
+#define MT8188_VDO1_RST_MDP_RDMA0		5
+#define MT8188_VDO1_RST_MDP_RDMA1		6
+#define MT8188_VDO1_RST_MDP_RDMA2		7
+#define MT8188_VDO1_RST_MDP_RDMA3		8
+#define MT8188_VDO1_RST_VPP_MERGE0		9
+#define MT8188_VDO1_RST_VPP_MERGE1		10
+#define MT8188_VDO1_RST_VPP_MERGE2		11
+#define MT8188_VDO1_RST_VPP_MERGE3		12
+#define MT8188_VDO1_RST_VPP_MERGE4		13
+#define MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC	14
+#define MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC	15
+#define MT8188_VDO1_RST_DISP_MUTEX		16
+#define MT8188_VDO1_RST_MDP_RDMA4		17
+#define MT8188_VDO1_RST_MDP_RDMA5		18
+#define MT8188_VDO1_RST_MDP_RDMA6		19
+#define MT8188_VDO1_RST_MDP_RDMA7		20
+#define MT8188_VDO1_RST_DP_INTF1_MMCK		21
+#define MT8188_VDO1_RST_DPI0_MM_CK		22
+#define MT8188_VDO1_RST_DPI1_MM_CK		23
+#define MT8188_VDO1_RST_MERGE0_DL_ASYNC		24
+#define MT8188_VDO1_RST_MERGE1_DL_ASYNC		25
+#define MT8188_VDO1_RST_MERGE2_DL_ASYNC		26
+#define MT8188_VDO1_RST_MERGE3_DL_ASYNC		27
+#define MT8188_VDO1_RST_MERGE4_DL_ASYNC		28
+#define MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC	29
+#define MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC	30
+#define MT8188_VDO1_RST_PADDING0		31
+#define MT8188_VDO1_RST_PADDING1		32
+#define MT8188_VDO1_RST_PADDING2		33
+#define MT8188_VDO1_RST_PADDING3		34
+#define MT8188_VDO1_RST_PADDING4		35
+#define MT8188_VDO1_RST_PADDING5		36
+#define MT8188_VDO1_RST_PADDING6		37
+#define MT8188_VDO1_RST_PADDING7		38
+#define MT8188_VDO1_RST_DISP_RSZ0		39
+#define MT8188_VDO1_RST_DISP_RSZ1		40
+#define MT8188_VDO1_RST_DISP_RSZ2		41
+#define MT8188_VDO1_RST_DISP_RSZ3		42
+#define MT8188_VDO1_RST_HDR_VDO_FE0		43
+#define MT8188_VDO1_RST_HDR_GFX_FE0		44
+#define MT8188_VDO1_RST_HDR_VDO_BE		45
+#define MT8188_VDO1_RST_HDR_VDO_FE1		46
+#define MT8188_VDO1_RST_HDR_GFX_FE1		47
+#define MT8188_VDO1_RST_DISP_MIXER		48
+#define MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC	49
+#define MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC	50
+#define MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC	51
+#define MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC	52
+#define MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC	53
+
 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */
diff --git a/include/dt-bindings/reset/qcom,sm8650-gpucc.h b/include/dt-bindings/reset/qcom,sm8650-gpucc.h
new file mode 100644
index 00000000000..f021a6cccc6
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,sm8650-gpucc.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8650_H
+#define _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8650_H
+
+#define GPUCC_GPU_CC_ACD_BCR			0
+#define GPUCC_GPU_CC_CX_BCR			1
+#define GPUCC_GPU_CC_FAST_HUB_BCR		2
+#define GPUCC_GPU_CC_FF_BCR			3
+#define GPUCC_GPU_CC_GFX3D_AON_BCR		4
+#define GPUCC_GPU_CC_GMU_BCR			5
+#define GPUCC_GPU_CC_GX_BCR			6
+#define GPUCC_GPU_CC_XO_BCR			7
+#define GPUCC_GPU_CC_GX_ACD_IROOT_BCR		8
+
+#endif
diff --git a/include/dt-bindings/reset/st,stm32mp25-rcc.h b/include/dt-bindings/reset/st,stm32mp25-rcc.h
new file mode 100644
index 00000000000..d5615930bcc
--- /dev/null
+++ b/include/dt-bindings/reset/st,stm32mp25-rcc.h
@@ -0,0 +1,167 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author(s): Gabriel Fernandez <gabriel.fernandez@foss.st.com>
+ */
+
+#ifndef _DT_BINDINGS_STM32MP25_RESET_H_
+#define _DT_BINDINGS_STM32MP25_RESET_H_
+
+#define TIM1_R		0
+#define TIM2_R		1
+#define TIM3_R		2
+#define TIM4_R		3
+#define TIM5_R		4
+#define TIM6_R		5
+#define TIM7_R		6
+#define TIM8_R		7
+#define TIM10_R		8
+#define TIM11_R		9
+#define TIM12_R		10
+#define TIM13_R		11
+#define TIM14_R		12
+#define TIM15_R		13
+#define TIM16_R		14
+#define TIM17_R		15
+#define TIM20_R		16
+#define LPTIM1_R	17
+#define LPTIM2_R	18
+#define LPTIM3_R	19
+#define LPTIM4_R	20
+#define LPTIM5_R	21
+#define SPI1_R		22
+#define SPI2_R		23
+#define SPI3_R		24
+#define SPI4_R		25
+#define SPI5_R		26
+#define SPI6_R		27
+#define SPI7_R		28
+#define SPI8_R		29
+#define SPDIFRX_R	30
+#define USART1_R	31
+#define USART2_R	32
+#define USART3_R	33
+#define UART4_R		34
+#define UART5_R		35
+#define USART6_R	36
+#define UART7_R		37
+#define UART8_R		38
+#define UART9_R		39
+#define LPUART1_R	40
+#define IS2M_R		41
+#define I2C1_R		42
+#define I2C2_R		43
+#define I2C3_R		44
+#define I2C4_R		45
+#define I2C5_R		46
+#define I2C6_R		47
+#define I2C7_R		48
+#define I2C8_R		49
+#define SAI1_R		50
+#define SAI2_R		51
+#define SAI3_R		52
+#define SAI4_R		53
+#define MDF1_R		54
+#define MDF2_R		55
+#define FDCAN_R		56
+#define HDP_R		57
+#define ADC12_R		58
+#define ADC3_R		59
+#define ETH1_R		60
+#define ETH2_R		61
+#define USB2_R		62
+#define USB2PHY1_R	63
+#define USB2PHY2_R	64
+#define USB3DR_R	65
+#define USB3PCIEPHY_R	66
+#define USBTC_R		67
+#define ETHSW_R		68
+#define SDMMC1_R	69
+#define SDMMC1DLL_R	70
+#define SDMMC2_R	71
+#define SDMMC2DLL_R	72
+#define SDMMC3_R	73
+#define SDMMC3DLL_R	74
+#define GPU_R		75
+#define LTDC_R		76
+#define DSI_R		77
+#define LVDS_R		78
+#define CSI_R		79
+#define DCMIPP_R	80
+#define CCI_R		81
+#define VDEC_R		82
+#define VENC_R		83
+#define WWDG1_R		84
+#define WWDG2_R		85
+#define VREF_R		86
+#define DTS_R		87
+#define CRC_R		88
+#define SERC_R		89
+#define OSPIIOM_R	90
+#define I3C1_R		91
+#define I3C2_R		92
+#define I3C3_R		93
+#define I3C4_R		94
+#define IWDG2_KER_R	95
+#define IWDG4_KER_R	96
+#define RNG_R		97
+#define PKA_R		98
+#define SAES_R		99
+#define HASH_R		100
+#define CRYP1_R		101
+#define CRYP2_R		102
+#define PCIE_R		103
+#define OSPI1_R		104
+#define OSPI1DLL_R	105
+#define OSPI2_R		106
+#define OSPI2DLL_R	107
+#define FMC_R		108
+#define DBG_R		109
+#define GPIOA_R		110
+#define GPIOB_R		111
+#define GPIOC_R		112
+#define GPIOD_R		113
+#define GPIOE_R		114
+#define GPIOF_R		115
+#define GPIOG_R		116
+#define GPIOH_R		117
+#define GPIOI_R		118
+#define GPIOJ_R		119
+#define GPIOK_R		120
+#define GPIOZ_R		121
+#define HPDMA1_R	122
+#define HPDMA2_R	123
+#define HPDMA3_R	124
+#define LPDMA_R		125
+#define HSEM_R		126
+#define IPCC1_R		127
+#define IPCC2_R		128
+#define C2_HOLDBOOT_R	129
+#define C1_HOLDBOOT_R	130
+#define C1_R		131
+#define C1P1POR_R	132
+#define C1P1_R		133
+#define C2_R		134
+#define C3_R		135
+#define SYS_R		136
+#define VSW_R		137
+#define C1MS_R		138
+#define DDRCP_R		139
+#define DDRCAPB_R	140
+#define DDRPHYCAPB_R	141
+#define DDRCFG_R	142
+#define DDR_R		143
+
+#define STM32MP25_LAST_RESET	144
+
+#define RST_SCMI_C1_R		0
+#define RST_SCMI_C2_R		1
+#define RST_SCMI_C1_HOLDBOOT_R	2
+#define RST_SCMI_C2_HOLDBOOT_R	3
+#define RST_SCMI_FMC		4
+#define RST_SCMI_OSPI1		5
+#define RST_SCMI_OSPI1DLL	6
+#define RST_SCMI_OSPI2		7
+#define RST_SCMI_OSPI2DLL	8
+
+#endif /* _DT_BINDINGS_STM32MP25_RESET_H_ */
diff --git a/include/dt-bindings/soc/rockchip,vop2.h b/include/dt-bindings/soc/rockchip,vop2.h
index 6e66a802b96..668f199df9f 100644
--- a/include/dt-bindings/soc/rockchip,vop2.h
+++ b/include/dt-bindings/soc/rockchip,vop2.h
@@ -10,5 +10,9 @@
 #define ROCKCHIP_VOP2_EP_LVDS0	5
 #define ROCKCHIP_VOP2_EP_MIPI1	6
 #define ROCKCHIP_VOP2_EP_LVDS1	7
+#define ROCKCHIP_VOP2_EP_HDMI1	8
+#define ROCKCHIP_VOP2_EP_EDP1	9
+#define ROCKCHIP_VOP2_EP_DP0	10
+#define ROCKCHIP_VOP2_EP_DP1	11
 
 #endif /* __DT_BINDINGS_ROCKCHIP_VOP2_H */