Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""

When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.

This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.

Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>

1 files changed, 0 insertions, 271 deletions

diff --git a/include/dt-bindings/clock/adi-sc5xx-clock.h b/include/dt-bindings/clock/adi-sc5xx-clock.h
deleted file mode 100644
index 4a5373d1141..00000000000
--- a/include/dt-bindings/clock/adi-sc5xx-clock.h
+++ /dev/null
@@ -1,271 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * (C) Copyright 2022 - Analog Devices, Inc.
- *
- * Written and/or maintained by Timesys Corporation
- *
- * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
- * Contact: Greg Malysa <greg.malysa@timesys.com>
- *
- */
-
-#ifndef DT_BINDINGS_CLOCK_ADI_SC5XX_CLOCK_H
-#define DT_BINDINGS_CLOCK_ADI_SC5XX_CLOCK_H
-
-//ADSP-SC594
-#define ADSP_SC594_CLK_DUMMY 0
-#define ADSP_SC594_CLK_SYS_CLKIN0 1
-#define ADSP_SC594_CLK_SYS_CLKIN1 2
-#define ADSP_SC594_CLK_CGU1_IN 3
-#define ADSP_SC594_CLK_CGU0_PLL_IN 4
-#define ADSP_SC594_CLK_CGU1_PLL_IN 5
-#define ADSP_SC594_CLK_CGU0_VCO_OUT 6
-#define ADSP_SC594_CLK_CGU1_VCO_OUT 7
-#define ADSP_SC594_CLK_CGU0_PLLCLK 8
-#define ADSP_SC594_CLK_CGU1_PLLCLK 9
-#define ADSP_SC594_CLK_CGU0_CDIV 10
-#define ADSP_SC594_CLK_CGU0_SYSCLK 11
-#define ADSP_SC594_CLK_CGU0_DDIV 12
-#define ADSP_SC594_CLK_CGU0_ODIV 13
-#define ADSP_SC594_CLK_CGU0_S0SELDIV 14
-#define ADSP_SC594_CLK_CGU0_S1SELDIV 15
-#define ADSP_SC594_CLK_CGU0_S1SELEXDIV 16
-#define ADSP_SC594_CLK_CGU0_S1SEL 17
-#define ADSP_SC594_CLK_CGU1_CDIV 18
-#define ADSP_SC594_CLK_CGU1_SYSCLK 19
-#define ADSP_SC594_CLK_CGU1_DDIV 20
-#define ADSP_SC594_CLK_CGU1_ODIV 21
-#define ADSP_SC594_CLK_CGU1_S0SELDIV 22
-#define ADSP_SC594_CLK_CGU1_S1SELDIV 23
-#define ADSP_SC594_CLK_CGU1_S1SELEXDIV 24
-#define ADSP_SC594_CLK_CGU1_S1SEL 25
-#define ADSP_SC594_CLK_CGU0_CCLK0 26
-#define ADSP_SC594_CLK_CGU0_CCLK1 27
-#define ADSP_SC594_CLK_CGU0_OCLK 28
-#define ADSP_SC594_CLK_CGU0_DCLK 29
-#define ADSP_SC594_CLK_CGU0_SCLK1 30
-#define ADSP_SC594_CLK_CGU0_SCLK0 31
-#define ADSP_SC594_CLK_CGU1_CCLK0 32
-#define ADSP_SC594_CLK_CGU1_CCLK1 33
-#define ADSP_SC594_CLK_CGU1_OCLK 34
-#define ADSP_SC594_CLK_CGU1_DCLK 35
-#define ADSP_SC594_CLK_CGU1_SCLK1 36
-#define ADSP_SC594_CLK_CGU1_SCLK0 37
-#define ADSP_SC594_CLK_SHARC0_SEL 38
-#define ADSP_SC594_CLK_SHARC1_SEL 39
-#define ADSP_SC594_CLK_ARM_SEL 40
-#define ADSP_SC594_CLK_CDU_DDR_SEL 41
-#define ADSP_SC594_CLK_CAN_SEL 42
-#define ADSP_SC594_CLK_SPDIF_SEL 43
-#define ADSP_SC594_CLK_RESERVED_SEL 44
-#define ADSP_SC594_CLK_GIGE_SEL 45
-#define ADSP_SC594_CLK_LP_SEL 46
-#define ADSP_SC594_CLK_LPDDR_SEL 47
-#define ADSP_SC594_CLK_OSPI_SEL 48
-#define ADSP_SC594_CLK_TRACE_SEL 49
-#define ADSP_SC594_CLK_SHARC0 50
-#define ADSP_SC594_CLK_SHARC1 51
-#define ADSP_SC594_CLK_ARM 52
-#define ADSP_SC594_CLK_CDU_DDR 53
-#define ADSP_SC594_CLK_CAN 54
-#define ADSP_SC594_CLK_SPDIF 55
-#define ADSP_SC594_CLK_SPI 56
-#define ADSP_SC594_CLK_GIGE 57
-#define ADSP_SC594_CLK_LP 58
-#define ADSP_SC594_CLK_LPDDR 59
-#define ADSP_SC594_CLK_OSPI 60
-#define ADSP_SC594_CLK_TRACE 61
-#define ADSP_SC594_CLK_END 62
-
-//ADSP-SC598
-#define ADSP_SC598_CLK_DUMMY 0
-#define ADSP_SC598_CLK_SYS_CLKIN0 1
-#define ADSP_SC598_CLK_SYS_CLKIN1 2
-#define ADSP_SC598_CLK_CGU0_PLL_IN 3
-#define ADSP_SC598_CLK_CGU0_VCO_OUT 4
-#define ADSP_SC598_CLK_CGU0_PLLCLK 5
-#define ADSP_SC598_CLK_CGU1_IN 6
-#define ADSP_SC598_CLK_CGU1_PLL_IN 7
-#define ADSP_SC598_CLK_CGU1_VCO_OUT 8
-#define ADSP_SC598_CLK_CGU1_PLLCLK 9
-#define ADSP_SC598_CLK_CGU0_CDIV 10
-#define ADSP_SC598_CLK_CGU0_SYSCLK 11
-#define ADSP_SC598_CLK_CGU0_DDIV 12
-#define ADSP_SC598_CLK_CGU0_ODIV 13
-#define ADSP_SC598_CLK_CGU0_S0SELDIV 14
-#define ADSP_SC598_CLK_CGU0_S1SELDIV 15
-#define ADSP_SC598_CLK_CGU0_S1SELEXDIV 16
-#define ADSP_SC598_CLK_CGU0_S1SEL 17
-#define ADSP_SC598_CLK_CGU1_CDIV 18
-#define ADSP_SC598_CLK_CGU1_SYSCLK 19
-#define ADSP_SC598_CLK_CGU1_DDIV 20
-#define ADSP_SC598_CLK_CGU1_ODIV 21
-#define ADSP_SC598_CLK_CGU1_S0SELDIV 22
-#define ADSP_SC598_CLK_CGU1_S1SELDIV 23
-#define ADSP_SC598_CLK_CGU1_S0SELEXDIV 24
-#define ADSP_SC598_CLK_CGU1_S1SELEXDIV 25
-#define ADSP_SC598_CLK_CGU1_S0SEL 26
-#define ADSP_SC598_CLK_CGU1_S1SEL 27
-#define ADSP_SC598_CLK_CGU0_CCLK2 28
-#define ADSP_SC598_CLK_CGU0_CCLK0 29
-#define ADSP_SC598_CLK_CGU0_OCLK 30
-#define ADSP_SC598_CLK_CGU0_DCLK 31
-#define ADSP_SC598_CLK_CGU0_SCLK1 32
-#define ADSP_SC598_CLK_CGU0_SCLK0 33
-#define ADSP_SC598_CLK_CGU1_CCLK0 34
-#define ADSP_SC598_CLK_CGU1_OCLK 35
-#define ADSP_SC598_CLK_CGU1_DCLK 36
-#define ADSP_SC598_CLK_CGU1_SCLK1 37
-#define ADSP_SC598_CLK_CGU1_SCLK0 38
-#define ADSP_SC598_CLK_CGU1_CCLK2 39
-#define ADSP_SC598_CLK_DCLK0_HALF 40
-#define ADSP_SC598_CLK_DCLK1_HALF 41
-#define ADSP_SC598_CLK_CGU1_SCLK1_HALF 42
-#define ADSP_SC598_CLK_SHARC0_SEL 43
-#define ADSP_SC598_CLK_SHARC1_SEL 44
-#define ADSP_SC598_CLK_ARM_SEL 45
-#define ADSP_SC598_CLK_CDU_DDR_SEL 46
-#define ADSP_SC598_CLK_CAN_SEL 47
-#define ADSP_SC598_CLK_SPDIF_SEL 48
-#define ADSP_SC598_CLK_SPI_SEL 49
-#define ADSP_SC598_CLK_GIGE_SEL 50
-#define ADSP_SC598_CLK_LP_SEL 51
-#define ADSP_SC598_CLK_LP_DDR_SEL 52
-#define ADSP_SC598_CLK_OSPI_REFCLK_SEL 53
-#define ADSP_SC598_CLK_TRACE_SEL 54
-#define ADSP_SC598_CLK_EMMC_SEL 55
-#define ADSP_SC598_CLK_EMMC_TIMER_QMC_SEL 56
-#define ADSP_SC598_CLK_SHARC0 57
-#define ADSP_SC598_CLK_SHARC1 58
-#define ADSP_SC598_CLK_ARM 59
-#define ADSP_SC598_CLK_CDU_DDR 60
-#define ADSP_SC598_CLK_CAN 61
-#define ADSP_SC598_CLK_SPDIF 62
-#define ADSP_SC598_CLK_SPI 63
-#define ADSP_SC598_CLK_GIGE 64
-#define ADSP_SC598_CLK_LP 65
-#define ADSP_SC598_CLK_LP_DDR 66
-#define ADSP_SC598_CLK_OSPI_REFCLK 67
-#define ADSP_SC598_CLK_TRACE 68
-#define ADSP_SC598_CLK_EMMC 69
-#define ADSP_SC598_CLK_EMMC_TIMER_QMC 70
-#define ADSP_SC598_CLK_3PLL_PLL_IN 71
-#define ADSP_SC598_CLK_3PLL_VCO_OUT 72
-#define ADSP_SC598_CLK_3PLL_PLLCLK 73
-#define ADSP_SC598_CLK_3PLL_DDIV 74
-#define ADSP_SC598_CLK_DDR 75
-#define ADSP_SC598_CLK_END 76
-
-//ADSP-SC58X
-#define ADSP_SC58X_CLK_DUMMY 0
-#define ADSP_SC58X_CLK_SYS_CLKIN0 1
-#define ADSP_SC58X_CLK_SYS_CLKIN1 2
-#define ADSP_SC58X_CLK_CGU0_PLL_IN 3
-#define ADSP_SC58X_CLK_CGU0_VCO_OUT 4
-#define ADSP_SC58X_CLK_CGU0_PLLCLK 5
-#define ADSP_SC58X_CLK_CGU1_IN 6
-#define ADSP_SC58X_CLK_CGU1_PLL_IN 7
-#define ADSP_SC58X_CLK_CGU1_VCO_OUT 8
-#define ADSP_SC58X_CLK_CGU1_PLLCLK 9
-#define ADSP_SC58X_CLK_CGU0_CDIV 10
-#define ADSP_SC58X_CLK_CGU0_SYSCLK 11
-#define ADSP_SC58X_CLK_CGU0_DDIV 12
-#define ADSP_SC58X_CLK_CGU0_ODIV 13
-#define ADSP_SC58X_CLK_CGU0_S0SELDIV 14
-#define ADSP_SC58X_CLK_CGU0_S1SELDIV 15
-#define ADSP_SC58X_CLK_CGU1_CDIV 16
-#define ADSP_SC58X_CLK_CGU1_SYSCLK 17
-#define ADSP_SC58X_CLK_CGU1_DDIV 18
-#define ADSP_SC58X_CLK_CGU1_ODIV 19
-#define ADSP_SC58X_CLK_CGU1_S0SELDIV 20
-#define ADSP_SC58X_CLK_CGU1_S1SELDIV 21
-#define ADSP_SC58X_CLK_CGU0_CCLK0 22
-#define ADSP_SC58X_CLK_CGU0_CCLK1 23
-#define ADSP_SC58X_CLK_CGU0_OCLK 24
-#define ADSP_SC58X_CLK_CGU0_DCLK 25
-#define ADSP_SC58X_CLK_CGU0_SCLK1 26
-#define ADSP_SC58X_CLK_CGU0_SCLK0 27
-#define ADSP_SC58X_CLK_CGU1_CCLK0 28
-#define ADSP_SC58X_CLK_CGU1_CCLK1 29
-#define ADSP_SC58X_CLK_CGU1_OCLK 30
-#define ADSP_SC58X_CLK_CGU1_DCLK 31
-#define ADSP_SC58X_CLK_CGU1_SCLK1 32
-#define ADSP_SC58X_CLK_CGU1_SCLK0 33
-#define ADSP_SC58X_CLK_OCLK0_HALF 34
-#define ADSP_SC58X_CLK_CCLK1_1_HALF 35
-#define ADSP_SC58X_CLK_SHARC0_SEL 36
-#define ADSP_SC58X_CLK_SHARC1_SEL 37
-#define ADSP_SC58X_CLK_ARM_SEL 38
-#define ADSP_SC58X_CLK_CDU_DDR_SEL 39
-#define ADSP_SC58X_CLK_CAN_SEL 40
-#define ADSP_SC58X_CLK_SPDIF_SEL 41
-#define ADSP_SC58X_CLK_RESERVED_SEL 42
-#define ADSP_SC58X_CLK_GIGE_SEL 43
-#define ADSP_SC58X_CLK_LP_SEL 44
-#define ADSP_SC58X_CLK_SDIO_SEL 45
-#define ADSP_SC58X_CLK_SHARC0 46
-#define ADSP_SC58X_CLK_SHARC1 47
-#define ADSP_SC58X_CLK_ARM 48
-#define ADSP_SC58X_CLK_CDU_DDR 49
-#define ADSP_SC58X_CLK_CAN 50
-#define ADSP_SC58X_CLK_SPDIF 51
-#define ADSP_SC58X_CLK_RESERVED 52
-#define ADSP_SC58X_CLK_GIGE 53
-#define ADSP_SC58X_CLK_LP 54
-#define ADSP_SC58X_CLK_SDIO 55
-#define ADSP_SC58X_CLK_END 56
-
-//ADSP-SC57X
-#define ADSP_SC57X_CLK_DUMMY 0
-#define ADSP_SC57X_CLK_SYS_CLKIN0 1
-#define ADSP_SC57X_CLK_SYS_CLKIN1 2
-#define ADSP_SC57X_CLK_CGU0_PLL_IN 3
-#define ADSP_SC57X_CLK_CGU0_PLLCLK 4
-#define ADSP_SC57X_CLK_CGU1_IN 5
-#define ADSP_SC57X_CLK_CGU1_PLL_IN 6
-#define ADSP_SC57X_CLK_CGU1_PLLCLK 7
-#define ADSP_SC57X_CLK_CGU0_CDIV 8
-#define ADSP_SC57X_CLK_CGU0_SYSCLK 9
-#define ADSP_SC57X_CLK_CGU0_DDIV 10
-#define ADSP_SC57X_CLK_CGU0_ODIV 11
-#define ADSP_SC57X_CLK_CGU0_S0SELDIV 12
-#define ADSP_SC57X_CLK_CGU0_S1SELDIV 13
-#define ADSP_SC57X_CLK_CGU1_CDIV 14
-#define ADSP_SC57X_CLK_CGU1_SYSCLK 15
-#define ADSP_SC57X_CLK_CGU1_DDIV 16
-#define ADSP_SC57X_CLK_CGU1_ODIV 17
-#define ADSP_SC57X_CLK_CGU1_S0SELDIV 18
-#define ADSP_SC57X_CLK_CGU1_S1SELDIV 19
-#define ADSP_SC57X_CLK_CGU0_CCLK0 20
-#define ADSP_SC57X_CLK_CGU0_CCLK1 21
-#define ADSP_SC57X_CLK_CGU0_OCLK 22
-#define ADSP_SC57X_CLK_CGU0_DCLK 23
-#define ADSP_SC57X_CLK_CGU0_SCLK1 24
-#define ADSP_SC57X_CLK_CGU0_SCLK0 25
-#define ADSP_SC57X_CLK_CGU1_CCLK0 26
-#define ADSP_SC57X_CLK_CGU1_CCLK1 27
-#define ADSP_SC57X_CLK_CGU1_OCLK 28
-#define ADSP_SC57X_CLK_CGU1_DCLK 29
-#define ADSP_SC57X_CLK_CGU1_SCLK1 30
-#define ADSP_SC57X_CLK_CGU1_SCLK0 31
-#define ADSP_SC57X_CLK_OCLK0_HALF 32
-#define ADSP_SC57X_CLK_CCLK1_1_HALF 33
-#define ADSP_SC57X_CLK_SHARC0_SEL 34
-#define ADSP_SC57X_CLK_SHARC1_SEL 35
-#define ADSP_SC57X_CLK_ARM_SEL 36
-#define ADSP_SC57X_CLK_CDU_DDR_SEL 37
-#define ADSP_SC57X_CLK_CAN_SEL 38
-#define ADSP_SC57X_CLK_SPDIF_SEL 39
-#define ADSP_SC57X_CLK_GIGE_SEL 40
-#define ADSP_SC57X_CLK_SDIO_SEL 41
-#define ADSP_SC57X_CLK_SHARC0 42
-#define ADSP_SC57X_CLK_SHARC1 43
-#define ADSP_SC57X_CLK_ARM 44
-#define ADSP_SC57X_CLK_CDU_DDR 45
-#define ADSP_SC57X_CLK_CAN 46
-#define ADSP_SC57X_CLK_SPDIF 47
-#define ADSP_SC57X_CLK_GIGE 48
-#define ADSP_SC57X_CLK_SDIO 49
-#define ADSP_SC57X_CLK_END 50
-
-#endif