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authorRajeshwari S Shinde2014-02-05 10:48:15 +0530
committerPantelis Antoniou2014-02-07 17:42:26 +0200
commitd3e016cc28684cd32d826a9414a0e89ccf80861a (patch)
tree8ed71c5f9ff24fded82a3f6730cd28744e17a2cc /include/dwmmc.h
parentdef816a2ba87c2a3507536e8cb226f0f85bdae2c (diff)
MMC: DWMMC: Correct the CLKDIV register value
This patch corrects the divider value written to CLKDIV register. Since SDCLKIN is divided inside controller by the DIVRATIO value set in the CLKSEL register, we need to use the same output clock value to calculate the CLKDIV value. as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1) Input parameter to mmc_clk is changed to dwmci_host, since we need the same to read DWMCI_CLKSEL register. This improves the read timing values for channel 0 on SMDK5250 from 0.288sec to 0.144sec Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Diffstat (limited to 'include/dwmmc.h')
-rw-r--r--include/dwmmc.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/dwmmc.h b/include/dwmmc.h
index a02dd67c137..b64155851d6 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -142,7 +142,7 @@ struct dwmci_host {
void (*clksel)(struct dwmci_host *host);
void (*board_init)(struct dwmci_host *host);
- unsigned int (*get_mmc_clk)(int dev_index);
+ unsigned int (*get_mmc_clk)(struct dwmci_host *host);
};
struct dwmci_idmac {