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authorMingkai Hu2015-10-26 19:47:41 +0800
committerYork Sun2015-10-29 10:33:58 -0700
commit435acd83b2b4f31699732f090d28d66cabb05912 (patch)
tree348edbeed8285a51e514b4af38b04bb81ef7ea87 /include/fsl_csu.h
parent18fb0e3cae64b03c51db7ba8b607e9031a844b99 (diff)
armv7/ls1021a: move ns_access to common file
Config Security Level Register is different between different SoCs, so put the CSL register definition into the arch specific directory. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include/fsl_csu.h')
-rw-r--r--include/fsl_csu.h34
1 files changed, 34 insertions, 0 deletions
diff --git a/include/fsl_csu.h b/include/fsl_csu.h
new file mode 100644
index 00000000000..f4d97fb6054
--- /dev/null
+++ b/include/fsl_csu.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#ifndef __FSL_CSU_H__
+#define __FSL_CSU_H__
+
+enum csu_cslx_access {
+ CSU_NS_SUP_R = 0x08,
+ CSU_NS_SUP_W = 0x80,
+ CSU_NS_SUP_RW = 0x88,
+ CSU_NS_USER_R = 0x04,
+ CSU_NS_USER_W = 0x40,
+ CSU_NS_USER_RW = 0x44,
+ CSU_S_SUP_R = 0x02,
+ CSU_S_SUP_W = 0x20,
+ CSU_S_SUP_RW = 0x22,
+ CSU_S_USER_R = 0x01,
+ CSU_S_USER_W = 0x10,
+ CSU_S_USER_RW = 0x11,
+ CSU_ALL_RW = 0xff,
+};
+
+struct csu_ns_dev {
+ unsigned long ind;
+ uint32_t val;
+};
+
+void enable_layerscape_ns_access(void);
+
+#endif