diff options
| author | York Sun | 2015-03-19 09:30:29 -0700 |
|---|---|---|
| committer | York Sun | 2015-04-23 08:55:54 -0700 |
| commit | 9f9f0093730f91d95cb8e9546155ae6a3286159e (patch) | |
| tree | 1d36b95e502a862e848187336cadb0a51a92b65c /include/fsl_ddr_sdram.h | |
| parent | 4516ff816084605990115d127df97950c23e389c (diff) | |
driver/ddr/fsl: Add workaround for DDR erratum A008511
This erratum only applies to general purpose DDR controllers in LS2.
It shouldn't be applied to DP-DDR controller. Check DDRC versoin number
before applying workaround.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include/fsl_ddr_sdram.h')
| -rw-r--r-- | include/fsl_ddr_sdram.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 095b33e29ee..6358b6f3a27 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -155,6 +155,8 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define MD_CNTL_CKE_CNTL_HIGH 0x00200000 #define MD_CNTL_WRCW 0x00080000 #define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF) +#define MD_CNTL_CS_SEL(x) (((x) & 0x7) << 28) +#define MD_CNTL_MD_SEL(x) (((x) & 0xf) << 24) /* DDR_CDR1 */ #define DDR_CDR1_DHC_EN 0x80000000 |