diff options
| author | Simon Glass | 2012-07-29 20:53:25 +0000 |
|---|---|---|
| committer | Tom Warren | 2012-09-07 13:54:30 -0700 |
| commit | b572595ee95829ab62e354c55a8fbd0f4db23935 (patch) | |
| tree | 18ce59921123f5b98f47e4845bef96f191593cd4 /include/linux | |
| parent | 057df193b40d31799d41d43bc832a972f658bfe4 (diff) | |
nand: Try to align the default buffers
The NAND layer needs to use cache-aligned buffers by default. Towards this
goal. align the default buffers and their members according to the minimum
DMA alignment defined for the architecture.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/mtd/nand.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 82704de0835..dc839e71538 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -391,9 +391,10 @@ struct nand_ecc_ctrl { * consecutive order. */ struct nand_buffers { - uint8_t ecccalc[NAND_MAX_OOBSIZE]; - uint8_t ecccode[NAND_MAX_OOBSIZE]; - uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE]; + uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; + uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; + uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE, + ARCH_DMA_MINALIGN)]; }; /** |