include: Remove unused header files

As part of various code clean-ups we have on occasion missed removing
unused header files.  None of these files are referenced anywhere else
at this point.

Signed-off-by: Tom Rini <trini@konsulko.com>

3 files changed, 0 insertions, 360 deletions

diff --git a/include/linux/mc146818rtc.h b/include/linux/mc146818rtc.h
deleted file mode 100644
index 0644d92b3ca..00000000000
--- a/include/linux/mc146818rtc.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/* mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM
- * Copyright Torsten Duwe <duwe@informatik.uni-erlangen.de> 1993
- * derived from Data Sheet, Copyright Motorola 1984 (!).
- * It was written to be part of the Linux operating system.
- */
-/* permission is hereby granted to copy, modify and redistribute this code
- * in terms of the GNU Library General Public License, Version 2 or later,
- * at your option.
- */
-
-#ifndef _MC146818RTC_H
-#define _MC146818RTC_H
-
-#include <asm/io.h>
-#include <linux/rtc.h>          /* get the user-level API */
-#include <asm/mc146818rtc.h>        /* register access macros */
-
-/**********************************************************************
- * register summary
- **********************************************************************/
-#define RTC_SECONDS     0
-#define RTC_SECONDS_ALARM   1
-#define RTC_MINUTES     2
-#define RTC_MINUTES_ALARM   3
-#define RTC_HOURS       4
-#define RTC_HOURS_ALARM     5
-/* RTC_*_alarm is always true if 2 MSBs are set */
-# define RTC_ALARM_DONT_CARE    0xC0
-
-#define RTC_DAY_OF_WEEK     6
-#define RTC_DAY_OF_MONTH    7
-#define RTC_MONTH       8
-#define RTC_YEAR        9
-
-/* control registers - Moto names
- */
-#define RTC_REG_A       10
-#define RTC_REG_B       11
-#define RTC_REG_C       12
-#define RTC_REG_D       13
-
-/**********************************************************************
- * register details
- **********************************************************************/
-#define RTC_FREQ_SELECT RTC_REG_A
-
-/* update-in-progress  - set to "1" 244 microsecs before RTC goes off the bus,
- * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete,
- * totalling to a max high interval of 2.228 ms.
- */
-# define RTC_UIP        0x80
-# define RTC_DIV_CTL        0x70
-   /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */
-#  define RTC_REF_CLCK_4MHZ 0x00
-#  define RTC_REF_CLCK_1MHZ 0x10
-#  define RTC_REF_CLCK_32KHZ    0x20
-   /* 2 values for divider stage reset, others for "testing purposes only" */
-#  define RTC_DIV_RESET1    0x60
-#  define RTC_DIV_RESET2    0x70
-  /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */
-# define RTC_RATE_SELECT    0x0F
-
-/**********************************************************************/
-#define RTC_CONTROL RTC_REG_B
-# define RTC_SET 0x80       /* disable updates for clock setting */
-# define RTC_PIE 0x40       /* periodic interrupt enable */
-# define RTC_AIE 0x20       /* alarm interrupt enable */
-# define RTC_UIE 0x10       /* update-finished interrupt enable */
-# define RTC_SQWE 0x08      /* enable square-wave output */
-# define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */
-# define RTC_24H 0x02       /* 24 hour mode - else hours bit 7 means pm */
-# define RTC_DST_EN 0x01    /* auto switch DST - works f. USA only */
-
-/**********************************************************************/
-#define RTC_INTR_FLAGS  RTC_REG_C
-/* caution - cleared by read */
-# define RTC_IRQF 0x80      /* any of the following 3 is active */
-# define RTC_PF 0x40
-# define RTC_AF 0x20
-# define RTC_UF 0x10
-
-/**********************************************************************/
-#define RTC_VALID   RTC_REG_D
-# define RTC_VRT 0x80       /* valid RAM and time */
-/**********************************************************************/
-#endif /* _MC146818RTC_H */
diff --git a/include/linux/mtd/doc2000.h b/include/linux/mtd/doc2000.h
deleted file mode 100644
index a72cb7d20b7..00000000000
--- a/include/linux/mtd/doc2000.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Linux driver for Disk-On-Chip devices
- *
- * Copyright © 1999 Machine Vision Holdings, Inc.
- * Copyright © 1999-2010 David Woodhouse <dwmw2@infradead.org>
- * Copyright © 2002-2003 Greg Ungerer <gerg@snapgear.com>
- * Copyright © 2002-2003 SnapGear Inc
- *
- */
-
-#ifndef __MTD_DOC2000_H__
-#define __MTD_DOC2000_H__
-
-#include <linux/mtd/mtd.h>
-#if 0
-#include <linux/mutex.h>
-#endif
-
-#define DoC_Sig1 0
-#define DoC_Sig2 1
-
-#define DoC_ChipID		0x1000
-#define DoC_DOCStatus		0x1001
-#define DoC_DOCControl		0x1002
-#define DoC_FloorSelect		0x1003
-#define DoC_CDSNControl		0x1004
-#define DoC_CDSNDeviceSelect	0x1005
-#define DoC_ECCConf		0x1006
-#define DoC_2k_ECCStatus	0x1007
-
-#define DoC_CDSNSlowIO		0x100d
-#define DoC_ECCSyndrome0	0x1010
-#define DoC_ECCSyndrome1	0x1011
-#define DoC_ECCSyndrome2	0x1012
-#define DoC_ECCSyndrome3	0x1013
-#define DoC_ECCSyndrome4	0x1014
-#define DoC_ECCSyndrome5	0x1015
-#define DoC_AliasResolution	0x101b
-#define DoC_ConfigInput		0x101c
-#define DoC_ReadPipeInit	0x101d
-#define DoC_WritePipeTerm	0x101e
-#define DoC_LastDataRead	0x101f
-#define DoC_NOP			0x1020
-
-#define DoC_Mil_CDSN_IO		0x0800
-#define DoC_2k_CDSN_IO		0x1800
-
-#define DoC_Mplus_NOP			0x1002
-#define DoC_Mplus_AliasResolution	0x1004
-#define DoC_Mplus_DOCControl		0x1006
-#define DoC_Mplus_AccessStatus		0x1008
-#define DoC_Mplus_DeviceSelect		0x1008
-#define DoC_Mplus_Configuration		0x100a
-#define DoC_Mplus_OutputControl		0x100c
-#define DoC_Mplus_FlashControl		0x1020
-#define DoC_Mplus_FlashSelect		0x1022
-#define DoC_Mplus_FlashCmd		0x1024
-#define DoC_Mplus_FlashAddress		0x1026
-#define DoC_Mplus_FlashData0		0x1028
-#define DoC_Mplus_FlashData1		0x1029
-#define DoC_Mplus_ReadPipeInit		0x102a
-#define DoC_Mplus_LastDataRead		0x102c
-#define DoC_Mplus_LastDataRead1		0x102d
-#define DoC_Mplus_WritePipeTerm		0x102e
-#define DoC_Mplus_ECCSyndrome0		0x1040
-#define DoC_Mplus_ECCSyndrome1		0x1041
-#define DoC_Mplus_ECCSyndrome2		0x1042
-#define DoC_Mplus_ECCSyndrome3		0x1043
-#define DoC_Mplus_ECCSyndrome4		0x1044
-#define DoC_Mplus_ECCSyndrome5		0x1045
-#define DoC_Mplus_ECCConf		0x1046
-#define DoC_Mplus_Toggle		0x1046
-#define DoC_Mplus_DownloadStatus	0x1074
-#define DoC_Mplus_CtrlConfirm		0x1076
-#define DoC_Mplus_Power			0x1fff
-
-/* How to access the device?
- * On ARM, it'll be mmap'd directly with 32-bit wide accesses.
- * On PPC, it's mmap'd and 16-bit wide.
- * Others use readb/writeb
- */
-#if defined(__arm__)
-#define ReadDOC_(adr, reg)      ((unsigned char)(*(volatile __u32 *)(((unsigned long)adr)+((reg)<<2))))
-#define WriteDOC_(d, adr, reg)  do{ *(volatile __u32 *)(((unsigned long)adr)+((reg)<<2)) = (__u32)d; wmb();} while(0)
-#define DOC_IOREMAP_LEN 0x8000
-#elif defined(__ppc__)
-#define ReadDOC_(adr, reg)      ((unsigned char)(*(volatile __u16 *)(((unsigned long)adr)+((reg)<<1))))
-#define WriteDOC_(d, adr, reg)  do{ *(volatile __u16 *)(((unsigned long)adr)+((reg)<<1)) = (__u16)d; wmb();} while(0)
-#define DOC_IOREMAP_LEN 0x4000
-#else
-#define ReadDOC_(adr, reg)      readb((void __iomem *)(adr) + (reg))
-#define WriteDOC_(d, adr, reg)  writeb(d, (void __iomem *)(adr) + (reg))
-#define DOC_IOREMAP_LEN 0x2000
-
-#endif
-
-#if defined(__i386__) || defined(__x86_64__)
-#define USE_MEMCPY
-#endif
-
-/* These are provided to directly use the DoC_xxx defines */
-#define ReadDOC(adr, reg)      ReadDOC_(adr,DoC_##reg)
-#define WriteDOC(d, adr, reg)  WriteDOC_(d,adr,DoC_##reg)
-
-#define DOC_MODE_RESET		0
-#define DOC_MODE_NORMAL		1
-#define DOC_MODE_RESERVED1	2
-#define DOC_MODE_RESERVED2	3
-
-#define DOC_MODE_CLR_ERR	0x80
-#define	DOC_MODE_RST_LAT	0x10
-#define	DOC_MODE_BDECT		0x08
-#define DOC_MODE_MDWREN	0x04
-
-#define DOC_ChipID_Doc2k	0x20
-#define DOC_ChipID_Doc2kTSOP	0x21	/* internal number for MTD */
-#define DOC_ChipID_DocMil	0x30
-#define DOC_ChipID_DocMilPlus32	0x40
-#define DOC_ChipID_DocMilPlus16	0x41
-
-#define CDSN_CTRL_FR_B		0x80
-#define CDSN_CTRL_FR_B0		0x40
-#define CDSN_CTRL_FR_B1		0x80
-
-#define CDSN_CTRL_ECC_IO	0x20
-#define CDSN_CTRL_FLASH_IO	0x10
-#define CDSN_CTRL_WP		0x08
-#define CDSN_CTRL_ALE		0x04
-#define CDSN_CTRL_CLE		0x02
-#define CDSN_CTRL_CE		0x01
-
-#define DOC_ECC_RESET		0
-#define DOC_ECC_ERROR		0x80
-#define DOC_ECC_RW		0x20
-#define DOC_ECC__EN		0x08
-#define DOC_TOGGLE_BIT		0x04
-#define DOC_ECC_RESV		0x02
-#define DOC_ECC_IGNORE		0x01
-
-#define DOC_FLASH_CE		0x80
-#define DOC_FLASH_WP		0x40
-#define DOC_FLASH_BANK		0x02
-
-/* We have to also set the reserved bit 1 for enable */
-#define DOC_ECC_EN (DOC_ECC__EN | DOC_ECC_RESV)
-#define DOC_ECC_DIS (DOC_ECC_RESV)
-
-struct Nand {
-	char floor, chip;
-	unsigned long curadr;
-	unsigned char curmode;
-	/* Also some erase/write/pipeline info when we get that far */
-};
-
-#define MAX_FLOORS 4
-#define MAX_CHIPS 4
-
-#define MAX_FLOORS_MIL 1
-#define MAX_CHIPS_MIL 1
-
-#define MAX_FLOORS_MPLUS 2
-#define MAX_CHIPS_MPLUS 1
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-struct DiskOnChip {
-	unsigned long physadr;
-	void __iomem *virtadr;
-	unsigned long totlen;
-	unsigned char ChipID; /* Type of DiskOnChip */
-	int ioreg;
-
-	unsigned long mfr; /* Flash IDs - only one type of flash per device */
-	unsigned long id;
-	int chipshift;
-	char page256;
-	char pageadrlen;
-	char interleave; /* Internal interleaving - Millennium Plus style */
-	unsigned long erasesize;
-
-	int curfloor;
-	int curchip;
-
-	int numchips;
-	struct Nand *chips;
-	struct mtd_info *nextdoc;
-/* XXX U-BOOT XXX */
-#if 0
-	struct mutex lock;
-#endif
-};
-
-int doc_decode_ecc(unsigned char sector[512], unsigned char ecc1[6]);
-
-/* XXX U-BOOT XXX */
-#if 1
-/*
- * NAND Flash Manufacturer ID Codes
- */
-#define NAND_MFR_TOSHIBA   0x98
-#define NAND_MFR_SAMSUNG   0xec
-#endif
-
-#endif /* __MTD_DOC2000_H__ */
diff --git a/include/linux/mtd/ndfc.h b/include/linux/mtd/ndfc.h
deleted file mode 100644
index d0558a98262..00000000000
--- a/include/linux/mtd/ndfc.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- *  linux/include/linux/mtd/ndfc.h
- *
- *  Copyright (c) 2006 Thomas Gleixner <tglx@linutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  Info:
- *   Contains defines, datastructures for ndfc nand controller
- *
- */
-#ifndef __LINUX_MTD_NDFC_H
-#define __LINUX_MTD_NDFC_H
-
-/* NDFC Register definitions */
-#define NDFC_CMD		0x00
-#define NDFC_ALE		0x04
-#define NDFC_DATA		0x08
-#define NDFC_ECC		0x10
-#define NDFC_BCFG0		0x30
-#define NDFC_BCFG1		0x34
-#define NDFC_BCFG2		0x38
-#define NDFC_BCFG3		0x3c
-#define NDFC_CCR		0x40
-#define NDFC_STAT		0x44
-#define NDFC_HWCTL		0x48
-#define NDFC_REVID		0x50
-
-#define NDFC_STAT_IS_READY	0x01000000
-
-#define NDFC_CCR_RESET_CE	0x80000000 /* CE Reset */
-#define NDFC_CCR_RESET_ECC	0x40000000 /* ECC Reset */
-#define NDFC_CCR_RIE		0x20000000 /* Interrupt Enable on Device Rdy */
-#define NDFC_CCR_REN		0x10000000 /* Enable wait for Rdy in LinearR */
-#define NDFC_CCR_ROMEN		0x08000000 /* Enable ROM In LinearR */
-#define NDFC_CCR_ARE		0x04000000 /* Auto-Read Enable */
-#define NDFC_CCR_BS(x)		(((x) & 0x3) << 24) /* Select Bank on CE[x] */
-#define NDFC_CCR_BS_MASK	0x03000000 /* Select Bank */
-#define NDFC_CCR_ARAC0		0x00000000 /* 3 Addr, 1 Col 2 Row 512b page */
-#define NDFC_CCR_ARAC1		0x00001000 /* 4 Addr, 1 Col 3 Row 512b page */
-#define NDFC_CCR_ARAC2		0x00002000 /* 4 Addr, 2 Col 2 Row 2K page */
-#define NDFC_CCR_ARAC3		0x00003000 /* 5 Addr, 2 Col 3 Row 2K page */
-#define NDFC_CCR_ARAC_MASK	0x00003000 /* Auto-Read mode Addr Cycles */
-#define NDFC_CCR_RPG		0x0000C000 /* Auto-Read Page */
-#define NDFC_CCR_EBCC		0x00000004 /* EBC Configuration Completed */
-#define NDFC_CCR_DHC		0x00000002 /* Direct Hardware Control Enable */
-
-#define NDFC_BxCFG_EN		0x80000000 /* Bank Enable */
-#define NDFC_BxCFG_CED		0x40000000 /* nCE Style */
-#define NDFC_BxCFG_SZ_MASK	0x08000000 /* Bank Size */
-#define NDFC_BxCFG_SZ_8BIT	0x00000000 /* 8bit */
-#define NDFC_BxCFG_SZ_16BIT	0x08000000 /* 16bit */
-
-#define NDFC_MAX_BANKS		4
-
-struct ndfc_controller_settings {
-	uint32_t	ccr_settings;
-	uint64_t	ndfc_erpn;
-};
-
-struct ndfc_chip_settings {
-	uint32_t	bank_settings;
-};
-
-#endif