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authorRoger Quadros2024-02-28 12:35:26 +0200
committerTom Rini2024-03-07 07:59:16 -0500
commita0e02c66194593a9983229781c2c6fb51f5b052f (patch)
tree968c104f80c11796a9f38d877b4f1e136a326549 /include/phy.h
parent9e434756ad22a7a03fd8f6cf467d343479aa7435 (diff)
net: mdio: Handle bus level GPIO Reset
Some platforms have bus level Reset controlled by a GPIO line. If available then handle bus reset via GPIO. Signed-off-by: Roger Quadros <rogerq@kernel.org>
Diffstat (limited to 'include/phy.h')
-rw-r--r--include/phy.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/include/phy.h b/include/phy.h
index e02cbdb58c9..ae23814bbf3 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -9,6 +9,7 @@
#ifndef _PHY_H
#define _PHY_H
+#include <asm-generic/gpio.h>
#include <log.h>
#include <phy_interface.h>
#include <dm/ofnode.h>
@@ -76,6 +77,12 @@ struct mii_dev {
int (*reset)(struct mii_dev *bus);
struct phy_device *phymap[PHY_MAX_ADDR];
u32 phy_mask;
+ /** @reset_delay_us: Bus GPIO reset pulse width in microseconds */
+ int reset_delay_us;
+ /** @reset_post_delay_us: Bus GPIO reset deassert delay in microseconds */
+ int reset_post_delay_us;
+ /** @reset_gpiod: Bus Reset GPIO descriptor pointer */
+ struct gpio_desc reset_gpiod;
};
/* struct phy_driver: a structure which defines PHY behavior