stpmic1: update register names

Alignment with  STPMIC1 datasheet
  s/MAIN_CONTROL_REG/MAIN_CR/g
  s/MASK_RESET_BUCK/BUCKS_MRST_CR/g
  s/MASK_RESET_LDOS/LDOS_MRST_CR/g
  s/BUCKX_CTRL_REG/BUCKX_MAIN_CR/g
  s/VREF_CTRL_REG/REFDDR_MAIN_CR/g
  s/LDOX_CTRL_REG/LDOX_MAIN_CR/g
  s/USB_CTRL_REG/BST_SW_CR/g
  s/STPMIC1_NVM_USER_STATUS_REG/STPMIC1_NVM_SR/g
  s/STPMIC1_NVM_USER_CONTROL_REG/STPMIC1_NVM_CR/g
and update all the associated defines.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

1 files changed, 58 insertions, 40 deletions

diff --git a/include/power/stpmic1.h b/include/power/stpmic1.h
index 5ed67d29cfe..ea91b75cfd2 100644
--- a/include/power/stpmic1.h
+++ b/include/power/stpmic1.h
@@ -6,51 +6,69 @@
 #ifndef __PMIC_STPMIC1_H_
 #define __PMIC_STPMIC1_H_
 
-#define STPMIC1_MAIN_CONTROL_REG	0x10
-#define STPMIC1_MASK_RESET_BUCK		0x18
-#define STPMIC1_MASK_RESET_LDOS		0x1a
-#define STPMIC1_BUCKX_CTRL_REG(buck)	(0x20 + (buck))
-#define STPMIC1_VREF_CTRL_REG		0x24
-#define STPMIC1_LDOX_CTRL_REG(ldo)	(0x25 + (ldo))
-#define STPMIC1_USB_CTRL_REG		0x40
-#define STPMIC1_NVM_USER_STATUS_REG	0xb8
-#define STPMIC1_NVM_USER_CONTROL_REG	0xb9
-
-/* Main PMIC Control Register (MAIN_CONTROL_REG) */
-#define STPMIC1_CTRL_SWITCH_OFF		BIT(0)
-#define STPMIC1_CTRL_RESTART		BIT(1)
-
-#define STPMIC1_MASK_RESET_BUCK3	BIT(2)
-#define STPMIC1_MASK_RESET_BUCK_DBG	GENMASK(3, 0)
-#define STPMIC1_MASK_RESET_LDOS_DBG	0x6F
-
-#define STPMIC1_BUCK_EN			BIT(0)
-#define STPMIC1_BUCK_MODE		BIT(1)
-#define STPMIC1_BUCK_OUTPUT_MASK	GENMASK(7, 2)
-#define STPMIC1_BUCK_OUTPUT_SHIFT	2
-#define STPMIC1_BUCK2_1200000V		(24 << STPMIC1_BUCK_OUTPUT_SHIFT)
-#define STPMIC1_BUCK2_1350000V		(30 << STPMIC1_BUCK_OUTPUT_SHIFT)
-#define STPMIC1_BUCK3_1800000V		(39 << STPMIC1_BUCK_OUTPUT_SHIFT)
-
-#define STPMIC1_VREF_EN			BIT(0)
-
-#define STPMIC1_LDO_EN			BIT(0)
-#define STPMIC1_LDO12356_OUTPUT_MASK	GENMASK(6, 2)
-#define STPMIC1_LDO12356_OUTPUT_SHIFT	2
+#define STPMIC1_MAIN_CR			0x10
+#define STPMIC1_BUCKS_MRST_CR		0x18
+#define STPMIC1_LDOS_MRST_CR		0x1a
+#define STPMIC1_BUCKX_MAIN_CR(buck)	(0x20 + (buck))
+#define STPMIC1_REFDDR_MAIN_CR		0x24
+#define STPMIC1_LDOX_MAIN_CR(ldo)	(0x25 + (ldo))
+#define STPMIC1_BST_SW_CR		0x40
+#define STPMIC1_NVM_SR			0xb8
+#define STPMIC1_NVM_CR			0xb9
+
+/* Main PMIC Control Register (MAIN_CR) */
+#define STPMIC1_SWOFF			BIT(0)
+#define STPMIC1_RREQ_EN			BIT(1)
+
+/* BUCKS_MRST_CR */
+#define STPMIC1_MRST_BUCK(buck)		BIT(buck)
+#define STPMIC1_MRST_BUCK_ALL		GENMASK(3, 0)
+
+/* LDOS_MRST_CR */
+#define STPMIC1_MRST_LDO(ldo)		BIT(ldo)
+#define STPMIC1_MRST_LDO_ALL		GENMASK(6, 0)
+
+/* BUCKx_MAIN_CR (x=1...4) */
+#define STPMIC1_BUCK_ENA		BIT(0)
+#define STPMIC1_BUCK_PREG_MODE		BIT(1)
+#define STPMIC1_BUCK_VOUT_MASK		GENMASK(7, 2)
+#define STPMIC1_BUCK_VOUT_SHIFT		2
+#define STPMIC1_BUCK_VOUT(sel)		(sel << STPMIC1_BUCK_VOUT_SHIFT)
+
+#define STPMIC1_BUCK2_1200000V		STPMIC1_BUCK_VOUT(24)
+#define STPMIC1_BUCK2_1350000V		STPMIC1_BUCK_VOUT(30)
+
+#define STPMIC1_BUCK3_1800000V		STPMIC1_BUCK_VOUT(39)
+
+/* REFDDR_MAIN_CR */
+#define STPMIC1_VREF_ENA		BIT(0)
+
+/* LDOX_MAIN_CR */
+#define STPMIC1_LDO_ENA			BIT(0)
+#define STPMIC1_LDO12356_VOUT_MASK	GENMASK(6, 2)
+#define STPMIC1_LDO12356_VOUT_SHIFT	2
+#define STPMIC1_LDO_VOUT(sel)		(sel << STPMIC1_LDO12356_VOUT_SHIFT)
+
 #define STPMIC1_LDO3_MODE		BIT(7)
 #define STPMIC1_LDO3_DDR_SEL		31
-#define STPMIC1_LDO3_1800000		(9 << STPMIC1_LDO12356_OUTPUT_SHIFT)
+#define STPMIC1_LDO3_1800000		STPMIC1_LDO_VOUT(9)
+
 #define STPMIC1_LDO4_UV			3300000
 
-#define STPMIC1_USB_BOOST_EN		BIT(0)
-#define STPMIC1_USB_PWR_SW_EN		GENMASK(2, 1)
+/* BST_SW_CR */
+#define STPMIC1_BST_ON			BIT(0)
+#define STPMIC1_VBUSOTG_ON		BIT(1)
+#define STPMIC1_SWOUT_ON		BIT(2)
+#define STPMIC1_PWR_SW_ON		(STPMIC1_VBUSOTG_ON | STPMIC1_SWOUT_ON)
 
-#define STPMIC1_NVM_USER_CONTROL_PROGRAM	BIT(0)
-#define STPMIC1_NVM_USER_CONTROL_READ		BIT(1)
+/* NVM_SR */
+#define STPMIC1_NVM_BUSY		BIT(0)
 
-#define STPMIC1_NVM_USER_STATUS_BUSY		BIT(0)
-#define STPMIC1_NVM_USER_STATUS_ERROR		BIT(1)
+/* NVM_CR */
+#define STPMIC1_NVM_CMD_PROGRAM		1
+#define STPMIC1_NVM_CMD_READ		2
 
+/* Timeout */
 #define STPMIC1_DEFAULT_START_UP_DELAY_MS	1
 #define STPMIC1_DEFAULT_STOP_DELAY_MS		5
 #define STPMIC1_USB_BOOST_START_UP_DELAY_MS	10
@@ -64,8 +82,8 @@ enum {
 };
 
 enum {
-	STPMIC1_BUCK_MODE_HP,
-	STPMIC1_BUCK_MODE_LP,
+	STPMIC1_PREG_MODE_HP,
+	STPMIC1_PREG_MODE_LP,
 };
 
 enum {