diff options
| author | Mateusz Kulikowski | 2016-03-31 23:12:24 +0200 |
|---|---|---|
| committer | Tom Rini | 2016-04-01 17:18:10 -0400 |
| commit | d424efb2c495f754ebc1155db6fe0b3dcb9ec485 (patch) | |
| tree | ef1885ef861bb9f0de11cacc1b9e6bf960c1beb5 /include/usb/ehci-ci.h | |
| parent | e162c6b1a758c6bda26417c1075fef7a97fb6743 (diff) | |
usb: ehci-ci: Add missing registers.
Some registers of usb_ehci were marked as reserved.
This may be true for some variants of Chipidea USB core, but they have
meaning on other devices.
The following registers were added:
sbusstatus/sbusmode: AHB-related registers
genconfig*: Auxiluary IP core configuration registers.
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Tested-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include/usb/ehci-ci.h')
| -rw-r--r-- | include/usb/ehci-ci.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h index 725aec5ebdb..305b180bc1a 100644 --- a/include/usb/ehci-ci.h +++ b/include/usb/ehci-ci.h @@ -191,7 +191,11 @@ struct usb_ehci { u32 gptimer1_ld; /* 0x088 - General Purpose Timer 1 load value */ u32 gptimer1_ctrl; /* 0x08C - General Purpose Timer 1 control */ u32 sbuscfg; /* 0x090 - System Bus Interface Control */ - u8 res2[0x6C]; + u32 sbusstatus; /* 0x094 - System Bus Interface Status */ + u32 sbusmode; /* 0x098 - System Bus Interface Mode */ + u32 genconfig; /* 0x09C - USB Core Configuration */ + u32 genconfig2; /* 0x0A0 - USB Core Configuration 2 */ + u8 res2[0x5c]; u8 caplength; /* 0x100 - Capability Register Length */ u8 res3[0x1]; u16 hciversion; /* 0x102 - Host Interface Version */ |