Merge tag 'u-boot-imx-20220523' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20220523
-------------------

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/12087

Additionally to u-boot-imx20200520:

- DH MX8MP
- i.MX GPIO: reading GPIO when direction is output
- Menlo i.MX53: switch to DM

And from u-boot-imx20200520:

- fix Verdin hang
- add pca9450 regulator
- conversion to DM_SERIAL
- NAND block handling
- fix crypto
- enable cache on some boards
- add ACC board (MX6)

31 files changed, 276 insertions, 54 deletions

diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h
index 6da0483ef09..4c04bbf6447 100644
--- a/include/configs/cgtqmx8.h
+++ b/include/configs/cgtqmx8.h
@@ -132,6 +132,5 @@
 
 /* Networking */
 #define CONFIG_FEC_MXC_PHYADDR		-1
-#define FEC_QUIRK_ENET_MAC
 
 #endif /* __CGTQMX8_H */
diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h
index 2b14464dff1..178f5a6e7d6 100644
--- a/include/configs/dh_imx6.h
+++ b/include/configs/dh_imx6.h
@@ -30,9 +30,6 @@
 /* Bootcounter */
 #define CONFIG_SYS_BOOTCOUNT_BE
 
-/* FEC ethernet */
-#define CONFIG_FEC_MXC_PHYADDR		7
-
 /* MMC Configs */
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
 #define CONFIG_SYS_FSL_USDHC_NUM	3
diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h
index bb53a33a542..6790053bb8d 100644
--- a/include/configs/imx27lite-common.h
+++ b/include/configs/imx27lite-common.h
@@ -70,7 +70,7 @@
 /*
  * Serial Driver info
  */
-#define CONFIG_MXC_UART_BASE	UART1_BASE
+#define CONFIG_MXC_UART_BASE	UART_BASE_ADDR(1)
 
 /*
  * Flash & Environment
diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h
new file mode 100644
index 00000000000..6d362557ac6
--- /dev/null
+++ b/include/configs/imx6q-bosch-acc.h
@@ -0,0 +1,122 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (c) 2017 DENX Software Engineering GmbH, Heiko Schocher <hs@denx.de>
+ * Copyright (c) 2019 Bosch Thermotechnik GmbH
+ * Copyright (c) 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro@denx.de>
+ */
+
+#ifndef __IMX6Q_ACC_H
+#define __IMX6Q_ACC_H
+
+#include <linux/sizes.h>
+#include "mx6_common.h"
+
+#ifdef CONFIG_SYS_BOOT_EMMC
+#define MMC_ROOTFS_DEV 0
+#define MMC_ROOTFS_PART 2
+#endif
+
+#ifdef CONFIG_SYS_BOOT_EMMC
+/* eMMC Boot */
+#define ENV_EXTRA \
+	"mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \
+	"mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \
+	"fitpart=1\0" \
+	"optargs=ro quiet systemd.gpt_auto=false\0" \
+	"production=1\0" \
+	"mmcautodetect=yes\0" \
+	"mmcrootfstype=ext4\0" \
+	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
+	"mmcargs=run finduuid; setenv bootargs " \
+		"root=PARTUUID=${uuid} ${optargs} rootfstype=${mmcrootfstype}\0" \
+	"mmc_mmc_fit=run env_persist; run setbm; run mmcloadfit; " \
+		"run auth_fit_or_reset; run mmcargs addcon; " \
+		"bootm ${fit_addr}#${bootconf}\0" \
+	"bootset=0\0" \
+	"setbm=if test ${bootset} -eq 1; " \
+		"then setenv mmcpart 4; setenv fitpart 3; " \
+		"else; setenv mmcpart 2; setenv fitpart 1; fi\0" \
+	"handle_ustate=if test ${ustate} -eq 2; then setenv ustate 3; fi\0" \
+	"switch_bootset=if test ${bootset} -eq 1; then setenv bootset 0; " \
+		"else; setenv bootset 1;fi\0" \
+	"env_persisted=0\0" \
+	"env_persist=if test ${env_persisted} != 1; " \
+		"then env set env_persisted 1; run save_env; fi;\0" \
+	"save_env=env save; env save\0" \
+	"altbootcmd=run handle_ustate; run switch_bootset; run save_env; run bootcmd\0"
+
+#define CONFIG_ENV_FLAGS_LIST_STATIC \
+	"bootset:bw," \
+	"clone_pending:bw," \
+	"endurance_test:bw," \
+	"env_persisted:bw," \
+	"factory_reset:bw," \
+	"fdtcontroladdr:xw," \
+	"fitpart:dw," \
+	"mmcpart:dw," \
+	"production:bw," \
+	"ustate:dw"
+
+#else
+/* SD Card boot */
+#define ENV_EXTRA \
+	"mmcdev=1\0" \
+	"fitpart=1\0" \
+	"rootpart=2\0" \
+	"optargs=ro systemd.gpt_auto=false\0" \
+	"finduuid=part uuid mmc ${mmcdev}:${rootpart} uuid\0" \
+	"mmcargs=run finduuid;setenv bootargs root=PARTUUID=${uuid} ${optargs}\0" \
+	"mmc_mmc_fit=run mmcloadfit; run auth_fit_or_reset; run mmcargs addcon; " \
+		"bootm ${fit_addr}#${bootconf}\0"
+
+#endif
+
+/* Default environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"bootconf=conf-imx6q-bosch-acc.dtb\0"\
+	"mmcfit_name=fitImage\0" \
+	"mmcloadfit=ext4load mmc ${mmcdev}:${fitpart} ${fit_addr} ${mmcfit_name}\0" \
+	"auth_fit_or_reset=hab_auth_img ${fit_addr} ${filesize} || reset\0" \
+	"console=ttymxc0\0" \
+	"addcon=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \
+	"fit_addr=19000000\0" \
+	ENV_EXTRA
+
+/* Physical Memory Map */
+#define PHYS_SDRAM                      MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR        IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE        IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* SPL */
+#ifdef CONFIG_SPL
+#include "imx6_spl.h"
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+
+#ifdef CONFIG_SYS_BOOT_EMMC
+
+/* Boot from eMMC */
+#define CONFIG_SYS_FSL_ESDHC_ADDR 1
+
+#else
+
+/* Boot from SD-card */
+#  define CONFIG_SYS_FSL_ESDHC_ADDR	0
+
+#endif
+
+#endif
+#endif
+
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC            (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS             0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT  1	/* Enabled USB controller number */
+
+#endif /* __IMX6Q_ACC_H */
diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h
index c20c32b6951..8d9212ec64c 100644
--- a/include/configs/imx8mm-cl-iot-gate.h
+++ b/include/configs/imx8mm-cl-iot-gate.h
@@ -145,7 +145,7 @@
 #define PHYS_SDRAM			0x40000000
 #define PHYS_SDRAM_SIZE			0x80000000 /* 2GB DDR */
 
-#define CONFIG_MXC_UART_BASE		UART3_BASE_ADDR
+#define CONFIG_MXC_UART_BASE		UART_BASE_ADDR(3)
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		2048
@@ -160,7 +160,6 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
 
 #define CONFIG_FEC_MXC_PHYADDR		0
-#define FEC_QUIRK_ENET_MAC
 
 /* USB Configs */
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
diff --git a/include/configs/imx8mm-mx8menlo.h b/include/configs/imx8mm-mx8menlo.h
index fd1831622f0..530ecd1d460 100644
--- a/include/configs/imx8mm-mx8menlo.h
+++ b/include/configs/imx8mm-mx8menlo.h
@@ -30,7 +30,4 @@
 	"initrd_addr=0x43800000\0"					\
 	"kernel_image=fitImage\0"
 
-#undef CONFIG_MXC_UART_BASE
-#define CONFIG_MXC_UART_BASE		UART2_BASE_ADDR
-
 #endif /* __IMX8MM_MX8MENLO_H */
diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h
index 7c17f14964f..573ddaf2952 100644
--- a/include/configs/imx8mm_beacon.h
+++ b/include/configs/imx8mm_beacon.h
@@ -91,7 +91,7 @@
 #define PHYS_SDRAM			0x40000000
 #define PHYS_SDRAM_SIZE		0x80000000 /* 2GB DDR */
 
-#define CONFIG_MXC_UART_BASE		UART2_BASE_ADDR
+#define CONFIG_MXC_UART_BASE		UART_BASE_ADDR(2)
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		2048
diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h
index 33778a2365e..67667dd523d 100644
--- a/include/configs/imx8mm_data_modul_edm_sbc.h
+++ b/include/configs/imx8mm_data_modul_edm_sbc.h
@@ -41,8 +41,6 @@
 #define PHYS_SDRAM			0x40000000
 #define PHYS_SDRAM_SIZE			0x40000000 /* Minimum 1 GiB DDR */
 
-#define CONFIG_MXC_UART_BASE		UART3_BASE_ADDR
-
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		2048
 #define CONFIG_SYS_MAXARGS		64
@@ -52,7 +50,6 @@
 
 /* PHY needs a longer autonegotiation timeout after reset */
 #define PHY_ANEG_TIMEOUT		20000
-#define FEC_QUIRK_ENET_MAC
 
 /* USDHC */
 #define CONFIG_SYS_FSL_USDHC_NUM	2
diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h
index 42b78485cfc..5e8f19c43fb 100644
--- a/include/configs/imx8mm_evk.h
+++ b/include/configs/imx8mm_evk.h
@@ -68,7 +68,7 @@
 #define PHYS_SDRAM                      0x40000000
 #define PHYS_SDRAM_SIZE			0x80000000 /* 2GB DDR */
 
-#define CONFIG_MXC_UART_BASE		UART2_BASE_ADDR
+#define CONFIG_MXC_UART_BASE		UART_BASE_ADDR(2)
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		2048
@@ -78,6 +78,5 @@
 					sizeof(CONFIG_SYS_PROMPT) + 16)
 
 #define CONFIG_FEC_MXC_PHYADDR          0
-#define FEC_QUIRK_ENET_MAC
 
 #endif
diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h
index f521add5b04..b9b24a8c51d 100644
--- a/include/configs/imx8mm_icore_mx8mm.h
+++ b/include/configs/imx8mm_icore_mx8mm.h
@@ -66,7 +66,7 @@
 #define CONFIG_SYS_BOOTM_LEN		SZ_256M
 
 /* UART */
-#define CONFIG_MXC_UART_BASE		UART2_BASE_ADDR
+#define CONFIG_MXC_UART_BASE		UART_BASE_ADDR(2)
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		2048
diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h
index 1b26e0280e1..9836d5b73ca 100644
--- a/include/configs/imx8mm_venice.h
+++ b/include/configs/imx8mm_venice.h
@@ -102,7 +102,7 @@
 #define CONFIG_SYS_BOOTM_LEN		SZ_256M
 
 /* UART */
-#define CONFIG_MXC_UART_BASE		UART2_BASE_ADDR
+#define CONFIG_MXC_UART_BASE		UART_BASE_ADDR(2)
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		SZ_2K
@@ -111,8 +111,4 @@
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)
 
-/* FEC */
-#define CONFIG_FEC_MXC_PHYADDR          0
-#define FEC_QUIRK_ENET_MAC
-
 #endif
diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h
index 41ce3c1c8ce..79c6b1076ff 100644
--- a/include/configs/imx8mn_beacon.h
+++ b/include/configs/imx8mn_beacon.h
@@ -107,7 +107,7 @@
 #define PHYS_SDRAM_SIZE		0x40000000 /* 1GB DDR */
 #endif
 
-#define CONFIG_MXC_UART_BASE		UART2_BASE_ADDR
+#define CONFIG_MXC_UART_BASE		UART_BASE_ADDR(2)
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE              2048
diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h
index 034132225c6..805ae2a7518 100644
--- a/include/configs/imx8mn_evk.h
+++ b/include/configs/imx8mn_evk.h
@@ -75,7 +75,7 @@
 #define PHYS_SDRAM                      0x40000000
 #define PHYS_SDRAM_SIZE			0x80000000 /* 2GB DDR */
 
-#define CONFIG_MXC_UART_BASE		UART2_BASE_ADDR
+#define CONFIG_MXC_UART_BASE		UART_BASE_ADDR(2)
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		2048
diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h
index 318289b76bc..00358892b28 100644
--- a/include/configs/imx8mn_var_som.h
+++ b/include/configs/imx8mn_var_som.h
@@ -64,7 +64,7 @@
 #define PHYS_SDRAM			0x40000000
 #define PHYS_SDRAM_SIZE			SZ_1G /* 1GB DDR */
 
-#define CONFIG_MXC_UART_BASE		UART4_BASE_ADDR
+#define CONFIG_MXC_UART_BASE		UART_BASE_ADDR(4)
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		SZ_2K
diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h
index a4826779022..3cbe11a9035 100644
--- a/include/configs/imx8mn_venice.h
+++ b/include/configs/imx8mn_venice.h
@@ -98,7 +98,7 @@
 #define CONFIG_SYS_BOOTM_LEN		SZ_256M
 
 /* UART */
-#define CONFIG_MXC_UART_BASE		UART2_BASE_ADDR
+#define CONFIG_MXC_UART_BASE		UART_BASE_ADDR(2)
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		SZ_2K
@@ -107,8 +107,4 @@
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)
 
-/* FEC */
-#define CONFIG_FEC_MXC_PHYADDR          0
-#define FEC_QUIRK_ENET_MAC
-
 #endif
diff --git a/include/configs/imx8mp_dhcom_pdk2.h b/include/configs/imx8mp_dhcom_pdk2.h
new file mode 100644
index 00000000000..7d5403fa9f4
--- /dev/null
+++ b/include/configs/imx8mp_dhcom_pdk2.h
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 Marek Vasut <marex@denx.de>
+ */
+
+#ifndef __IMX8MP_DHCOM_PDK2_H
+#define __IMX8MP_DHCOM_PDK2_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_SYS_BOOTM_LEN		SZ_128M
+
+#define CONFIG_SPL_MAX_SIZE		(148 * 1024)
+#define CONFIG_SYS_MONITOR_LEN		SZ_1M
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_STACK		0x96FC00
+#define CONFIG_SPL_BSS_START_ADDR	0x0096FC00
+#define CONFIG_SPL_BSS_MAX_SIZE		0x400	/* 1 KiB */
+#define CONFIG_SYS_SPL_MALLOC_START	0x4c000000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	SZ_512K	/* 512 kiB */
+
+/* For RAW image gives a error info not panic */
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#endif
+
+/* Link Definitions */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x200000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define PHYS_SDRAM			0x40000000
+#define PHYS_SDRAM_SIZE			0x20000000 /* Minimum 512 MiB DDR */
+
+#define CONFIG_MXC_UART_BASE		UART1_BASE_ADDR
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		2048
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* PHY needs a longer autonegotiation timeout after reset */
+#define PHY_ANEG_TIMEOUT		20000
+#define FEC_QUIRK_ENET_MAC
+
+/* USDHC */
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+
+#if !defined(CONFIG_SPL_BUILD)
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"altbootcmd=run bootcmd ; reset\0"				\
+	"bootlimit=3\0"							\
+	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0"		\
+	"pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0"	\
+	"ramdisk_addr_r=0x58000000\0"					\
+	"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0"		\
+	/* Give slow devices beyond USB HUB chance to come up. */	\
+	"usb_pgood_delay=2000\0"					\
+	"dfu_alt_info="							\
+		/* RAM block at DRAM offset 256..768 MiB */		\
+		"ram ram0=ram ram 0x50000000 0x20000000&"		\
+		/* 16 MiB SPI NOR */					\
+		"mtd nor0=sf raw 0x0 0x1000000\0"			\
+	"dh_update_env="						\
+		"setenv dh_update_env true ; saveenv ; saveenv\0"	\
+	"dh_update_sf_gen_fcfb="					\
+		"setexpr sfaddr ${loadaddr} - 0x1000 ; "		\
+		"base ${sfaddr} ; "					\
+		"mw 0 0 0x400 ; "					\
+		"mw 0x400 0x42464346 ; "				\
+		"mw 0x404 0x56010000 ; "				\
+		"mw 0x40c 00030300 ; "					\
+		"mw 0x444 0x00020101 ; "				\
+		"mw 0x450 0x10000000 ; "				\
+		"mw 0x480 0x0818040b ; "				\
+		"mw 0x484 0x24043008 ; "				\
+		"mw 0x5c0 0x100 ; "					\
+		"mw 0x5c4 0x10000 ; "					\
+		"base 0\0"						\
+	"dh_update_sf_write_data="					\
+		"setexpr sfaddr ${loadaddr} - 0x1000 ; "		\
+		"setexpr filesize ${filesize} + 0x1000 ; "		\
+		"sf probe && sf update ${sfaddr} 0 ${filesize}\0"	\
+	"dh_update_sd_to_sf="						\
+		"load mmc 0:1 ${loadaddr} boot/flash.bin && "		\
+		"run dh_update_sf_gen_fcfb dh_update_sf_write_data\0"	\
+	"dh_update_emmc_to_sf="						\
+		"load mmc 1:1 ${loadaddr} boot/flash.bin && "		\
+		"run dh_update_sf_gen_fcfb dh_update_sf_write_data\0"	\
+	BOOTENV
+
+#define BOOT_TARGET_DEVICES(func)	\
+	func(MMC, mmc, 0)		\
+	func(MMC, mmc, 1)		\
+	func(USB, usb, 0)		\
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#endif
+
+#endif
diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h
index cc8d65cb54e..1e7c44c42a4 100644
--- a/include/configs/imx8mp_evk.h
+++ b/include/configs/imx8mp_evk.h
@@ -32,7 +32,6 @@
 
 #if defined(CONFIG_CMD_NET)
 #define CONFIG_FEC_MXC_PHYADDR          1
-#define FEC_QUIRK_ENET_MAC
 
 #define DWC_NET_PHYADDR			1
 
@@ -80,7 +79,7 @@
 #define PHYS_SDRAM_2			0x100000000
 #define PHYS_SDRAM_2_SIZE		0xC0000000	/* 3 GB */
 
-#define CONFIG_MXC_UART_BASE		UART2_BASE_ADDR
+#define CONFIG_MXC_UART_BASE		UART_BASE_ADDR(2)
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		2048
diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h
index c5dd545471e..52e8ea8f86a 100644
--- a/include/configs/imx8mp_rsb3720.h
+++ b/include/configs/imx8mp_rsb3720.h
@@ -51,7 +51,6 @@
 /* ENET1 */
 #if defined(CONFIG_CMD_NET)
 #define CONFIG_FEC_MXC_PHYADDR          4
-#define FEC_QUIRK_ENET_MAC
 
 #define DWC_NET_PHYADDR			4
 #ifdef CONFIG_DWC_ETH_QOS
@@ -169,8 +168,6 @@
 #define PHYS_SDRAM_2_SIZE		0x80000000	/* 2 GB */
 #endif
 
-#define CONFIG_MXC_UART_BASE		UART3_BASE_ADDR
-
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		2048
 #define CONFIG_SYS_MAXARGS		64
diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h
index aa0396db8b8..4120e4cc6ba 100644
--- a/include/configs/imx8mp_venice.h
+++ b/include/configs/imx8mp_venice.h
@@ -106,4 +106,8 @@
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* FEC */
+#define FEC_QUIRK_ENET_MAC
+
 #endif
diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h
index 989486aa6dc..6eecfc813a4 100644
--- a/include/configs/imx8mq_cm.h
+++ b/include/configs/imx8mq_cm.h
@@ -71,7 +71,7 @@
 #define PHYS_SDRAM                      0x40000000
 #define PHYS_SDRAM_SIZE					0x40000000 /* 1 GB DDR */
 
-#define CONFIG_MXC_UART_BASE		UART1_BASE_ADDR
+#define CONFIG_MXC_UART_BASE		UART_BASE_ADDR(1)
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		1024
diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h
index f7929e5867e..e31f4135ae5 100644
--- a/include/configs/imx8mq_evk.h
+++ b/include/configs/imx8mq_evk.h
@@ -37,7 +37,6 @@
 /* ENET1 */
 #if defined(CONFIG_CMD_NET)
 #define CONFIG_FEC_MXC_PHYADDR          0
-#define FEC_QUIRK_ENET_MAC
 #endif
 
 #ifndef CONFIG_SPL_BUILD
@@ -78,7 +77,7 @@
 #define PHYS_SDRAM                      0x40000000
 #define PHYS_SDRAM_SIZE			0xC0000000 /* 3GB DDR */
 
-#define CONFIG_MXC_UART_BASE		UART1_BASE_ADDR
+#define CONFIG_MXC_UART_BASE		UART_BASE_ADDR(1)
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		1024
diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h
index f6410114b76..57e45b0447c 100644
--- a/include/configs/imx8mq_phanbell.h
+++ b/include/configs/imx8mq_phanbell.h
@@ -31,7 +31,6 @@
 /* ENET1 */
 #if defined(CONFIG_CMD_NET)
 #define CONFIG_FEC_MXC_PHYADDR          0
-#define FEC_QUIRK_ENET_MAC
 #endif
 
 #define CONFIG_MFG_ENV_SETTINGS \
@@ -106,7 +105,7 @@
 #define PHYS_SDRAM                      0x40000000
 #define PHYS_SDRAM_SIZE			0x40000000 /* 1GB DDR */
 
-#define CONFIG_MXC_UART_BASE		UART1_BASE_ADDR
+#define CONFIG_MXC_UART_BASE		UART_BASE_ADDR(1)
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		1024
diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h
index 1b429f7dbe2..231571b05eb 100644
--- a/include/configs/kontron-sl-mx8mm.h
+++ b/include/configs/kontron-sl-mx8mm.h
@@ -28,7 +28,7 @@
 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
 /* Board and environment settings */
-#define CONFIG_MXC_UART_BASE		UART3_BASE_ADDR
+#define CONFIG_MXC_UART_BASE		UART_BASE_ADDR(3)
 #define CONFIG_HOSTNAME			"kontron-mx8mm"
 
 #ifdef CONFIG_USB_EHCI_HCD
@@ -70,8 +70,6 @@
 #define CONFIG_MALLOC_F_ADDR		0x930000
 #endif
 
-#define FEC_QUIRK_ENET_MAC
-
 #define ENV_MEM_LAYOUT_SETTINGS \
 	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
 	"kernel_addr_r=0x42000000\0" \
diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h
index e8e92920dcb..1834991ac3b 100644
--- a/include/configs/kontron_pitx_imx8m.h
+++ b/include/configs/kontron_pitx_imx8m.h
@@ -38,7 +38,6 @@
 /* ENET1 Config */
 #if defined(CONFIG_CMD_NET)
 #define CONFIG_FEC_MXC_PHYADDR          0
-#define FEC_QUIRK_ENET_MAC
 
 #define PHY_ANEG_TIMEOUT		20000
 
@@ -84,7 +83,7 @@
 #define PHYS_SDRAM                      0x40000000
 #define PHYS_SDRAM_SIZE			0xC0000000 /* 3GB DDR */
 
-#define CONFIG_MXC_UART_BASE		UART3_BASE_ADDR
+#define CONFIG_MXC_UART_BASE		UART_BASE_ADDR(3)
 
 #define CONFIG_SYS_FSL_USDHC_NUM	2
 #define CONFIG_SYS_FSL_ESDHC_ADDR       0
diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h
index 71f0c42ec0c..46fadd56106 100644
--- a/include/configs/phycore_imx8mm.h
+++ b/include/configs/phycore_imx8mm.h
@@ -84,7 +84,7 @@
 #define PHYS_SDRAM_SIZE                 SZ_2G /* 2GB DDR */
 
 /* UART */
-#define CONFIG_MXC_UART_BASE		UART3_BASE_ADDR
+#define CONFIG_MXC_UART_BASE		UART_BASE_ADDR(3)
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		SZ_2K
diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h
index 0c963b62b3b..eb92c423392 100644
--- a/include/configs/phycore_imx8mp.h
+++ b/include/configs/phycore_imx8mp.h
@@ -84,7 +84,7 @@
 #define PHYS_SDRAM_SIZE			0x80000000
 
 /* UART */
-#define CONFIG_MXC_UART_BASE		UART1_BASE_ADDR
+#define CONFIG_MXC_UART_BASE		UART_BASE_ADDR(1)
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		SZ_2K
diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h
index 95845276e7b..1dc7d352590 100644
--- a/include/configs/pico-imx8mq.h
+++ b/include/configs/pico-imx8mq.h
@@ -31,7 +31,6 @@
 /* ENET1 */
 #if defined(CONFIG_CMD_NET)
 #define CONFIG_FEC_MXC_PHYADDR		1
-#define FEC_QUIRK_ENET_MAC
 #endif
 
 /* Initial environment variables */
@@ -85,7 +84,7 @@
 #define PHYS_SDRAM			0x40000000
 #define PHYS_SDRAM_SIZE			0x80000000	/* 2 GiB DDR */
 
-#define CONFIG_MXC_UART_BASE		UART1_BASE_ADDR
+#define CONFIG_MXC_UART_BASE		UART_BASE_ADDR(1)
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		1024
diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h
index da3dc95f9ee..cd950ad055e 100644
--- a/include/configs/verdin-imx8mm.h
+++ b/include/configs/verdin-imx8mm.h
@@ -84,7 +84,7 @@
 #define PHYS_SDRAM_SIZE			SZ_2G /* 2GB DDR */
 
 /* UART */
-#define CONFIG_MXC_UART_BASE		UART1_BASE_ADDR
+#define CONFIG_MXC_UART_BASE		UART_BASE_ADDR(1)
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		SZ_2K
@@ -95,7 +95,6 @@
 
 /* ENET */
 #define CONFIG_FEC_MXC_PHYADDR          7
-#define FEC_QUIRK_ENET_MAC
 
 /* USB Configs */
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h
index 7b7407752c1..470f64d5a74 100644
--- a/include/configs/verdin-imx8mp.h
+++ b/include/configs/verdin-imx8mp.h
@@ -36,7 +36,6 @@
 /* ENET1 */
 #if defined(CONFIG_CMD_NET)
 #define CONFIG_FEC_MXC_PHYADDR		7
-#define FEC_QUIRK_ENET_MAC
 
 #define PHY_ANEG_TIMEOUT 20000
 #endif /* CONFIG_CMD_NET */
@@ -101,7 +100,7 @@
 #define PHYS_SDRAM_2_SIZE		(SZ_4G + SZ_1G)
 
 /* UART */
-#define CONFIG_MXC_UART_BASE		UART3_BASE_ADDR
+#define CONFIG_MXC_UART_BASE		UART_BASE_ADDR(3)
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		SZ_2K
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index 7b6e3e2c20d..d57c4ca820c 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -48,7 +48,11 @@ struct rng4tst {
 	u32 rtmctl;		/* misc. control register */
 	u32 rtscmisc;		/* statistical check misc. register */
 	u32 rtpkrrng;		/* poker range register */
-#define RTSDCTL_ENT_DLY_MIN	3200
+#ifdef CONFIG_MX6SX
+#define RTSDCTL_ENT_DLY		12000
+#else
+#define RTSDCTL_ENT_DLY		3200
+#endif
 #define RTSDCTL_ENT_DLY_MAX	12800
 	union {
 		u32 rtpkrmax;	/* PRGM=1: poker max. limit register */
diff --git a/include/power/pca9450.h b/include/power/pca9450.h
index 27703bb1f91..fa0405fcb87 100644
--- a/include/power/pca9450.h
+++ b/include/power/pca9450.h
@@ -56,4 +56,15 @@ enum {
 
 int power_pca9450_init(unsigned char bus, unsigned char addr);
 
+enum {
+	NXP_CHIP_TYPE_PCA9450A = 0,
+	NXP_CHIP_TYPE_PCA9450BC,
+	NXP_CHIP_TYPE_AMOUNT
+};
+
+#define PCA9450_DVS_BUCK_RUN_MASK	0x7f
+#define PCA9450_LDO12_MASK		0x07
+#define PCA9450_LDO34_MASK		0x1f
+#define PCA9450_LDO5_MASK		0x0f
+
 #endif