* Code cleanup

* Patch by Sascha Hauer, 28 Jun:
  - add generic support for Motorola i.MX architecture
  - add support for mx1ads, mx1fs2 and scb9328 boards

* Patches by Marc Leeman, 23 Jul 2004:
  - Add define for the PCI/Memory Buffer Configuration Register
  - corrected comments in cpu/mpc824x/cpu_init.c

* Add support for multiple serial interfaces
  (for example to allow modem dial-in / dial-out)

13 files changed, 1332 insertions, 1113 deletions

diff --git a/include/asm-arm/arch-arm920t/imx-regs.h b/include/asm-arm/arch-arm920t/imx-regs.h
new file mode 100644
index 00000000000..1486b74c2a3
--- /dev/null
+++ b/include/asm-arm/arch-arm920t/imx-regs.h
@@ -0,0 +1,571 @@
+#ifndef _IMX_REGS_H
+#define _IMX_REGS_H
+/* ------------------------------------------------------------------------
+ *  Motorola IMX system registers
+ * ------------------------------------------------------------------------
+ *
+ */
+
+# ifndef __ASSEMBLY__
+#  define __REG(x)	(*((volatile u32 *)(x)))
+# define __REG2(x,y)	\
+	( __builtin_constant_p(y) ? (__REG((x) + (y))) \
+			  : (*(volatile u32 *)((u32)&__REG(x) + (y))) )
+# else
+#  define __REG(x) (x)
+#  define __REG2(x,y) ((x)+(y))
+#endif
+
+#define IMX_IO_BASE		0x00200000
+
+/*
+ *  Register BASEs, based on OFFSETs
+ *
+ */
+#define IMX_AIPI1_BASE             (0x00000 + IMX_IO_BASE)
+#define IMX_WDT_BASE               (0x01000 + IMX_IO_BASE)
+#define IMX_TIM1_BASE              (0x02000 + IMX_IO_BASE)
+#define IMX_TIM2_BASE              (0x03000 + IMX_IO_BASE)
+#define IMX_RTC_BASE               (0x04000 + IMX_IO_BASE)
+#define IMX_LCDC_BASE              (0x05000 + IMX_IO_BASE)
+#define IMX_UART1_BASE             (0x06000 + IMX_IO_BASE)
+#define IMX_UART2_BASE             (0x07000 + IMX_IO_BASE)
+#define IMX_PWM_BASE               (0x08000 + IMX_IO_BASE)
+#define IMX_DMAC_BASE              (0x09000 + IMX_IO_BASE)
+#define IMX_AIPI2_BASE             (0x10000 + IMX_IO_BASE)
+#define IMX_SIM_BASE               (0x11000 + IMX_IO_BASE)
+#define IMX_USBD_BASE              (0x12000 + IMX_IO_BASE)
+#define IMX_SPI1_BASE              (0x13000 + IMX_IO_BASE)
+#define IMX_MMC_BASE               (0x14000 + IMX_IO_BASE)
+#define IMX_ASP_BASE               (0x15000 + IMX_IO_BASE)
+#define IMX_BTA_BASE               (0x16000 + IMX_IO_BASE)
+#define IMX_I2C_BASE               (0x17000 + IMX_IO_BASE)
+#define IMX_SSI_BASE               (0x18000 + IMX_IO_BASE)
+#define IMX_SPI2_BASE              (0x19000 + IMX_IO_BASE)
+#define IMX_MSHC_BASE              (0x1A000 + IMX_IO_BASE)
+#define IMX_PLL_BASE               (0x1B000 + IMX_IO_BASE)
+#define IMX_SYSCTRL_BASE           (0x1B800 + IMX_IO_BASE)
+#define IMX_GPIO_BASE              (0x1C000 + IMX_IO_BASE)
+#define IMX_EIM_BASE               (0x20000 + IMX_IO_BASE)
+#define IMX_SDRAMC_BASE            (0x21000 + IMX_IO_BASE)
+#define IMX_MMA_BASE               (0x22000 + IMX_IO_BASE)
+#define IMX_AITC_BASE              (0x23000 + IMX_IO_BASE)
+#define IMX_CSI_BASE               (0x24000 + IMX_IO_BASE)
+
+/* SYSCTRL Registers */
+#define SIDR   __REG(IMX_SYSCTRL_BASE + 0x4) /* Silicon ID Register		    */
+#define FMCR   __REG(IMX_SYSCTRL_BASE + 0x8) /* Function Multiplex Control Register */
+#define GPCR   __REG(IMX_SYSCTRL_BASE + 0xC) /* Function Multiplex Control Register */
+
+/* Chip Select Registers */
+#define CS0U __REG(IMX_EIM_BASE)        /* Chip Select 0 Upper Register */
+#define CS0L __REG(IMX_EIM_BASE + 0x4)  /* Chip Select 0 Lower Register */
+#define CS1U __REG(IMX_EIM_BASE + 0x8)  /* Chip Select 1 Upper Register */
+#define CS1L __REG(IMX_EIM_BASE + 0xc)  /* Chip Select 1 Lower Register */
+#define CS2U __REG(IMX_EIM_BASE + 0x10) /* Chip Select 2 Upper Register */
+#define CS2L __REG(IMX_EIM_BASE + 0x14) /* Chip Select 2 Lower Register */
+#define CS3U __REG(IMX_EIM_BASE + 0x18) /* Chip Select 3 Upper Register */
+#define CS3L __REG(IMX_EIM_BASE + 0x1c) /* Chip Select 3 Lower Register */
+#define CS4U __REG(IMX_EIM_BASE + 0x20) /* Chip Select 4 Upper Register */
+#define CS4L __REG(IMX_EIM_BASE + 0x24) /* Chip Select 4 Lower Register */
+#define CS5U __REG(IMX_EIM_BASE + 0x28) /* Chip Select 5 Upper Register */
+#define CS5L __REG(IMX_EIM_BASE + 0x2c) /* Chip Select 5 Lower Register */
+#define EIM  __REG(IMX_EIM_BASE + 0x30) /* EIM Configuration Register */
+
+/* SDRAM controller registers */
+
+#define SDCTL0 __REG(IMX_SDRAMC_BASE)        /* SDRAM 0 Control Register */
+#define SDCTL1 __REG(IMX_SDRAMC_BASE + 0x4)  /* SDRAM 1 Control Register */
+#define SDMISC __REG(IMX_SDRAMC_BASE + 0x14) /* Miscellaneous Register */
+#define SDRST  __REG(IMX_SDRAMC_BASE + 0x18) /* SDRAM Reset Register */
+
+/* PLL registers */
+#define CSCR   __REG(IMX_PLL_BASE)        /* Clock Source Control Register */
+#define MPCTL0 __REG(IMX_PLL_BASE + 0x4)  /* MCU PLL Control Register 0 */
+#define MPCTL1 __REG(IMX_PLL_BASE + 0x8)  /* MCU PLL and System Clock Register 1 */
+#define SPCTL0 __REG(IMX_PLL_BASE + 0xc)  /* System PLL Control Register 0 */
+#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
+#define PCDR   __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */
+
+#define CSCR_MPLL_RESTART (1<<21)
+
+/*
+ *  GPIO Module and I/O Multiplexer
+ *  x = 0..3 for reg_A, reg_B, reg_C, reg_D
+ */
+#define DDIR(x)    __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8)
+#define OCR1(x)    __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8)
+#define OCR2(x)    __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8)
+#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8)
+#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8)
+#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8)
+#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8)
+#define DR(x)      __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8)
+#define GIUS(x)    __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8)
+#define SSR(x)     __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8)
+#define ICR1(x)    __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8)
+#define ICR2(x)    __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8)
+#define IMR(x)     __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8)
+#define ISR(x)     __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8)
+#define GPR(x)     __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8)
+#define SWR(x)     __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8)
+#define PUEN(x)    __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8)
+
+#define GPIO_PIN_MASK 0x1f
+#define GPIO_PORT_MASK (0x3 << 5)
+
+#define GPIO_PORTA (0<<5)
+#define GPIO_PORTB (1<<5)
+#define GPIO_PORTC (2<<5)
+#define GPIO_PORTD (3<<5)
+
+#define GPIO_OUT   (1<<7)
+#define GPIO_IN    (0<<7)
+#define GPIO_PUEN  (1<<8)
+
+#define GPIO_PF    (0<<9)
+#define GPIO_AF    (1<<9)
+
+#define GPIO_OCR_MASK (3<<10)
+#define GPIO_AIN   (0<<10)
+#define GPIO_BIN   (1<<10)
+#define GPIO_CIN   (2<<10)
+#define GPIO_GPIO  (3<<10)
+
+#define GPIO_AOUT  (1<<12)
+#define GPIO_BOUT  (1<<13)
+
+/* assignements for GPIO alternate/primary functions */
+
+/* FIXME: This list is not completed. The correct directions are
+ * missing on some (many) pins
+ */
+#define PA0_PF_A24           ( GPIO_PORTA | GPIO_PF | 0 )
+#define PA0_AIN_SPI2_CLK     ( GPIO_PORTA | GPIO_OUT | GPIO_AIN | 0 )
+#define PA0_AF_ETMTRACESYNC  ( GPIO_PORTA | GPIO_AF | 0 )
+#define PA1_AOUT_SPI2_RXD    ( GPIO_PORTA | GPIO_IN | GPIO_AOUT | 1 )
+#define PA1_PF_TIN           ( GPIO_PORTA | GPIO_PF | 1 )
+#define PA2_PF_PWM0          ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 )
+#define PA3_PF_CSI_MCLK      ( GPIO_PORTA | GPIO_PF | 3 )
+#define PA4_PF_CSI_D0        ( GPIO_PORTA | GPIO_PF | 4 )
+#define PA5_PF_CSI_D1        ( GPIO_PORTA | GPIO_PF | 5 )
+#define PA6_PF_CSI_D2        ( GPIO_PORTA | GPIO_PF | 6 )
+#define PA7_PF_CSI_D3        ( GPIO_PORTA | GPIO_PF | 7 )
+#define PA8_PF_CSI_D4        ( GPIO_PORTA | GPIO_PF | 8 )
+#define PA9_PF_CSI_D5        ( GPIO_PORTA | GPIO_PF | 9 )
+#define PA10_PF_CSI_D6       ( GPIO_PORTA | GPIO_PF | 10 )
+#define PA11_PF_CSI_D7       ( GPIO_PORTA | GPIO_PF | 11 )
+#define PA12_PF_CSI_VSYNC    ( GPIO_PORTA | GPIO_PF | 12 )
+#define PA13_PF_CSI_HSYNC    ( GPIO_PORTA | GPIO_PF | 13 )
+#define PA14_PF_CSI_PIXCLK   ( GPIO_PORTA | GPIO_PF | 14 )
+#define PA15_PF_I2C_SDA      ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 )
+#define PA16_PF_I2C_SCL      ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 )
+#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 )
+#define PA17_AIN_SPI2_SS     ( GPIO_PORTA | GPIO_AIN | 17 )
+#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 )
+#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 )
+#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 )
+#define PA21_PF_A0           ( GPIO_PORTA | GPIO_PF | 21 )
+#define PA22_PF_CS4          ( GPIO_PORTA | GPIO_PF | 22 )
+#define PA23_PF_CS5          ( GPIO_PORTA | GPIO_PF | 23 )
+#define PA24_PF_A16          ( GPIO_PORTA | GPIO_PF | 24 )
+#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 )
+#define PA25_PF_A17          ( GPIO_PORTA | GPIO_PF | 25 )
+#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 )
+#define PA26_PF_A18          ( GPIO_PORTA | GPIO_PF | 26 )
+#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 )
+#define PA27_PF_A19          ( GPIO_PORTA | GPIO_PF | 27 )
+#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 )
+#define PA28_PF_A20          ( GPIO_PORTA | GPIO_PF | 28 )
+#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 )
+#define PA29_PF_A21          ( GPIO_PORTA | GPIO_PF | 29 )
+#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 )
+#define PA30_PF_A22          ( GPIO_PORTA | GPIO_PF | 30 )
+#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 )
+#define PA31_PF_A23          ( GPIO_PORTA | GPIO_PF | 31 )
+#define PA31_AF_ETMTRACECLK  ( GPIO_PORTA | GPIO_AF | 31 )
+#define PB8_PF_SD_DAT0       ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 )
+#define PB8_AF_MS_PIO        ( GPIO_PORTB | GPIO_AF | 8 )
+#define PB9_PF_SD_DAT1       ( GPIO_PORTB | GPIO_PF | GPIO_PUEN  | 9 )
+#define PB9_AF_MS_PI1        ( GPIO_PORTB | GPIO_AF | 9 )
+#define PB10_PF_SD_DAT2      ( GPIO_PORTB | GPIO_PF | GPIO_PUEN  | 10 )
+#define PB10_AF_MS_SCLKI     ( GPIO_PORTB | GPIO_AF | 10 )
+#define PB11_PF_SD_DAT3      ( GPIO_PORTB | GPIO_PF | GPIO_PUEN  | 11 )
+#define PB11_AF_MS_SDIO      ( GPIO_PORTB | GPIO_AF | 11 )
+#define PB12_PF_SD_CLK       ( GPIO_PORTB | GPIO_PF | GPIO_OUT | 12 )
+#define PB12_AF_MS_SCLK0     ( GPIO_PORTB | GPIO_AF | 12 )
+#define PB13_PF_SD_CMD       ( GPIO_PORTB | GPIO_PF | GPIO_OUT | GPIO_PUEN | 13 )
+#define PB13_AF_MS_BS        ( GPIO_PORTB | GPIO_AF | 13 )
+#define PB14_AF_SSI_RXFS     ( GPIO_PORTB | GPIO_AF | 14 )
+#define PB15_AF_SSI_RXCLK    ( GPIO_PORTB | GPIO_AF | 15 )
+#define PB16_AF_SSI_RXDAT    ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 )
+#define PB17_AF_SSI_TXDAT    ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 )
+#define PB18_AF_SSI_TXFS     ( GPIO_PORTB | GPIO_AF | 18 )
+#define PB19_AF_SSI_TXCLK    ( GPIO_PORTB | GPIO_AF | 19 )
+#define PB20_PF_USBD_AFE     ( GPIO_PORTB | GPIO_PF | 20 )
+#define PB21_PF_USBD_OE      ( GPIO_PORTB | GPIO_PF | 21 )
+#define PB22_PFUSBD_RCV      ( GPIO_PORTB | GPIO_PF | 22 )
+#define PB23_PF_USBD_SUSPND  ( GPIO_PORTB | GPIO_PF | 23 )
+#define PB24_PF_USBD_VP      ( GPIO_PORTB | GPIO_PF | 24 )
+#define PB25_PF_USBD_VM      ( GPIO_PORTB | GPIO_PF | 25 )
+#define PB26_PF_USBD_VPO     ( GPIO_PORTB | GPIO_PF | 26 )
+#define PB27_PF_USBD_VMO     ( GPIO_PORTB | GPIO_PF | 27 )
+#define PB28_PF_UART2_CTS    ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 )
+#define PB29_PF_UART2_RTS    ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 )
+#define PB30_PF_UART2_TXD    ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 )
+#define PB31_PF_UART2_RXD    ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 )
+#define PC3_PF_SSI_RXFS      ( GPIO_PORTC | GPIO_PF | 3 )
+#define PC4_PF_SSI_RXCLK     ( GPIO_PORTC | GPIO_PF | 4 )
+#define PC5_PF_SSI_RXDAT     ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 )
+#define PC6_PF_SSI_TXDAT     ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 )
+#define PC7_PF_SSI_TXFS      ( GPIO_PORTC | GPIO_PF | 7 )
+#define PC8_PF_SSI_TXCLK     ( GPIO_PORTC | GPIO_PF | 8 )
+#define PC9_PF_UART1_CTS     ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 )
+#define PC10_PF_UART1_RTS    ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 )
+#define PC11_PF_UART1_TXD    ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 )
+#define PC12_PF_UART1_RXD    ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 )
+#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 )
+#define PC14_PF_SPI1_SCLK    ( GPIO_PORTC | GPIO_PF | 14 )
+#define PC15_PF_SPI1_SS      ( GPIO_PORTC | GPIO_PF | 15 )
+#define PC16_PF_SPI1_MISO    ( GPIO_PORTC | GPIO_PF | 16 )
+#define PC17_PF_SPI1_MOSI    ( GPIO_PORTC | GPIO_PF | 17 )
+#define PD6_PF_LSCLK         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 )
+#define PD7_PF_REV           ( GPIO_PORTD | GPIO_PF | 7 )
+#define PD7_AF_UART2_DTR     ( GPIO_PORTD | GPIO_IN | GPIO_AF | 7 )
+#define PD7_AIN_SPI2_SCLK    ( GPIO_PORTD | GPIO_AIN | 7 )
+#define PD8_PF_CLS           ( GPIO_PORTD | GPIO_PF | 8 )
+#define PD8_AF_UART2_DCD     ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 )
+#define PD8_AIN_SPI2_SS      ( GPIO_PORTD | GPIO_AIN | 8 )
+#define PD9_PF_PS            ( GPIO_PORTD | GPIO_PF | 9 )
+#define PD9_AF_UART2_RI      ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 )
+#define PD9_AOUT_SPI2_RXD    ( GPIO_PORTD | GPIO_IN | GPIO_AOUT | 9 )
+#define PD10_PF_SPL_SPR      ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 )
+#define PD10_AF_UART2_DSR    ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 )
+#define PD10_AIN_SPI2_TXD    ( GPIO_PORTD | GPIO_OUT | GPIO_AIN | 10 )
+#define PD11_PF_CONTRAST     ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 )
+#define PD12_PF_ACD_OE       ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 )
+#define PD13_PF_LP_HSYNC     ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 )
+#define PD14_PF_FLM_VSYNC    ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 )
+#define PD15_PF_LD0          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 )
+#define PD16_PF_LD1          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 )
+#define PD17_PF_LD2          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 )
+#define PD18_PF_LD3          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 )
+#define PD19_PF_LD4          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 )
+#define PD20_PF_LD5          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 )
+#define PD21_PF_LD6          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 )
+#define PD22_PF_LD7          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 )
+#define PD23_PF_LD8          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 )
+#define PD24_PF_LD9          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 )
+#define PD25_PF_LD10         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 )
+#define PD26_PF_LD11         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 )
+#define PD27_PF_LD12         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 )
+#define PD28_PF_LD13         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 )
+#define PD29_PF_LD14         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 )
+#define PD30_PF_LD15         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 )
+#define PD31_PF_TMR2OUT      ( GPIO_PORTD | GPIO_PF | 31 )
+#define PD31_BIN_SPI2_TXD    ( GPIO_PORTD | GPIO_BIN | 31 )
+
+/*
+ *  DMA Controller
+ */
+#define DCR     __REG(IMX_DMAC_BASE +0x00)	/* DMA Control Register */
+#define DISR    __REG(IMX_DMAC_BASE +0x04)	/* DMA Interrupt status Register */
+#define DIMR    __REG(IMX_DMAC_BASE +0x08)	/* DMA Interrupt mask Register */
+#define DBTOSR  __REG(IMX_DMAC_BASE +0x0c)	/* DMA Burst timeout status Register */
+#define DRTOSR  __REG(IMX_DMAC_BASE +0x10)	/* DMA Request timeout Register */
+#define DSESR   __REG(IMX_DMAC_BASE +0x14)	/* DMA Transfer Error Status Register */
+#define DBOSR   __REG(IMX_DMAC_BASE +0x18)	/* DMA Buffer overflow status Register */
+#define DBTOCR  __REG(IMX_DMAC_BASE +0x1c)	/* DMA Burst timeout control Register */
+#define WSRA    __REG(IMX_DMAC_BASE +0x40)	/* W-Size Register A */
+#define XSRA    __REG(IMX_DMAC_BASE +0x44)	/* X-Size Register A */
+#define YSRA    __REG(IMX_DMAC_BASE +0x48)	/* Y-Size Register A */
+#define WSRB    __REG(IMX_DMAC_BASE +0x4c)	/* W-Size Register B */
+#define XSRB    __REG(IMX_DMAC_BASE +0x50)	/* X-Size Register B */
+#define YSRB    __REG(IMX_DMAC_BASE +0x54)	/* Y-Size Register B */
+#define SAR(x)  __REG2( IMX_DMAC_BASE + 0x80, (x) << 6)	/* Source Address Registers */
+#define DAR(x)  __REG2( IMX_DMAC_BASE + 0x84, (x) << 6)	/* Destination Address Registers */
+#define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6)	/* Count Registers */
+#define CCR(x)  __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6)	/* Control Registers */
+#define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6)	/* Request source select Registers */
+#define BLR(x)  __REG2( IMX_DMAC_BASE + 0x94, (x) << 6)	/* Burst length Registers */
+#define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6)	/* Request timeout Registers */
+#define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6)	/* Bus Utilization Registers */
+
+/* TODO: define DMA_REQ lines */
+
+#define DCR_DRST           (1<<1)
+#define DCR_DEN            (1<<0)
+#define DBTOCR_EN          (1<<15)
+#define DBTOCR_CNT(x)      ((x) & 0x7fff )
+#define CNTR_CNT(x)        ((x) & 0xffffff )
+#define CCR_DMOD_LINEAR    ( 0x0 << 12 )
+#define CCR_DMOD_2D        ( 0x1 << 12 )
+#define CCR_DMOD_FIFO      ( 0x2 << 12 )
+#define CCR_DMOD_EOBFIFO   ( 0x3 << 12 )
+#define CCR_SMOD_LINEAR    ( 0x0 << 10 )
+#define CCR_SMOD_2D        ( 0x1 << 10 )
+#define CCR_SMOD_FIFO      ( 0x2 << 10 )
+#define CCR_SMOD_EOBFIFO   ( 0x3 << 10 )
+#define CCR_MDIR_DEC       (1<<9)
+#define CCR_MSEL_B         (1<<8)
+#define CCR_DSIZ_32        ( 0x0 << 6 )
+#define CCR_DSIZ_8         ( 0x1 << 6 )
+#define CCR_DSIZ_16        ( 0x2 << 6 )
+#define CCR_SSIZ_32        ( 0x0 << 4 )
+#define CCR_SSIZ_8         ( 0x1 << 4 )
+#define CCR_SSIZ_16        ( 0x2 << 4 )
+#define CCR_REN            (1<<3)
+#define CCR_RPT            (1<<2)
+#define CCR_FRC            (1<<1)
+#define CCR_CEN            (1<<0)
+#define RTOR_EN            (1<<15)
+#define RTOR_CLK           (1<<14)
+#define RTOR_PSC           (1<<13)
+
+/*
+ * LCD Controller
+ */
+
+#define LCDC_SSA	__REG(IMX_LCDC_BASE+0x00)
+
+#define LCDC_SIZE	__REG(IMX_LCDC_BASE+0x04)
+#define SIZE_XMAX(x)	((((x) >> 4) & 0x3f) << 20)
+#define SIZE_YMAX(y)    ( (y) & 0x1ff )
+
+#define LCDC_VPW	__REG(IMX_LCDC_BASE+0x08)
+#define VPW_VPW(x)	( (x) & 0x3ff )
+
+#define LCDC_CPOS	__REG(IMX_LCDC_BASE+0x0C)
+#define CPOS_CC1        (1<<31)
+#define CPOS_CC0        (1<<30)
+#define CPOS_OP         (1<<28)
+#define CPOS_CXP(x)     (((x) & 3ff) << 16)
+#define CPOS_CYP(y)     ((y) & 0x1ff)
+
+#define LCDC_LCWHB	__REG(IMX_LCDC_BASE+0x10)
+#define LCWHB_BK_EN     (1<<31)
+#define LCWHB_CW(w)     (((w) & 0x1f) << 24)
+#define LCWHB_CH(h)     (((h) & 0x1f) << 16)
+#define LCWHB_BD(x)     ((x) & 0xff)
+
+#define LCDC_LCHCC	__REG(IMX_LCDC_BASE+0x14)
+#define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11)
+#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5)
+#define LCHCC_CUR_COL_B(b) ((b) & 0x1f)
+
+#define LCDC_PCR	__REG(IMX_LCDC_BASE+0x18)
+#define PCR_TFT         (1<<31)
+#define PCR_COLOR       (1<<30)
+#define PCR_PBSIZ_1     (0<<28)
+#define PCR_PBSIZ_2     (1<<28)
+#define PCR_PBSIZ_4     (2<<28)
+#define PCR_PBSIZ_8     (3<<28)
+#define PCR_BPIX_1      (0<<25)
+#define PCR_BPIX_2      (1<<25)
+#define PCR_BPIX_4      (2<<25)
+#define PCR_BPIX_8      (3<<25)
+#define PCR_BPIX_12     (4<<25)
+#define PCR_BPIX_16     (4<<25)
+#define PCR_PIXPOL      (1<<24)
+#define PCR_FLMPOL      (1<<23)
+#define PCR_LPPOL       (1<<22)
+#define PCR_CLKPOL      (1<<21)
+#define PCR_OEPOL       (1<<20)
+#define PCR_SCLKIDLE    (1<<19)
+#define PCR_END_SEL     (1<<18)
+#define PCR_END_BYTE_SWAP (1<<17)
+#define PCR_REV_VS      (1<<16)
+#define PCR_ACD_SEL     (1<<15)
+#define PCR_ACD(x)      (((x) & 0x7f) << 8)
+#define PCR_SCLK_SEL    (1<<7)
+#define PCR_SHARP       (1<<6)
+#define PCR_PCD(x)      ((x) & 0x3f)
+
+#define LCDC_HCR	__REG(IMX_LCDC_BASE+0x1C)
+#define HCR_H_WIDTH(x)  (((x) & 0x3f) << 26)
+#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8)
+#define HCR_H_WAIT_2(x) ((x) & 0xff)
+
+#define LCDC_VCR	__REG(IMX_LCDC_BASE+0x20)
+#define VCR_V_WIDTH(x)  (((x) & 0x3f) << 26)
+#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8)
+#define VCR_V_WAIT_2(x) ((x) & 0xff)
+
+#define LCDC_POS	__REG(IMX_LCDC_BASE+0x24)
+#define POS_POS(x)      ((x) & 1f)
+
+#define LCDC_LSCR1	__REG(IMX_LCDC_BASE+0x28)
+#define LSCR1_GRAY1(x)  (((x) & 0xf) << 4)
+#define LSCR1_GRAY2(x)  ((x) & 0xf)
+
+#define LCDC_PWMR	__REG(IMX_LCDC_BASE+0x2C)
+#define PWMR_CLS(x)     (((x) & 0x1ff) << 16)
+#define PWMR_LDMSK      (1<<15)
+#define PWMR_SCR1       (1<<10)
+#define PWMR_SCR0       (1<<9)
+#define PWMR_CC_EN      (1<<8)
+#define PWMR_PW(x)      ((x) & 0xff)
+
+#define LCDC_DMACR	__REG(IMX_LCDC_BASE+0x30)
+#define DMACR_BURST     (1<<31)
+#define DMACR_HM(x)     (((x) & 0xf) << 16)
+#define DMACR_TM(x)     ((x) &0xf)
+
+#define LCDC_RMCR	__REG(IMX_LCDC_BASE+0x34)
+#define RMCR_LCDC_EN		(1<<1)
+#define RMCR_SELF_REF		(1<<0)
+
+#define LCDC_LCDICR	__REG(IMX_LCDC_BASE+0x38)
+#define LCDICR_INT_SYN  (1<<2)
+#define LCDICR_INT_CON  (1)
+
+#define LCDC_LCDISR	__REG(IMX_LCDC_BASE+0x40)
+#define LCDISR_UDR_ERR (1<<3)
+#define LCDISR_ERR_RES (1<<2)
+#define LCDISR_EOF     (1<<1)
+#define LCDISR_BOF     (1<<0)
+/*
+ *  UART Module
+ */
+#define URXD0(x) __REG2( IMX_UART1_BASE + 0x0, ((x) & 1) << 12)	/* Receiver Register */
+#define URTX0(x) __REG2( IMX_UART1_BASE + 0x40, ((x) & 1) << 12)	/* Transmitter Register */
+#define UCR1(x)  __REG2( IMX_UART1_BASE + 0x80, ((x) & 1) << 12)	/* Control Register 1 */
+#define UCR2(x)  __REG2( IMX_UART1_BASE + 0x84, ((x) & 1) << 12)	/* Control Register 2 */
+#define UCR3(x)  __REG2( IMX_UART1_BASE + 0x88, ((x) & 1) << 12)	/* Control Register 3 */
+#define UCR4(x)  __REG2( IMX_UART1_BASE + 0x8c, ((x) & 1) << 12)	/* Control Register 4 */
+#define UFCR(x)  __REG2( IMX_UART1_BASE + 0x90, ((x) & 1) << 12)	/* FIFO Control Register */
+#define USR1(x)  __REG2( IMX_UART1_BASE + 0x94, ((x) & 1) << 12)	/* Status Register 1 */
+#define USR2(x)  __REG2( IMX_UART1_BASE + 0x98, ((x) & 1) << 12)	/* Status Register 2 */
+#define UESC(x)  __REG2( IMX_UART1_BASE + 0x9c, ((x) & 1) << 12)	/* Escape Character Register */
+#define UTIM(x)  __REG2( IMX_UART1_BASE + 0xa0, ((x) & 1) << 12)	/* Escape Timer Register */
+#define UBIR(x)  __REG2( IMX_UART1_BASE + 0xa4, ((x) & 1) << 12)	/* BRM Incremental Register */
+#define UBMR(x)  __REG2( IMX_UART1_BASE + 0xa8, ((x) & 1) << 12)	/* BRM Modulator Register */
+#define UBRC(x)  __REG2( IMX_UART1_BASE + 0xac, ((x) & 1) << 12)	/* Baud Rate Count Register */
+#define BIPR1(x) __REG2( IMX_UART1_BASE + 0xb0, ((x) & 1) << 12)	/* Incremental Preset Register 1 */
+#define BIPR2(x) __REG2( IMX_UART1_BASE + 0xb4, ((x) & 1) << 12)	/* Incremental Preset Register 2 */
+#define BIPR3(x) __REG2( IMX_UART1_BASE + 0xb8, ((x) & 1) << 12)	/* Incremental Preset Register 3 */
+#define BIPR4(x) __REG2( IMX_UART1_BASE + 0xbc, ((x) & 1) << 12)	/* Incremental Preset Register 4 */
+#define BMPR1(x) __REG2( IMX_UART1_BASE + 0xc0, ((x) & 1) << 12)	/* BRM Modulator Register 1 */
+#define BMPR2(x) __REG2( IMX_UART1_BASE + 0xc4, ((x) & 1) << 12)	/* BRM Modulator Register 2 */
+#define BMPR3(x) __REG2( IMX_UART1_BASE + 0xc8, ((x) & 1) << 12)	/* BRM Modulator Register 3 */
+#define BMPR4(x) __REG2( IMX_UART1_BASE + 0xcc, ((x) & 1) << 12)	/* BRM Modulator Register 4 */
+#define UTS(x)   __REG2( IMX_UART1_BASE + 0xd0, ((x) & 1) << 12)	/* UART Test Register */
+
+/* UART Control Register Bit Fields.*/
+#define  URXD_CHARRDY    (1<<15)
+#define  URXD_ERR        (1<<14)
+#define  URXD_OVRRUN     (1<<13)
+#define  URXD_FRMERR     (1<<12)
+#define  URXD_BRK        (1<<11)
+#define  URXD_PRERR      (1<<10)
+#define  UCR1_ADEN       (1<<15) /* Auto dectect interrupt */
+#define  UCR1_ADBR       (1<<14) /* Auto detect baud rate */
+#define  UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */
+#define  UCR1_IDEN       (1<<12) /* Idle condition interrupt */
+#define  UCR1_RRDYEN     (1<<9)	 /* Recv ready interrupt enable */
+#define  UCR1_RDMAEN     (1<<8)	 /* Recv ready DMA enable */
+#define  UCR1_IREN       (1<<7)	 /* Infrared interface enable */
+#define  UCR1_TXMPTYEN   (1<<6)	 /* Transimitter empty interrupt enable */
+#define  UCR1_RTSDEN     (1<<5)	 /* RTS delta interrupt enable */
+#define  UCR1_SNDBRK     (1<<4)	 /* Send break */
+#define  UCR1_TDMAEN     (1<<3)	 /* Transmitter ready DMA enable */
+#define  UCR1_UARTCLKEN  (1<<2)	 /* UART clock enabled */
+#define  UCR1_DOZE       (1<<1)	 /* Doze */
+#define  UCR1_UARTEN     (1<<0)	 /* UART enabled */
+#define  UCR2_ESCI     	 (1<<15) /* Escape seq interrupt enable */
+#define  UCR2_IRTS  	 (1<<14) /* Ignore RTS pin */
+#define  UCR2_CTSC  	 (1<<13) /* CTS pin control */
+#define  UCR2_CTS        (1<<12) /* Clear to send */
+#define  UCR2_ESCEN      (1<<11) /* Escape enable */
+#define  UCR2_PREN       (1<<8) /* Parity enable */
+#define  UCR2_PROE       (1<<7) /* Parity odd/even */
+#define  UCR2_STPB       (1<<6)	/* Stop */
+#define  UCR2_WS         (1<<5)	/* Word size */
+#define  UCR2_RTSEN      (1<<4)	/* Request to send interrupt enable */
+#define  UCR2_TXEN       (1<<2)	/* Transmitter enabled */
+#define  UCR2_RXEN       (1<<1)	/* Receiver enabled */
+#define  UCR2_SRST 	 (1<<0)	/* SW reset */
+#define  UCR3_DTREN 	 (1<<13) /* DTR interrupt enable */
+#define  UCR3_PARERREN   (1<<12) /* Parity enable */
+#define  UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
+#define  UCR3_DSR        (1<<10) /* Data set ready */
+#define  UCR3_DCD        (1<<9)  /* Data carrier detect */
+#define  UCR3_RI         (1<<8)  /* Ring indicator */
+#define  UCR3_TIMEOUTEN  (1<<7)  /* Timeout interrupt enable */
+#define  UCR3_RXDSEN	 (1<<6)  /* Receive status interrupt enable */
+#define  UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
+#define  UCR3_AWAKEN	 (1<<4)  /* Async wake interrupt enable */
+#define  UCR3_REF25 	 (1<<3)  /* Ref freq 25 MHz */
+#define  UCR3_REF30 	 (1<<2)  /* Ref Freq 30 MHz */
+#define  UCR3_INVT  	 (1<<1)  /* Inverted Infrared transmission */
+#define  UCR3_BPEN  	 (1<<0)  /* Preset registers enable */
+#define  UCR4_CTSTL_32   (32<<10) /* CTS trigger level (32 chars) */
+#define  UCR4_INVR  	 (1<<9)  /* Inverted infrared reception */
+#define  UCR4_ENIRI 	 (1<<8)  /* Serial infrared interrupt enable */
+#define  UCR4_WKEN  	 (1<<7)  /* Wake interrupt enable */
+#define  UCR4_REF16 	 (1<<6)  /* Ref freq 16 MHz */
+#define  UCR4_IRSC  	 (1<<5) /* IR special case */
+#define  UCR4_TCEN  	 (1<<3) /* Transmit complete interrupt enable */
+#define  UCR4_BKEN  	 (1<<2) /* Break condition interrupt enable */
+#define  UCR4_OREN  	 (1<<1) /* Receiver overrun interrupt enable */
+#define  UCR4_DREN  	 (1<<0) /* Recv data ready interrupt enable */
+#define  UFCR_RXTL_SHF   0      /* Receiver trigger level shift */
+#define  UFCR_RFDIV      (7<<7) /* Reference freq divider mask */
+#define  UFCR_TXTL_SHF   10     /* Transmitter trigger level shift */
+#define  USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
+#define  USR1_RTSS  	 (1<<14) /* RTS pin status */
+#define  USR1_TRDY  	 (1<<13) /* Transmitter ready interrupt/dma flag */
+#define  USR1_RTSD  	 (1<<12) /* RTS delta */
+#define  USR1_ESCF  	 (1<<11) /* Escape seq interrupt flag */
+#define  USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
+#define  USR1_RRDY       (1<<9)	/* Receiver ready interrupt/dma flag */
+#define  USR1_TIMEOUT    (1<<7)	/* Receive timeout interrupt status */
+#define  USR1_RXDS  	 (1<<6)	/* Receiver idle interrupt flag */
+#define  USR1_AIRINT	 (1<<5)	/* Async IR wake interrupt flag */
+#define  USR1_AWAKE 	 (1<<4)	/* Aysnc wake interrupt flag */
+#define  USR2_ADET  	 (1<<15) /* Auto baud rate detect complete */
+#define  USR2_TXFE  	 (1<<14) /* Transmit buffer FIFO empty */
+#define  USR2_DTRF  	 (1<<13) /* DTR edge interrupt flag */
+#define  USR2_IDLE  	 (1<<12) /* Idle condition */
+#define  USR2_IRINT 	 (1<<8)	/* Serial infrared interrupt flag */
+#define  USR2_WAKE  	 (1<<7)	/* Wake */
+#define  USR2_RTSF  	 (1<<4)	/* RTS edge interrupt flag */
+#define  USR2_TXDC  	 (1<<3)	/* Transmitter complete */
+#define  USR2_BRCD  	 (1<<2)	/* Break condition */
+#define  USR2_ORE        (1<<1)	/* Overrun error */
+#define  USR2_RDR        (1<<0)	/* Recv data ready */
+#define  UTS_FRCPERR	 (1<<13) /* Force parity error */
+#define  UTS_LOOP        (1<<12) /* Loop tx and rx */
+#define  UTS_TXEMPTY	 (1<<6)	/* TxFIFO empty */
+#define  UTS_RXEMPTY	 (1<<5)	/* RxFIFO empty */
+#define  UTS_TXFULL 	 (1<<4)	/* TxFIFO full */
+#define  UTS_RXFULL 	 (1<<3)	/* RxFIFO full */
+#define  UTS_SOFTRST	 (1<<0)	/* Software reset */
+
+/* General purpose timers registers */
+#define TCTL1   __REG(IMX_TIM1_BASE)
+#define TPRER1  __REG(IMX_TIM1_BASE + 0x4)
+#define TCMP1   __REG(IMX_TIM1_BASE + 0x8)
+#define TCR1    __REG(IMX_TIM1_BASE + 0xc)
+#define TCN1    __REG(IMX_TIM1_BASE + 0x10)
+#define TSTAT1  __REG(IMX_TIM1_BASE + 0x14)
+#define TCTL2   __REG(IMX_TIM2_BASE)
+#define TPRER2  __REG(IMX_TIM2_BASE + 0x4)
+#define TCMP2   __REG(IMX_TIM2_BASE + 0x8)
+#define TCR2    __REG(IMX_TIM2_BASE + 0xc)
+#define TCN2    __REG(IMX_TIM2_BASE + 0x10)
+#define TSTAT2  __REG(IMX_TIM2_BASE + 0x14)
+
+/* General purpose timers bitfields */
+#define TCTL_SWR       (1<<15) /* Software reset */
+#define TCTL_FRR       (1<<8)  /* Freerun / restart */
+#define TCTL_CAP       (3<<6)  /* Capture Edge */
+#define TCTL_OM        (1<<5)  /* output mode */
+#define TCTL_IRQEN     (1<<4)  /* interrupt enable */
+#define TCTL_CLKSOURCE (7<<1)  /* Clock source */
+#define TCTL_TEN       (1)     /* Timer enable */
+#define TPRER_PRES     (0xff)  /* Prescale */
+#define TSTAT_CAPT     (1<<1)  /* Capture event */
+#define TSTAT_COMP     (1)     /* Compare event */
+
+#endif				/* _IMX_REGS_H */
diff --git a/include/common.h b/include/common.h
index 02efba3c7af..48e38b965dd 100644
--- a/include/common.h
+++ b/include/common.h
@@ -126,6 +126,17 @@ typedef void (interrupt_handler_t)(void *);
 # endif
 #endif
 
+#ifndef CONFIG_SERIAL_MULTI
+
+#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2) \
+ || defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) \
+ || defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
+
+#define CONFIG_SERIAL_MULTI	1
+
+#endif
+
+#endif /* CONFIG_SERIAL_MULTI */
 
 /*
  * General Purpose Utilities
@@ -403,6 +414,15 @@ ulong	get_PLLCLK (void);
 #if defined CONFIG_INCA_IP
 uint	incaip_get_cpuclk (void);
 #endif
+#if defined(CONFIG_IMX)
+ulong get_systemPLLCLK(void);
+ulong get_FCLK(void);
+ulong get_HCLK(void);
+ulong get_BCLK(void);
+ulong get_PERCLK1(void);
+ulong get_PERCLK2(void);
+ulong get_PERCLK3(void);
+#endif
 ulong	get_bus_freq  (ulong);
 
 #if defined(CONFIG_MPC85xx)
diff --git a/include/commproc.h b/include/commproc.h
index f87620ebf13..83119717a9c 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -74,9 +74,10 @@
 #define CPM_I2C_BASE		0x0820
 #define CPM_SPI_BASE		0x0840
 #define CPM_FEC_BASE		0x0860
-#define CPM_WLKBD_BASE		0x0880
+#define CPM_SERIAL2_BASE	0x0880
 #define CPM_SCC_BASE		0x0900
 #define CPM_POST_BASE		0x0980
+#define CPM_WLKBD_BASE		0x0a00
 
 #endif
 
@@ -1041,7 +1042,7 @@ typedef struct scc_enet {
 
 /***  LWMON  **********************************************************/
 
-#if defined(CONFIG_LWMON) && !defined(CONFIG_8xx_CONS_SCC2)
+#if defined(CONFIG_LWMON)
 /* Bits in parallel I/O port registers that have to be set/cleared
  * to configure the pins for SCC2 use.
  */
diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h
index bb8ce43babf..b1f41a17279 100644
--- a/include/configs/PPChameleonEVB.h
+++ b/include/configs/PPChameleonEVB.h
@@ -43,6 +43,9 @@
  * CONFIG_PPCHAMELEON_CLK_25
  * CONFIG_PPCHAMELEON_CLK_33
  */
+#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
+#define CONFIG_PPCHAMELEON_CLK_33
+#endif
 
 #if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
 #error "* Two external frequencies (SysClk) are defined! *"
@@ -74,11 +77,11 @@
 
 
 #ifdef CONFIG_PPCHAMELEON_CLK_25
-	#define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/
+# define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/
 #elif (defined (CONFIG_PPCHAMELEON_CLK_33))
-#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/
+# define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/
 #else
-#error "* External frequency (SysClk) not defined! *"
+# error "* External frequency (SysClk) not defined! *"
 #endif
 
 #define CONFIG_BAUDRATE		115200
diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h
index 830bf81a451..47f24be5206 100644
--- a/include/configs/Total5200.h
+++ b/include/configs/Total5200.h
@@ -64,6 +64,7 @@
  * Video console
  */
 #if 1
+#define CONFIG_VIDEO
 #define CONFIG_VIDEO_SED13806
 #define CONFIG_VIDEO_SED13806_16BPP
 
diff --git a/include/configs/lwmon.h b/include/configs/lwmon.h
index d944ed88cdd..a76ec23652b 100644
--- a/include/configs/lwmon.h
+++ b/include/configs/lwmon.h
@@ -47,11 +47,9 @@
 
 #define	CONFIG_SPLASH_SCREEN		/* ... with splashscreen support*/
 
-#if 1
+#define CONFIG_SERIAL_MULTI	1
 #define CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
-#else
-#define CONFIG_8xx_CONS_SCC2
-#endif
+#define CONFIG_8xx_CONS_SCC2	1	/* Console is on SCC2		*/
 
 #define CONFIG_BAUDRATE		115200	/* with watchdog >= 38400 needed */
 
@@ -151,17 +149,6 @@
 #define CFG_CMD_POST_DIAG 0
 #endif
 
-#ifdef CONFIG_8xx_CONS_SCC2	/* Can't use ethernet, then */
-#define CONFIG_COMMANDS	     ( (CONFIG_CMD_DFL & ~CFG_CMD_NET) | \
-				CFG_CMD_ASKENV	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_EEPROM	| \
-				CFG_CMD_IDE	| \
-				CFG_CMD_BSP	| \
-				CFG_CMD_BMP	| \
-				CFG_CMD_POST_DIAG )
-#else
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_ASKENV	| \
 				CFG_CMD_DHCP	| \
@@ -172,7 +159,6 @@
 				CFG_CMD_BSP	| \
 				CFG_CMD_BMP	| \
 				CFG_CMD_POST_DIAG )
-#endif
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 
diff --git a/include/configs/mx1ads.h b/include/configs/mx1ads.h
index 5cf092af550..df951e2d745 100644
--- a/include/configs/mx1ads.h
+++ b/include/configs/mx1ads.h
@@ -16,7 +16,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -25,7 +25,6 @@
  * MA 02111-1307 USA
  */
 
-
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
@@ -40,14 +39,19 @@
  * (easy to change)
  */
 #define CONFIG_ARM920T		1	/* This is an ARM920T Core		*/
-#define	CONFIG_MC9328		1	/* It's a Motorola MC9328 SoC 		*/
-#define CONFIG_MX1ADS		1	/* on a Motorola MX1ADS Board  		*/
-
-#define BOARD_LATE_INIT		1
+#define CONFIG_IMX		1	/* It's a Motorola MC9328 SoC		*/
+#define CONFIG_MX1ADS		1	/* on a Motorola MX1ADS Board		*/
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff		*/
 
+/*
+ * Select serial console configuration
+  */
+#define CONFIG_IMX_SERIAL1		/* internal uart 1 */
+/* #define _CONFIG_UART2 */		/* internal uart 2 */
+/* #define CONFIG_SILENT_CONSOLE */	/* use this to disable output */
 
+#define BOARD_LATE_INIT		1
 #define USE_920T_MMU		1
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff 		*/
 
 #if 0
 #define CFG_MX1_GPCR		0x000003AB	/* for MX1ADS 0L44N		*/
@@ -60,6 +64,8 @@
  */
 
 #define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+
+
 #define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
@@ -67,13 +73,13 @@
  */
 #define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */
 #define CS8900_BASE		0x15000300
-#define CS8900_BUS16		1 	/* the Linux driver does accesses as shorts */
+#define CS8900_BUS16		1	/* the Linux driver does accesses as shorts */
 
 /*
  * select serial console configuration
  */
 
-#define CONFIG_UART1 		1
+/* #define CONFIG_UART1			*/
 /* #define CONFIG_UART2		1	*/
 
 #define CONFIG_BAUDRATE		115200
@@ -85,24 +91,20 @@
 #define CONFIG_COMMANDS \
 			(CONFIG_CMD_DFL	 | \
 			CFG_CMD_CACHE	 | \
-			/*CFG_CMD_NAND	 |*/ \
-			/*CFG_CMD_EEPROM |*/ \
-			/*CFG_CMD_I2C	 |*/ \
-			/*CFG_CMD_USB	 |*/ \
-			CFG_CMD_REGINFO  | \
+			CFG_CMD_REGINFO	 | \
 			CFG_CMD_ELF)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
 #define CONFIG_BOOTDELAY	3
-#define CONFIG_BOOTARGS    	"root=/dev/docbp mem=48M"
+#define CONFIG_BOOTARGS		"root=/dev/msdk mem=48M"
 #define CONFIG_ETHADDR		08:00:3e:26:0a:5c
-#define CONFIG_NETMASK          255.255.255.0
+#define CONFIG_NETMASK		255.255.255.0
 #define CONFIG_IPADDR		192.168.0.22
 #define CONFIG_SERVERIP		192.168.0.11
 #define CONFIG_BOOTFILE		"mx1ads"
-/*#define CONFIG_BOOTCOMMAND	"tftp; bootm" */
+#define CONFIG_BOOTCOMMAND	"tftp; bootm"
 
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
@@ -114,10 +116,10 @@
  * Miscellaneous configurable options
  */
 
-#define CFG_HUSH_PARSER         1
+#define CFG_HUSH_PARSER		1
 #define CFG_PROMPT_HUSH_PS2	"> "
 
-#define	CFG_LONGHELP				/* undef to save memory		*/
+#define CFG_LONGHELP				/* undef to save memory		*/
 
 #ifdef CFG_HUSH_PARSER
 #define CFG_PROMPT		"MX1ADS$ "	/* Monitor Command Prompt */
@@ -125,21 +127,20 @@
 #define CFG_PROMPT		"MX1ADS=> "	/* Monitor Command Prompt */
 #endif
 
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CFG_PBSIZE 		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
 						/* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_MAXARGS		16		/* max number of command args	*/
 #define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
 #define CFG_MEMTEST_START	0x09000000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0AF00000	/* 63 MB in DRAM	*/
 
-#undef  CFG_CLKS_IN_HZ				/* everything, incl board info, in Hz */
-
-#define	CFG_LOAD_ADDR		0x08800000	/* default load address	*/
-
-
-#define	CFG_HZ			1000
+#undef	CFG_CLKS_IN_HZ				/* everything, incl board info, in Hz */
+#define CFG_LOAD_ADDR		0x08800000	/* default load address */
+/*#define	CFG_HZ			1000 */
+#define CFG_HZ			3686400
+#define CFG_CPUSPEED		0x141
 
 /* valid baudrates */
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
@@ -159,27 +160,35 @@
  * Physical Memory Map
  */
 
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of SDRAM	*/
+#define PHYS_SDRAM_1		0x08000000	/* SDRAM  on CSD0		*/
+#define PHYS_SDRAM_1_SIZE	0x04000000	/* 64 MB			*/
 
-#define CONFIG_NR_DRAM_BANKS	1	   	/* we have 1 bank of SDRAM 	*/
-#define PHYS_SDRAM_1		0x08000000 	/* SDRAM  on CSD0 		*/
-#define PHYS_SDRAM_1_SIZE	0x04000000 	/* 64 MB 			*/
-
-#define CFG_MAX_FLASH_BANKS	1		/* 1 bank of SyncFlash 		*/
-#define CFG_FLASH_BASE		0x0C000000 	/* SyncFlash on CSD1 		*/
-#define FLASH_BANK_SIZE		0x01000000	/* 16 MB Total 		 	*/
-
+#define CFG_MAX_FLASH_BANKS	1		/* 1 bank of SyncFlash		*/
+#define CFG_FLASH_BASE		0x0C000000	/* SyncFlash on CSD1		*/
+#define FLASH_BANK_SIZE		0x01000000	/* 16 MB Total			*/
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
 
-
 #define CONFIG_SYNCFLASH	1
 #define PHYS_FLASH_SIZE		0x01000000
 #define CFG_MAX_FLASH_SECT	(16)
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE+0x00ff0000)
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE+0x00ff8000)
 
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_SIZE		0x0f000	/* Total Size of Environment Sector */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE		0x04000 /* Total Size of Environment Sector */
 #define CFG_ENV_SECT_SIZE	0x100000
+
+/*-----------------------------------------------------------------------
+ * Enable passing ATAGS
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+
+#define CONFIG_SYS_CLK_FREQ 16780000
+#define CONFIG_SYSPLL_CLK_FREQ 16000000
+
 #endif	/* __CONFIG_H */
diff --git a/include/configs/mx1fs2.h b/include/configs/mx1fs2.h
new file mode 100644
index 00000000000..61a3b29612e
--- /dev/null
+++ b/include/configs/mx1fs2.h
@@ -0,0 +1,291 @@
+/*
+ * Copyright (C) 2004 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_ARM920T	   1	 /* this is an ARM920T CPU     */
+#define CONFIG_IMX	   1	 /* in a Motorola MC9328MXL Chip */
+#define CONFIG_MX1FS2	   1	 /* on a mx1fs2 board */
+#undef	CONFIG_USE_IRQ		 /* don't need use IRQ/FIQ    */
+
+/*
+ * Select serial console configuration
+ */
+#undef	_CONFIG_UART1 /* internal uart 1 */
+#define _CONFIG_UART2 /* internal uart 2 */
+#undef	_CONFIG_UART3 /* internal uart 3 */
+#undef	_CONFIG_UART4 /* internal uart 4 */
+#undef	CONFIG_SILENT_CONSOLE  /* use this to disable output */
+
+/*
+ * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if
+ * neccessary in include/cmd_confdefs.h file. (Un)comment for getting
+ * functionality or size of u-boot code.
+ */
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL		 \
+				& ~CFG_CMD_LOADS	 \
+				& ~CFG_CMD_CONSOLE	 \
+				& ~CFG_CMD_AUTOSCRIPT	 \
+				& ~CFG_CMD_NET		 \
+				& ~CFG_CMD_PING		 \
+				& ~CFG_CMD_DHCP		 \
+				| CFG_CMD_JFFS2		 \
+				)
+
+#include <cmd_confdefs.h>
+
+/*
+ * Boot options. Setting delay to -1 stops autostart count down.
+ */
+#define CONFIG_BOOTDELAY   10
+#define CONFIG_BOOTARGS	   "root=/dev/mtdblock4 console=ttySMX0,115200n8 rootfstype=jffs2"
+#define CONFIG_BOOTCOMMAND "bootm 10080000"
+#define CONFIG_SHOW_BOOT_PROGRESS
+
+/*
+ * General options for u-boot. Modify to save memory foot print
+ */
+#define CFG_LONGHELP				      /* undef saves memory  */
+#define CFG_PROMPT		"mx1fs2> "	      /* prompt string	     */
+#define CFG_CBSIZE		256		      /* console I/O buffer  */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size   */
+#define CFG_MAXARGS		16		      /* max command args    */
+#define CFG_BARGSIZE		CFG_CBSIZE	      /* boot args buf size  */
+
+#define CFG_MEMTEST_START	0x08100000	      /* memtest test area   */
+#define CFG_MEMTEST_END		0x08F00000
+
+#undef	CFG_CLKS_IN_HZ			     /* use HZ for freq. display     */
+
+#define CFG_HZ			3686400	     /* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED		0x141	     /* core clock - register value  */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_BAUDRATE 115200
+/*
+ * Definitions related to passing arguments to kernel.
+ */
+#define CONFIG_CMDLINE_TAG	     1	 /* send commandline to Kernel	     */
+#define CONFIG_SETUP_MEMORY_TAGS     1	 /* send memory definition to kernel */
+#define	 CONFIG_INITRD_TAG	     1	   /* send initrd params	*/
+#undef	CONFIG_VFD			 /* do not send framebuffer setup    */
+
+#define CFG_JFFS_CUSTOM_PART
+/*
+ * Malloc pool need to host env + 128 Kb reserve for other allocations.
+ */
+#define CFG_MALLOC_LEN	  (CFG_ENV_SIZE + (128<<10) )
+
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+#define CONFIG_STACKSIZE	(120<<10)      /* stack size */
+
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4<<10)	       /* IRQ stack  */
+#define CONFIG_STACKSIZE_FIQ	(4<<10)	       /* FIQ stack  */
+#endif
+
+/* SDRAM Setup Values
+ * 0x910a8300 Precharge Command CAS 3
+ * 0x910a8200 Precharge Command CAS 2
+ *
+ * 0xa10a8300 AutoRefresh Command CAS 3
+ * 0xa10a8200 Set AutoRefresh Command CAS 2
+ */
+#define PRECHARGE_CMD 0x910a8300
+#define AUTOREFRESH_CMD 0xa10a8300
+
+#define CONFIG_INIT_CRITICAL
+
+#define BUS32BIT_VERSION
+/*
+ * SDRAM Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS  1			     /* we have 1 bank of SDRAM */
+#define MX1FS2_SDRAM_1	      0x08000000	     /* SDRAM bank #1		*/
+#ifdef BUS32BIT_VERSION
+#define MX1FS2_SDRAM_1_SIZE  (0x04000000 - 0x100000) /* 64 MB - 1M Framebuffer */
+#else
+#define MX1FS2_SDRAM_1_SIZE  (0x01FC0000 - 0x100000) /* 32 MB - 1M Framebuffer */
+#endif
+/*
+ * Flash Controller settings
+ */
+
+#define CFG_MAX_FLASH_BANKS	1	/* FLASH banks count (not chip count)*/
+#define CFG_MAX_FLASH_SECT	256	/* number of sector in FLASH bank    */
+
+#ifdef BUS32BIT_VERSION
+#define MX1FS2_FLASH_BUS_WIDTH	4	/* we use 32 bit FLASH memory...     */
+#define MX1FS2_FLASH_INTERLEAVE 2	/* ... made of 2 chips */
+#define MX1FS2_FLASH_BANK_SIZE	0x02000000  /* size of one flash bank*/
+#define MX1FS2_FLASH_SECT_SIZE	0x00020000  /* size of erase sector */
+#define MX1FS2_JFFS2_PART0_START 0x10200000
+#define MX1FS2_JFFS2_PART0_SIZE	 0x00500000
+#define MX1FS2_JFFS2_PART1_START 0x10700000
+#define MX1FS2_JFFS2_PART1_SIZE	 0x00900000
+#else
+#define MX1FS2_FLASH_BUS_WIDTH	2	/* we use 16 bit FLASH memory...     */
+#define MX1FS2_FLASH_INTERLEAVE 1	/* ... made of 1 chip */
+#define MX1FS2_FLASH_BANK_SIZE	0x01000000  /* size of one flash bank*/
+#define MX1FS2_FLASH_SECT_SIZE	0x00010000  /* size of erase sector */
+#endif
+#define MX1FS2_FLASH_BASE	0x10000000  /* location of flash memory */
+#define MX1FS2_FLASH_UNLOCK	   1	   /* perform hw unlock first */
+
+/* This should be defined if CFI FLASH device is present. Actually benefit
+   is not so clear to me. In other words we can provide more informations
+   to user, but this expects more complex flash handling we do not provide
+   now.*/
+#undef	CFG_FLASH_CFI
+
+#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ)    /* timeout for Erase operation */
+#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ)    /* timeout for Write operation */
+
+#define CFG_FLASH_BASE		MX1FS2_FLASH_BASE
+
+/*
+ * This is setting for JFFS2 support in u-boot.
+ * Right now there is no gain for user, but later on booting kernel might be
+ * possible. Consider using XIP kernel running from flash to save RAM
+ * footprint.
+ * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support.
+ */
+#define CFG_JFFS2_FIRST_BANK		0
+#define CFG_JFFS2_FIRST_SECTOR		5
+#define CFG_JFFS2_NUM_BANKS		1
+
+/*
+ * Environment setup. Definitions of monitor location and size with
+ * definition of environment setup ends up in 2 possibilities.
+ * 1. Embeded environment - in u-boot code is space for environment
+ * 2. Environment is read from predefined sector of flash
+ * Right now we support 2. possiblity, but expecting no env placed
+ * on mentioned address right now. This also needs to provide whole
+ * sector for it - for us 256Kb is really waste of memory. U-boot uses
+ * default env. and until kernel parameters could be sent to kernel
+ * env. has no sense to us.
+ */
+
+#define CFG_MONITOR_BASE	0x10000000
+#define CFG_MONITOR_LEN		0x20000		/* 128b ( 1 flash sector )   */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		0x10020000	/* absolute address for now  */
+#define CFG_ENV_SIZE		0x20000
+
+#define	 CONFIG_ENV_OVERWRITE	1		/* env is not writable now   */
+
+/* Setup CS4 and CS5 */
+#define CFG_GIUS_A_VAL		0x0003fffe
+
+/*
+ * CSxU_VAL:
+ * 63| x	x x x | x x x x | x x  x    x | x x x x | x x x x | x x x x | x x x x | x x x x|32
+ *   |DTACK_SEL|0|BCD |	  BCS	| PSZ|PME|SYNC|	 DOL	| CNC|	  WSC	    | 0| WWS  |	  EDC  |
+ *
+ * CSxL_VAL:
+ * 31| x x x x | x x x x | x x x x | x x x x | x x x x |  x x x x | x x	 x x | x x  x	 x| 0
+ *   |	 OEA   |   OEN	 |   WEA   |   WEN   |	 CSA   |EBC| DSZ  | 0|SP|0|WP| 0 0|PA|CSEN|
+ */
+
+#define CFG_CS0U_VAL 0x00008C00
+#define CFG_CS0L_VAL 0x22222601
+#define CFG_CS1U_VAL 0x00008C00
+#define CFG_CS1L_VAL 0x22222301
+#define CFG_CS4U_VAL 0x00008C00
+#define CFG_CS4L_VAL 0x22222301
+#define CFG_CS5U_VAL 0x00008C00
+#define CFG_CS5L_VAL 0x22222301
+
+/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
+   f_ref=16,777MHz
+
+   0x002a141f: 191,9944MHz
+   0x040b2007: 144MHz
+   0x042a141f: 96MHz
+   0x0811140d: 64MHz
+   0x040e200e: 150MHz
+   0x00321431: 200MHz
+
+   0x08001800: 64MHz mit 16er Quarz
+   0x04001800: 96MHz mit 16er Quarz
+   0x04002400: 144MHz mit 16er Quarz
+
+   31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
+      |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------|	    */
+
+#define CFG_MPCTL0_VAL		0x07E723AD
+#define CFG_MPCTL1_VAL		0x00000040
+#define CFG_PCDR_VAL		0x00010005
+#define CFG_GPCR_VAL		0x00000FFB
+
+#define USE_16M_OSZI /* If you have one, you want to use it
+			The internal 32kHz oszillator jitters */
+#ifdef USE_16M_OSZI
+
+#define CFG_SPCTL0_VAL		0x04001401
+#define CFG_SPCTL1_VAL		0x0C000040
+#define CFG_CSCR_VAL		0x07030003
+#define CONFIG_SYS_CLK_FREQ	16780000
+#define CONFIG_SYSPLL_CLK_FREQ	16000000
+
+#else
+
+#define CFG_SPCTL0_VAL		0x07E716D1
+#define CFG_CSCR_VAL		0x06000003
+#define CONFIG_SYS_CLK_FREQ	16780000
+#define CONFIG_SYSPLL_CLK_FREQ	16780000
+
+#endif
+
+/*
+ * Well this has to be defined, but on the other hand it is used differently
+ * one may expect. For instance loadb command do not cares :-)
+ * So advice is - do not relay on this...
+ */
+#define CFG_LOAD_ADDR		0x08400000
+
+#define CFG_FMCR_VAL		0x00000003 /* Reset Default */
+
+/* Bit[0:3] contain PERCLK1DIV for UART 1
+   0x000b00b ->b<- -> 192MHz/12=16MHz
+   0x000b00b ->8<- -> 144MHz/09=16MHz
+   0x000b00b ->3<- -> 64MHz/4=16MHz */
+
+#ifdef _CONFIG_UART1
+#define CONFIG_IMX_SERIAL1
+#elif defined _CONFIG_UART2
+#define CONFIG_IMX_SERIAL2
+#elif defined _CONFIG_UART3 | defined _CONFIG_UART4
+#define CONFIG_IMX_SERIAL_NONE
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_CLK		3686400
+#define CFG_NS16550_REG_SIZE	1
+#define CONFIG_CONS_INDEX	1
+#ifdef _CONFIG_UART3
+#define CFG_NS16550_COM1	0x15000000
+#elif defined _CONFIG_UART4
+#define CFG_NS16550_COM1	0x16000000
+#endif
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h
new file mode 100644
index 00000000000..6cd91269d43
--- /dev/null
+++ b/include/configs/scb9328.h
@@ -0,0 +1,357 @@
+/*
+ * Copyright (C) 2003 ETC s.r.o.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Written by Peter Figuli <peposh@etc.sk>, 2003.
+ *
+ * 2003/13/06 Initial MP10 Support copied from wepep250
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_ARM920T		1     /* this is an ARM920T CPU	    */
+#define CONFIG_IMX		1     /* in a Motorola MC9328MXL Chip */
+#define CONFIG_SCB9328		1     /* on a scb9328tronix board */
+#undef	CONFIG_USE_IRQ		      /* don't need use IRQ/FIQ	   */
+
+#define CONFIG_IMX_SERIAL1
+/*
+ * Select serial console configuration
+ */
+
+
+/*
+ * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if
+ * neccessary in include/cmd_confdefs.h file. (Un)comment for getting
+ * functionality or size of u-boot code.
+ */
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL		\
+				& ~CFG_CMD_LOADS	\
+				& ~CFG_CMD_CONSOLE	\
+				& ~CFG_CMD_AUTOSCRIPT	\
+				| CFG_CMD_NET		\
+				| CFG_CMD_PING		\
+				| CFG_CMD_DHCP		\
+				)
+
+#include <cmd_confdefs.h>
+
+/*
+ * Boot options. Setting delay to -1 stops autostart count down.
+ * NOTE: Sending parameters to kernel depends on kernel version and
+ * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept
+ * parameters at all! Do not get confused by them so.
+ */
+#define CONFIG_BOOTDELAY   -1
+#define CONFIG_BOOTARGS	   "console=ttySMX0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=scb9328_flash:128k(U-boot)ro,128k(U-boot_env),1m(kernel),4m(root),4m(fs) eval_board=evk9328"
+#define CONFIG_BOOTCOMMAND "bootm 10040000"
+#define CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_ETHADDR		80:81:82:83:84:85
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		10.10.10.9
+#define CONFIG_SERVERIP		10.10.10.10
+
+/*
+ * General options for u-boot. Modify to save memory foot print
+ */
+#define CFG_LONGHELP				      /* undef saves memory  */
+#define CFG_PROMPT		"scb9328> "	      /* prompt string	     */
+#define CFG_CBSIZE		256		      /* console I/O buffer  */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size   */
+#define CFG_MAXARGS		16		      /* max command args    */
+#define CFG_BARGSIZE		CFG_CBSIZE	      /* boot args buf size  */
+
+#define CFG_MEMTEST_START	0x08100000	      /* memtest test area   */
+#define CFG_MEMTEST_END		0x08F00000
+
+#undef	CFG_CLKS_IN_HZ			     /* use HZ for freq. display     */
+
+#define CFG_HZ			3686400	     /* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED		0x141	     /* core clock - register value  */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_BAUDRATE 115200
+/*
+ * Definitions related to passing arguments to kernel.
+ */
+#define CONFIG_CMDLINE_TAG	     1	 /* send commandline to Kernel	     */
+#define CONFIG_SETUP_MEMORY_TAGS     1	 /* send memory definition to kernel */
+#define CONFIG_INITRD_TAG	     1	 /* send initrd params		     */
+#undef	CONFIG_VFD			 /* do not send framebuffer setup    */
+
+
+/*
+ * Malloc pool need to host env + 128 Kb reserve for other allocations.
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + (128<<10) )
+
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+#define CONFIG_STACKSIZE	(120<<10)      /* stack size		     */
+
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4<<10)	       /* IRQ stack		     */
+#define CONFIG_STACKSIZE_FIQ	(4<<10)	       /* FIQ stack		     */
+#endif
+
+/* SDRAM Setup Values
+0x910a8300 Precharge Command CAS 3
+0x910a8200 Precharge Command CAS 2
+
+0xa10a8300 AutoRefresh Command CAS 3
+0xa10a8200 Set AutoRefresh Command CAS 2 */
+
+#define PRECHARGE_CMD 0x910a8200
+#define AUTOREFRESH_CMD 0xa10a8200
+#define CONFIG_INIT_CRITICAL
+
+/*
+ * SDRAM Memory Map
+ */
+/* SH FIXME */
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of SDRAM */
+#define SCB9328_SDRAM_1		0x08000000	/* SDRAM bank #1	   */
+#define SCB9328_SDRAM_1_SIZE	0x01000000	/* 16 MB		   */
+
+/*
+ * Flash Controller settings
+ */
+
+/*
+ * Hardware drivers
+ */
+
+
+/*
+ * Configuration for FLASH memory for the Synertronixx board
+ */
+
+/* #define SCB9328_FLASH_32M */
+
+/* 32MB */
+#ifdef SCB9328_FLASH_32M
+#define CFG_MAX_FLASH_BANKS		1	/* FLASH banks count (not chip count)*/
+#define CFG_MAX_FLASH_SECT		256	/* number of sector in FLASH bank    */
+#define SCB9328_FLASH_BUS_WIDTH		2	/* we use 16 bit FLASH memory...     */
+#define SCB9328_FLASH_INTERLEAVE	1	/* ... made of 1 chip		     */
+#define SCB9328_FLASH_BANK_SIZE	 0x02000000	/* size of one flash bank	     */
+#define SCB9328_FLASH_SECT_SIZE	 0x00020000	/* size of erase sector		     */
+#define SCB9328_FLASH_BASE	 0x10000000	/* location of flash memory	     */
+#define SCB9328_FLASH_UNLOCK		1	/* perform hw unlock first	     */
+#else
+
+/* 16MB */
+#define CFG_MAX_FLASH_BANKS		1	/* FLASH banks count (not chip count)*/
+#define CFG_MAX_FLASH_SECT		128	/* number of sector in FLASH bank    */
+#define SCB9328_FLASH_BUS_WIDTH		2	/* we use 16 bit FLASH memory...     */
+#define SCB9328_FLASH_INTERLEAVE	1	/* ... made of 1 chip		     */
+#define SCB9328_FLASH_BANK_SIZE	 0x01000000	/* size of one flash bank	     */
+#define SCB9328_FLASH_SECT_SIZE	 0x00020000	/* size of erase sector		     */
+#define SCB9328_FLASH_BASE	 0x10000000	/* location of flash memory	     */
+#define SCB9328_FLASH_UNLOCK		1	/* perform hw unlock first	     */
+#endif /* SCB9328_FLASH_32M */
+
+/* This should be defined if CFI FLASH device is present. Actually benefit
+   is not so clear to me. In other words we can provide more informations
+   to user, but this expects more complex flash handling we do not provide
+   now.*/
+#undef	CFG_FLASH_CFI
+
+#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ)    /* timeout for Erase operation */
+#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ)    /* timeout for Write operation */
+
+#define CFG_FLASH_BASE		SCB9328_FLASH_BASE
+
+/*
+ * This is setting for JFFS2 support in u-boot.
+ * Right now there is no gain for user, but later on booting kernel might be
+ * possible. Consider using XIP kernel running from flash to save RAM
+ * footprint.
+ * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support.
+ */
+#define CFG_JFFS2_FIRST_BANK		0
+#define CFG_JFFS2_FIRST_SECTOR		5
+#define CFG_JFFS2_NUM_BANKS		1
+
+/*
+ * Environment setup. Definitions of monitor location and size with
+ * definition of environment setup ends up in 2 possibilities.
+ * 1. Embeded environment - in u-boot code is space for environment
+ * 2. Environment is read from predefined sector of flash
+ * Right now we support 2. possiblity, but expecting no env placed
+ * on mentioned address right now. This also needs to provide whole
+ * sector for it - for us 256Kb is really waste of memory. U-boot uses
+ * default env. and until kernel parameters could be sent to kernel
+ * env. has no sense to us.
+ */
+
+/* Setup for PA23 which is Reset Default PA23 but has to become
+   CS5 */
+
+#define CFG_GPR_A_VAL		0x00800000
+#define CFG_GIUS_A_VAL		0x0043fffe
+
+#define CFG_MONITOR_BASE	0x10000000
+#define CFG_MONITOR_LEN		0x20000		/* 128b ( 1 flash sector )  */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		0x10020000	/* absolute address for now  */
+#define CFG_ENV_SIZE		0x20000
+
+#define	 CONFIG_ENV_OVERWRITE  1		/* env is not writable now   */
+
+/*
+ * CSxU_VAL:
+ * 63| x	x x x | x x x x | x x  x    x | x x x x | x x x x | x x x x | x x x x | x x x x|32
+ *   |DTACK_SEL|0|BCD |	  BCS	| PSZ|PME|SYNC|	 DOL	| CNC|	  WSC	    | 0| WWS  |	  EDC  |
+ *
+ * CSxL_VAL:
+ * 31| x x x x | x x x x | x x x x | x x x x | x x x x |  x x x x | x x	 x x | x x  x	 x| 0
+ *   |	 OEA   |   OEN	 |   WEA   |   WEN   |	 CSA   |EBC| DSZ  | 0|SP|0|WP| 0 0|PA|CSEN|
+ */
+
+#define CFG_CS0U_VAL 0x000F2000
+#define CFG_CS0L_VAL 0x11110d01
+#define CFG_CS1U_VAL 0x000F0a00
+#define CFG_CS1L_VAL 0x11110601
+#define CFG_CS2U_VAL 0x0
+#define CFG_CS2L_VAL 0x0
+
+#define CFG_CS3U_VAL 0x000FFFFF
+#define CFG_CS3L_VAL 0x00000303
+
+#define CFG_CS4U_VAL 0x000F0a00
+#define CFG_CS4L_VAL 0x11110301
+
+/* CNC == 3 too long
+   #define CFG_CS5U_VAL 0x0000C210 */
+
+/* #define CFG_CS5U_VAL 0x00008400
+   mal laenger mahcen, ob der bei 150MHz laenger haelt dann und
+   kaum langsamer ist */
+/* #define CFG_CS5U_VAL 0x00009400
+   #define CFG_CS5L_VAL 0x11010D03 */
+
+#define CFG_CS5U_VAL 0x00008400
+#define CFG_CS5L_VAL 0x00000D03
+
+#define CONFIG_DRIVER_DM9000		1
+#define CONFIG_DRIVER_DM9000		1
+#define CONFIG_DM9000_BASE		0x16000000
+#define DM9000_IO			CONFIG_DM9000_BASE
+#define DM9000_DATA			(CONFIG_DM9000_BASE+4)
+/* #define CONFIG_DM9000_USE_8BIT */
+#define CONFIG_DM9000_USE_16BIT
+/* #define CONFIG_DM9000_USE_32BIT */
+
+/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
+   f_ref=16,777MHz
+
+   0x002a141f: 191,9944MHz
+   0x040b2007: 144MHz
+   0x042a141f: 96MHz
+   0x0811140d: 64MHz
+   0x040e200e: 150MHz
+   0x00321431: 200MHz
+
+   0x08001800: 64MHz mit 16er Quarz
+   0x04001800: 96MHz mit 16er Quarz
+   0x04002400: 144MHz mit 16er Quarz
+
+   31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
+      |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------|	    */
+
+#define CPU200
+
+#ifdef CPU200
+#define CFG_MPCTL0_VAL 0x00321431
+#else
+#define CFG_MPCTL0_VAL 0x040e200e
+#endif
+
+/* #define BUS64 */
+#define BUS72
+
+#ifdef BUS72
+#define CFG_SPCTL0_VAL 0x04002400
+#endif
+
+#ifdef BUS96
+#define CFG_SPCTL0_VAL 0x04001800
+#endif
+
+#ifdef BUS64
+#define CFG_SPCTL0_VAL 0x08001800
+#endif
+
+/* Das ist der BCLK Divider, der aus der System PLL
+   BCLK und HCLK erzeugt:
+   31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0
+   0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2
+   0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2
+   0x2f001003 : 192MHz/5=38,4MHz
+   0x2f000003 : 64MHz/1
+   Bit 22: SPLL Restart
+   Bit 21: MPLL Restart */
+
+#ifdef BUS64
+#define CFG_CSCR_VAL 0x2f030003
+#endif
+
+#ifdef BUS72
+#define CFG_CSCR_VAL 0x2f030403
+#endif
+
+/*
+ * Well this has to be defined, but on the other hand it is used differently
+ * one may expect. For instance loadb command do not cares :-)
+ * So advice is - do not relay on this...
+ */
+#define CFG_LOAD_ADDR 0x08400000
+
+#define MHZ16QUARZINUSE
+
+#ifdef MHZ16QUARZINUSE
+#define CONFIG_SYSPLL_CLK_FREQ 16000000
+#else
+#define CONFIG_SYSPLL_CLK_FREQ 16780000
+#endif
+
+#define CONFIG_SYS_CLK_FREQ 16780000
+
+/* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */
+#define CFG_FMCR_VAL 0x00000001
+
+/* Bit[0:3] contain PERCLK1DIV for UART 1
+   0x000b00b ->b<- -> 192MHz/12=16MHz
+   0x000b00b ->8<- -> 144MHz/09=16MHz
+   0x000b00b ->3<- -> 64MHz/4=16MHz */
+
+#ifdef BUS96
+#define CFG_PCDR_VAL 0x000b00b5
+#endif
+
+#ifdef BUS64
+#define CFG_PCDR_VAL 0x000b00b3
+#endif
+
+#ifdef BUS72
+#define CFG_PCDR_VAL 0x000b00b8
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/devices.h b/include/devices.h
index 9f2a0c34acc..09c2c5f511f 100644
--- a/include/devices.h
+++ b/include/devices.h
@@ -39,7 +39,7 @@
 typedef struct {
 	int	flags;			/* Device flags: input/output/system	*/
 	int	ext;			/* Supported extensions			*/
-	char	name[8];		/* Device name				*/
+	char	name[16];		/* Device name				*/
 
 /* GENERAL functions */
 
diff --git a/include/mc9328.h b/include/mc9328.h
deleted file mode 100644
index 2a6e7577fb3..00000000000
--- a/include/mc9328.h
+++ /dev/null
@@ -1,1051 +0,0 @@
-/*
- * include/mc9328.h
- *
- * (c) Copyright 2004
- * Techware Information Technology, Inc.
- * http://www.techware.com.tw/
- *
- * Ming-Len Wu <minglen_wu@techware.com.tw>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __MC9328_H__
-#define __MC9328_H__
-
-typedef volatile unsigned long	VU32;
-typedef VU32	*		P_VU32;
-
-#define __REG(x)		(*((volatile u32 *)(x)))
-
-/*
- * MX1 Chip selects & internal memory's
- */
-#define MX1_DMI_PHYS	0x00000000	/* double map image	*/
-#define MX1_BROM_PHYS	0x00100000	/* Bootstrape ROM	*/
-#define MX1_ESRAM_PHYS	0x00300000	/* Embedded SRAM (128KB)*/
-
-#define MX1_CSD0_PHYS	0x08000000	/* CSD0 64MB (SDRAM)	*/
-#define MX1_CSD1_PHYS	0x0C000000	/* CSD1 64MB (SDRAM)	*/
-#define MX1_CS0_PHYS	0x10000000	/* CS0 32MB (Flash)	*/
-#define MX1_CS1_PHYS	0x12000000	/* CS1 16MB (Flash)	*/
-#define MX1_CS2_PHYS	0x13000000	/* CS2 16MB (Ext SRAM)	*/
-#define MX1_CS3_PHYS	0x14000000	/* CS3 16MB (Spare)	*/
-#define MX1_CS4_PHYS	0x15000000	/* CS4 16MB (Spare)	*/
-#define MX1_CS5_PHYS	0x16000000	/* CS5 16MB (Spare)	*/
-
-/*
- *	MX1 Watchdog registers
- */
-#define MX1_WCR		__REG(0x00201000)  /* Watchdog Control Register		*/
-#define MX1_WSR		__REG(0x00201004)  /* Watchdog Service Register		*/
-#define MX1_WSTR	__REG(0x00201008)  /* Watchdog Status Register		*/
-
-/*
- *	MX1 Timer registers
- */
-#define MX1_TCTL1	__REG(0x00202000)  /* Timer 1 Control Register		*/
-#define MX1_TPRER1	__REG(0x00202004)  /* Timer 1 Prescaler Register	*/
-#define MX1_TCMP1	__REG(0x00202008)  /* Timer 1 Compare Register		*/
-#define MX1_TCR1	__REG(0x0020200C)  /* Timer 1 Capture Register		*/
-#define MX1_TCN1	__REG(0x00202010)  /* Timer 1 Counter Register		*/
-#define MX1_TSTAT1	__REG(0x00202014)  /* Timer 1 Status Register		*/
-
-#define MX1_TCTL2	__REG(0x00203000)  /* Timer 2 Control Register		*/
-#define MX1_TPRER2	__REG(0x00203004)  /* Timer 2 Prescaler Register	*/
-#define MX1_TCMP2	__REG(0x00203008)  /* Timer 2 Compare Register		*/
-#define MX1_TCR2	__REG(0x0020300C)  /* Timer 2 Capture Register		*/
-#define MX1_TCN2	__REG(0x00203010)  /* Timer 2 Counter Register		*/
-#define MX1_TSTAT2	__REG(0x00203014)  /* Timer 2 Status Register		*/
-
-/*
- *	MX1 RTC registers
- */
-#define MX1_HOURMIN	__REG(0x00204000)  /* RTC Hour & Min Counter Registers	*/
-#define MX1_SECONDS	__REG(0x00204004)  /* RTC Seconds Counter Registers	*/
-#define MX1_ALRM_HM	__REG(0x00204008)  /* RTC Hour & Min Alarm Registers	*/
-#define MX1_ALRM_SEC	__REG(0x0020400C)  /* RTC Seconds Alarm Registers	*/
-#define MX1_RCCTL	__REG(0x00204010)  /* RTC Control Registers		*/
-#define MX1_RTCISR	__REG(0x00204014)  /* RTC Interrupt Status Registers	*/
-#define MX1_RTCIENR	__REG(0x00204018)  /* RTC Interrupt Enable Registers	*/
-#define MX1_STPWCH	__REG(0x0020401C)  /* RTC Stopwatch Minutes Registers	*/
-#define MX1_DAYR	__REG(0x00204020)  /* RTC Days Counter Registers	*/
-#define MX1_DAYALARM	__REG(0x00204020)  /* RTC Day Alarm Registers		*/
-
-/*
- *	MX1 LCD Controller registers
- */
-#define MX1_SSA		__REG(0x00205000)  /* Screen Start Address Register	*/
-#define MX1_SIZE	__REG(0x00205004)  /* Size Register			*/
-#define MX1_VPW		__REG(0x00205008)  /* Virtual Page Width Register	*/
-#define MX1_CPOS	__REG(0x0020500C)  /* LCD Cursor Position  Register	*/
-#define MX1_LCWHB	__REG(0x00205010)  /* LCD Cursor Width Height & Blink Register	*/
-#define MX1_LCHCC	__REG(0x00205014)  /* LCD Color Cursor Mapping Register */
-#define MX1_PCR		__REG(0x00205018)  /* LCD Panel Configuration Register	*/
-#define MX1_HCR		__REG(0x0020501C)  /* Horizontal Configuration Register */
-#define MX1_VCR		__REG(0x00205020)  /* Vertical Configuration Register	*/
-#define MX1_POS		__REG(0x00205024)  /* Panning Offset Register		*/
-#define MX1_LGPMR	__REG(0x00205028)  /* LCD Gray Palette Mapping Register */
-#define MX1_PWMR	__REG(0x0020502C)  /* PWM Contrast Control Register	*/
-#define MX1_DMACR	__REG(0x00205030)  /* DMA Control Register		*/
-#define MX1_RMCR	__REG(0x00205034)  /* Refresh Mode Control Register	*/
-#define MX1_LCDICR	__REG(0x00205038)  /* Interrupt Configuration Register	*/
-#define MX1_LCDISR	__REG(0x00205040)  /* Interrupt Status Register		*/
-
-/*
- *	MX1 UART registers
- */
-
-/* UART 1 */
-#define MX1_URX0D_1	__REG(0x00206000)  /* UART 1 Receiver Register 0	*/
-#define MX1_URX1D_1	__REG(0x00206004)  /* UART 1 Receiver Register 1	*/
-#define MX1_URX2D_1	__REG(0x00206008)  /* UART 1 Receiver Register 2	*/
-#define MX1_URX3D_1	__REG(0x0020600C)  /* UART 1 Receiver Register 3	*/
-#define MX1_URX4D_1	__REG(0x00206010)  /* UART 1 Receiver Register 4	*/
-#define MX1_URX5D_1	__REG(0x00206014)  /* UART 1 Receiver Register 5	*/
-#define MX1_URX6D_1	__REG(0x00206018)  /* UART 1 Receiver Register 6	*/
-#define MX1_URX7D_1	__REG(0x0020601C)  /* UART 1 Receiver Register 7	*/
-#define MX1_URX8D_1	__REG(0x00206020)  /* UART 1 Receiver Register 8	*/
-#define MX1_URX9D_1	__REG(0x00206024)  /* UART 1 Receiver Register 9	*/
-#define MX1_URX10D_1	__REG(0x00206028)  /* UART 1 Receiver Register 10	*/
-#define MX1_URX11D_1	__REG(0x0020602C)  /* UART 1 Receiver Register 11	*/
-#define MX1_URX12D_1	__REG(0x00206030)  /* UART 1 Receiver Register 12	*/
-#define MX1_URX13D_1	__REG(0x00206034)  /* UART 1 Receiver Register 13	*/
-#define MX1_URX14D_1	__REG(0x00206038)  /* UART 1 Receiver Register 14	*/
-#define MX1_URX15D_1	__REG(0x0020603c)  /* UART 1 Receiver Register 15	*/
-
-#define MX1_UTX0D_1	__REG(0x00206040)  /* UART 1 Transmitter Register 0	*/
-#define MX1_UTX1D_1	__REG(0x00206044)  /* UART 1 Transmitter Register 1	*/
-#define MX1_UTX2D_1	__REG(0x00206048)  /* UART 1 Transmitter Register 2	*/
-#define MX1_UTX3D_1	__REG(0x0020604C)  /* UART 1 Transmitter Register 3	*/
-#define MX1_UTX4D_1	__REG(0x00206050)  /* UART 1 Transmitter Register 4	*/
-#define MX1_UTX5D_1	__REG(0x00206054)  /* UART 1 Transmitter Register 5	*/
-#define MX1_UTX6D_1	__REG(0x00206058)  /* UART 1 Transmitter Register 6	*/
-#define MX1_UTX7D_1	__REG(0x0020605C)  /* UART 1 Transmitter Register 7	*/
-#define MX1_UTX8D_1	__REG(0x00206060)  /* UART 1 Transmitter Register 8	*/
-#define MX1_UTX9D_1	__REG(0x00206064)  /* UART 1 Transmitter Register 9	*/
-#define MX1_UTX10D_1	__REG(0x00206068)  /* UART 1 Transmitter Register 10	*/
-#define MX1_UTX11D_1	__REG(0x0020606C)  /* UART 1 Transmitter Register 11	*/
-#define MX1_UTX12D_1	__REG(0x00206060)  /* UART 1 Transmitter Register 12	*/
-#define MX1_UTX13D_1	__REG(0x00206074)  /* UART 1 Transmitter Register 13	*/
-#define MX1_UTX14D_1	__REG(0x00206078)  /* UART 1 Transmitter Register 14	*/
-#define MX1_UTX15D_1	__REG(0x0020607c)  /* UART 1 Transmitter Register 15	*/
-
-#define MX1_UCR1_1	__REG(0x00206080)  /* UART 1 Control Register 1		*/
-#define MX1_UCR2_1	__REG(0x00206084)  /* UART 1 Control Register 2		*/
-#define MX1_UCR3_1	__REG(0x00206088)  /* UART 1 Control Register 3		*/
-#define MX1_UCR4_1	__REG(0x0020608C)  /* UART 1 Control Register 4		*/
-#define MX1_UFCR_1	__REG(0x00206090)  /* UART 1 FIFO Control Register	*/
-#define MX1_USR1_1	__REG(0x00206094)  /* UART 1 Status  Register 1		*/
-#define MX1_USR2_1	__REG(0x00206098)  /* UART 1 Status  Register 2		*/
-#define MX1_UESC_1	__REG(0x0020609C)  /* UART 1 Escape Character Register	*/
-#define MX1_UTIM_1	__REG(0x002060A0)  /* UART 1 Escape Timer Register	*/
-#define MX1_UBIR_1	__REG(0x002060A4)  /* UART 1 BRM Incremental Register	*/
-#define MX1_UBMR_1	__REG(0x002060A8)  /* UART 1 BRM Modulator Register	*/
-#define MX1_UBRC_1	__REG(0x002060AC)  /* UART 1 Baud Rate Count Register	*/
-#define MX1_BIPR1_1	__REG(0x002060B0)  /* UART 1 BRM Incremental Preset Register 1	*/
-#define MX1_BIPR2_1	__REG(0x002060B4)  /* UART 1 BRM Incremental Preset Register 2	*/
-#define MX1_BIPR3_1	__REG(0x002060B8)  /* UART 1 BRM Incremental Preset Register 3	*/
-#define MX1_BIPR4_1	__REG(0x002060BC)  /* UART 1 BRM Incremental Preset Register 4	*/
-#define MX1_BMPR1_1	__REG(0x002060C0)  /* UART 1 BRM Modulator Preset Register 1	*/
-#define MX1_BMPR2_1	__REG(0x002060C4)  /* UART 1 BRM Modulator Preset Register 2	*/
-#define MX1_BMPR3_1	__REG(0x002060C8)  /* UART 1 BRM Modulator Preset Register 3	*/
-#define MX1_BMPR4_1	__REG(0x002060CC)  /* UART 1 BRM Modulator Preset Register 4	*/
-#define MX1_UTS_1	__REG(0x002060D0)  /* UART 1 Test Register 1		*/
-
-/* UART 2 */
-#define MX1_URX0D_2	__REG(0x00207000)  /* UART 2 Receiver Register 0	*/
-#define MX1_URX1D_2	__REG(0x00207004)  /* UART 2 Receiver Register 1	*/
-#define MX1_URX2D_2	__REG(0x00207008)  /* UART 2 Receiver Register 2	*/
-#define MX1_URX3D_2	__REG(0x0020700C)  /* UART 2 Receiver Register 3	*/
-#define MX1_URX4D_2	__REG(0x00207010)  /* UART 2 Receiver Register 4	*/
-#define MX1_URX5D_2	__REG(0x00207014)  /* UART 2 Receiver Register 5	*/
-#define MX1_URX6D_2	__REG(0x00207018)  /* UART 2 Receiver Register 6	*/
-#define MX1_URX7D_2	__REG(0x0020701C)  /* UART 2 Receiver Register 7	*/
-#define MX1_URX8D_2	__REG(0x00207020)  /* UART 2 Receiver Register 8	*/
-#define MX1_URX9D_2	__REG(0x00207024)  /* UART 2 Receiver Register 9	*/
-#define MX1_URX10D_2	__REG(0x00207028)  /* UART 2 Receiver Register 10	*/
-#define MX1_URX11D_2	__REG(0x0020702C)  /* UART 2 Receiver Register 11	*/
-#define MX1_URX12D_2	__REG(0x00207030)  /* UART 2 Receiver Register 12	*/
-#define MX1_URX13D_2	__REG(0x00207034)  /* UART 2 Receiver Register 13	*/
-#define MX1_URX14D_2	__REG(0x00207038)  /* UART 2 Receiver Register 14	*/
-#define MX1_URX15D_2	__REG(0x0020703c)  /* UART 2 Receiver Register 15	*/
-
-#define MX1_UTX0D_2	__REG(0x00207040)  /* UART 2 Transmitter Register 0	*/
-#define MX1_UTX1D_2	__REG(0x00207044)  /* UART 2 Transmitter Register 1	*/
-#define MX1_UTX2D_2	__REG(0x00207048)  /* UART 2 Transmitter Register 2	*/
-#define MX1_UTX3D_2	__REG(0x0020704C)  /* UART 2 Transmitter Register 3	*/
-#define MX1_UTX4D_2	__REG(0x00207050)  /* UART 2 Transmitter Register 4	*/
-#define MX1_UTX5D_2	__REG(0x00207054)  /* UART 2 Transmitter Register 5	*/
-#define MX1_UTX6D_2	__REG(0x00207058)  /* UART 2 Transmitter Register 6	*/
-#define MX1_UTX7D_2	__REG(0x0020705C)  /* UART 2 Transmitter Register 7	*/
-#define MX1_UTX8D_2	__REG(0x00207060)  /* UART 2 Transmitter Register 8	*/
-#define MX1_UTX9D_2	__REG(0x00207064)  /* UART 2 Transmitter Register 9	*/
-#define MX1_UTX10D_2	__REG(0x00207068)  /* UART 2 Transmitter Register 10	*/
-#define MX1_UTX11D_2	__REG(0x0020706C)  /* UART 2 Transmitter Register 11	*/
-#define MX1_UTX12D_2	__REG(0x00207060)  /* UART 2 Transmitter Register 12	*/
-#define MX1_UTX13D_2	__REG(0x00207074)  /* UART 2 Transmitter Register 13	*/
-#define MX1_UTX14D_2	__REG(0x00207078)  /* UART 2 Transmitter Register 14	*/
-#define MX1_UTX15D_2	__REG(0x0020707c)  /* UART 2 Transmitter Register 15	*/
-
-#define MX1_UCR1_2	__REG(0x00207080)  /* UART 2 Control Register 1		*/
-#define MX1_UCR2_2	__REG(0x00207084)  /* UART 2 Control Register 2		*/
-#define MX1_UCR3_2	__REG(0x00207088)  /* UART 2 Control Register 3		*/
-#define MX1_UCR4_2	__REG(0x0020708C)  /* UART 2 Control Register 4		*/
-#define MX1_UFCR_2	__REG(0x00207090)  /* UART 2 FIFO Control Register	*/
-#define MX1_USR1_2	__REG(0x00207094)  /* UART 2 Status  Register 1		*/
-#define MX1_USR2_2	__REG(0x00207098)  /* UART 2 Status  Register 2		*/
-#define MX1_UESC_2	__REG(0x0020709C)  /* UART 2 Escape Character Register	*/
-#define MX1_UTIM_2	__REG(0x002070A0)  /* UART 2 Escape Timer Register	*/
-#define MX1_UBIR_2	__REG(0x002070A4)  /* UART 2 BRM Incremental Register	*/
-#define MX1_UBMR_2	__REG(0x002070A8)  /* UART 2 BRM Modulator Register	*/
-#define MX1_UBRC_2	__REG(0x002070AC)  /* UART 2 Baud Rate Count Register	*/
-#define MX1_BIPR1_2	__REG(0x002070B0)  /* UART 2 BRM Incremental Preset Register 1	*/
-#define MX1_BIPR2_2	__REG(0x002070B4)  /* UART 2 BRM Incremental Preset Register 2	*/
-#define MX1_BIPR3_2	__REG(0x002070B8)  /* UART 2 BRM Incremental Preset Register 3	*/
-#define MX1_BIPR4_2	__REG(0x002070BC)  /* UART 2 BRM Incremental Preset Register 4	*/
-#define MX1_BMPR1_2	__REG(0x002070C0)  /* UART 2 BRM Modulator Preset Register 1	*/
-#define MX1_BMPR2_2	__REG(0x002070C4)  /* UART 2 BRM Modulator Preset Register 2	*/
-#define MX1_BMPR3_2	__REG(0x002070C8)  /* UART 2 BRM Modulator Preset Register 3	*/
-#define MX1_BMPR4_2	__REG(0x002070CC)  /* UART 2 BRM Modulator Preset Register 4	*/
-#define MX1_UTS_2	__REG(0x002070D0)  /* UART 2 Test Register 1		*/
-
-/*
- *	MX1 PWM registers
- */
-#define MX1_PWMC	__REG(0x00208000)  /* PWM Control Register		*/
-#define MX1_PWMS	__REG(0x00208004)  /* PWM Sample Register		*/
-#define MX1_PWMP	__REG(0x00208008)  /* PWM Period Register		*/
-#define MX1_PWMCNT	__REG(0x0020800C)  /* PWM Counter Register		*/
-
-/*
- *	MX1 DMAC registers
- */
-#define MX1_DCR		__REG(0x00209000)  /* DMA Control Register		*/
-#define MX1_DISR	__REG(0x00209004)  /* DMA Interrupt Status Register	*/
-#define MX1_DIMR	__REG(0x00209008)  /* DMA Interrupt Mask Register	*/
-#define MX1_DBTOSR	__REG(0x0020900C)  /* DMA Burst Time-Out Status Register	*/
-#define MX1_DRTOSR	__REG(0x00209010)  /* DMA Request Time-Out Status Register	*/
-#define MX1_DSESR	__REG(0x00209014)  /* DMA Request Time-Out Status Register	*/
-#define MX1_DBOSR	__REG(0x00209018)  /* DMA Buffer Overflow Status Register	*/
-#define MX1_DBTOCR	__REG(0x0020901C)  /* DMA Burst Time-Out Control Register	*/
-
-#define MX1_WSRA	__REG(0x00209040)  /* DMA W-Size Register A		*/
-#define MX1_XSRA	__REG(0x00209044)  /* DMA X-Size Register A		*/
-#define MX1_YSRA	__REG(0x00209048)  /* DMA Y-Size Register A		*/
-
-#define MX1_WSRB	__REG(0x0020904C)  /* DMA W-Size Register B		*/
-#define MX1_XSRB	__REG(0x00209050)  /* DMA X-Size Register B		*/
-#define MX1_YSRB	__REG(0x00209054)  /* DMA Y-Size Register B		*/
-
-/* Channel 0 */
-
-#define MX1_SAR0	__REG(0x00209080)  /* Channel 0 Source Address Register */
-#define MX1_DAR0	__REG(0x00209084)  /* Channel 0 Destination Address Register	*/
-#define MX1_CNTR0	__REG(0x00209088)  /* Channel 0 Count Register		*/
-#define MX1_CCR0	__REG(0x0020908C)  /* Channel 0 Control Register	*/
-#define MX1_RSSR0	__REG(0x00209090)  /* Channel 0 Request Source Select Register	*/
-#define MX1_BLR0	__REG(0x00209094)  /* Channel 0 Burst Length  Register	*/
-#define MX1_RTOR0	__REG(0x00209098)  /* Channel 0 Request Time-Out Register	*/
-#define MX1_BUCR0	__REG(0x00209098)  /* Channel 0 Bus Utilization Control Register	*/
-
-/* Channel 1 */
-
-#define MX1_SAR1	__REG(0x002090C0)  /* Channel 1 Source Address Register */
-#define MX1_DAR1	__REG(0x002090C4)  /* Channel 1 Destination Address Register	*/
-#define MX1_CNTR1	__REG(0x002090C8)  /* Channel 1 Count Register		*/
-#define MX1_CCR1	__REG(0x002090CC)  /* Channel 1 Control Register	*/
-#define MX1_RSSR1	__REG(0x002090D0)  /* Channel 1 Request Source Select Register	*/
-#define MX1_BLR1	__REG(0x002090D4)  /* Channel 1 Burst Length  Register	*/
-#define MX1_RTOR1	__REG(0x002090D8)  /* Channel 1 Request Time-Out Register	*/
-#define MX1_BUCR1	__REG(0x002090D8)  /* Channel 1 Bus Utilization Control Register	*/
-
-/* Channel 2 */
-
-#define MX1_SAR2	__REG(0x00209100)  /* Channel 2 Source Address Register */
-#define MX1_DAR2	__REG(0x00209104)  /* Channel 2 Destination Address Register	*/
-#define MX1_CNTR2	__REG(0x00209108)  /* Channel 2 Count Register		*/
-#define MX1_CCR2	__REG(0x0020910C)  /* Channel 2 Control Register	*/
-#define MX1_RSSR2	__REG(0x00209110)  /* Channel 2 Request Source Select Register	*/
-#define MX1_BLR2	__REG(0x00209114)  /* Channel 2 Burst Length  Register	*/
-#define MX1_RTOR2	__REG(0x00209118)  /* Channel 2 Request Time-Out Register	*/
-#define MX1_BUCR2	__REG(0x00209118)  /* Channel 2 Bus Utilization Control Register	*/
-
-/* Channel 3 */
-
-#define MX1_SAR3	__REG(0x00209140)  /* Channel 3 Source Address Register */
-#define MX1_DAR3	__REG(0x00209144)  /* Channel 3 Destination Address Register	*/
-#define MX1_CNTR3	__REG(0x00209148)  /* Channel 3 Count Register		*/
-#define MX1_CCR3	__REG(0x0020914C)  /* Channel 3 Control Register	*/
-#define MX1_RSSR3	__REG(0x00209150)  /* Channel 3 Request Source Select Register	*/
-#define MX1_BLR3	__REG(0x00209154)  /* Channel 3 Burst Length  Register	*/
-#define MX1_RTOR3	__REG(0x00209158)  /* Channel 3 Request Time-Out Register	*/
-#define MX1_BUCR3	__REG(0x00209158)  /* Channel 3 Bus Utilization Control Register	*/
-
-/* Channel 4 */
-
-#define MX1_SAR4	__REG(0x00209180)  /* Channel 4 Source Address Register */
-#define MX1_DAR4	__REG(0x00209184)  /* Channel 4 Destination Address Register	*/
-#define MX1_CNTR4	__REG(0x00209188)  /* Channel 4 Count Register		*/
-#define MX1_CCR4	__REG(0x0020918C)  /* Channel 4 Control Register	*/
-#define MX1_RSSR4	__REG(0x00209190)  /* Channel 4 Request Source Select Register	*/
-#define MX1_BLR4	__REG(0x00209194)  /* Channel 4 Burst Length  Register	*/
-#define MX1_RTOR4	__REG(0x00209198)  /* Channel 4 Request Time-Out Register	*/
-#define MX1_BUCR4	__REG(0x00209198)  /* Channel 4 Bus Utilization Control Register	*/
-
-/* Channel 5 */
-
-#define MX1_SAR5	__REG(0x002091C0)  /* Channel 5 Source Address Register */
-#define MX1_DAR5	__REG(0x002091C4)  /* Channel 5 Destination Address Register	*/
-#define MX1_CNTR5	__REG(0x002091C8)  /* Channel 5 Count Register		*/
-#define MX1_CCR5	__REG(0x002091CC)  /* Channel 5 Control Register	*/
-#define MX1_RSSR5	__REG(0x002091D0)  /* Channel 5 Request Source Select Register	*/
-#define MX1_BLR5	__REG(0x002091D4)  /* Channel 5 Burst Length  Register	*/
-#define MX1_RTOR5	__REG(0x002091D8)  /* Channel 5 Request Time-Out Register	*/
-#define MX1_BUCR5	__REG(0x002091D8)  /* Channel 5 Bus Utilization Control Register	*/
-
-/* Channel 6 */
-
-#define MX1_SAR6	__REG(0x00209200)  /* Channel 6 Source Address Register */
-#define MX1_DAR6	__REG(0x00209204)  /* Channel 6 Destination Address Register	*/
-#define MX1_CNTR6	__REG(0x00209208)  /* Channel 6 Count Register		*/
-#define MX1_CCR6	__REG(0x0020920C)  /* Channel 6 Control Register	*/
-#define MX1_RSSR6	__REG(0x00209210)  /* Channel 6 Request Source Select Register	*/
-#define MX1_BLR6	__REG(0x00209214)  /* Channel 6 Burst Length  Register	*/
-#define MX1_RTOR6	__REG(0x00209218)  /* Channel 6 Request Time-Out Register	*/
-#define MX1_BUCR6	__REG(0x00209218)  /* Channel 6 Bus Utilization Control Register	*/
-
-/* Channel 7 */
-
-#define MX1_SAR7	__REG(0x00209240)  /* Channel 7 Source Address Register */
-#define MX1_DAR7	__REG(0x00209244)  /* Channel 7 Destination Address Register	*/
-#define MX1_CNTR7	__REG(0x00209248)  /* Channel 7 Count Register		*/
-#define MX1_CCR7	__REG(0x0020924C)  /* Channel 7 Control Register	*/
-#define MX1_RSSR7	__REG(0x00209250)  /* Channel 7 Request Source Select Register	*/
-#define MX1_BLR7	__REG(0x00209254)  /* Channel 7 Burst Length  Register	*/
-#define MX1_RTOR7	__REG(0x00209258)  /* Channel 7 Request Time-Out Register	*/
-#define MX1_BUCR7	__REG(0x00209258)  /* Channel 7 Bus Utilization Control Register	*/
-
-/* Channel 8 */
-
-#define MX1_SAR8	__REG(0x00209280)  /* Channel 8 Source Address Register */
-#define MX1_DAR8	__REG(0x00209284)  /* Channel 8 Destination Address Register	*/
-#define MX1_CNTR8	__REG(0x00209288)  /* Channel 8 Count Register		*/
-#define MX1_CCR8	__REG(0x0020928C)  /* Channel 8 Control Register	*/
-#define MX1_RSSR8	__REG(0x00209290)  /* Channel 8 Request Source Select Register	*/
-#define MX1_BLR8	__REG(0x00209294)  /* Channel 8 Burst Length  Register	*/
-#define MX1_RTOR8	__REG(0x00209298)  /* Channel 8 Request Time-Out Register	*/
-#define MX1_BUCR8	__REG(0x00209298)  /* Channel 8 Bus Utilization Control Register	*/
-
-/* Channel 9 */
-
-#define MX1_SAR9	__REG(0x002092C0)  /* Channel 9 Source Address Register */
-#define MX1_DAR9	__REG(0x002092C4)  /* Channel 9 Destination Address Register	*/
-#define MX1_CNTR9	__REG(0x002092C8)  /* Channel 9 Count Register		*/
-#define MX1_CCR9	__REG(0x002092CC)  /* Channel 9 Control Register	*/
-#define MX1_RSSR9	__REG(0x002092D0)  /* Channel 9 Request Source Select Register	*/
-#define MX1_BLR9	__REG(0x002092D4)  /* Channel 9 Burst Length  Register	*/
-#define MX1_RTOR9	__REG(0x002092D8)  /* Channel 9 Request Time-Out Register	*/
-#define MX1_BUCR9	__REG(0x002092D8)  /* Channel 9 Bus Utilization Control Register	*/
-
-/* Channel 10 */
-
-#define MX1_SAR10	__REG(0x00209300)  /* Channel 10 Source Address Register */
-#define MX1_DAR10	__REG(0x00209304)  /* Channel 10 Destination Address Register	*/
-#define MX1_CNTR10	__REG(0x00209308)  /* Channel 10 Count Register			*/
-#define MX1_CCR10	__REG(0x0020930C)  /* Channel 10 Control Register	*/
-#define MX1_RSSR10	__REG(0x00209310)  /* Channel 10 Request Source Select Register		*/
-#define MX1_BLR10	__REG(0x00209314)  /* Channel 10 Burst Length  Register		*/
-#define MX1_RTOR10	__REG(0x00209318)  /* Channel 10 Request Time-Out Register	*/
-#define MX1_BUCR10	__REG(0x00209318)  /* Channel 10 Bus Utilization Control Register	*/
-
-#define MX1_TCR		__REG(0x00209340)  /* Test Control Register		*/
-#define MX1_TFIFOAR	__REG(0x00209344)  /* Test FIFO A  Register		*/
-#define MX1_TDRR	__REG(0x00209348)  /* Test DMA Request Register		*/
-#define MX1_TDIPR	__REG(0x0020934C)  /* Test DMA In Progress Register	*/
-#define MX1_TFIFOBR	__REG(0x00209350)  /* Test FIFO B Register		*/
-
-/*
- *	MX1 SIM registers
- */
-
-#define MX1_PORT_CNTL	__REG(0x00211000)  /* Port Control Register		*/
-#define MX1_CNTL	__REG(0x00211004)  /* Control Register			*/
-#define MX1_RCV_THRESHOLD __REG(0x00211008)/* Receive Threshold	 Register	*/
-#define MX1_ENABLE	__REG(0x0021100C)  /* Transmit/Receive Enable Register	*/
-#define MX1_XMT_STATUS	__REG(0x00211010)  /* Transmit Status  Register		*/
-#define MX1_RCV_STATUS	__REG(0x00211014)  /* Receive Status  Register		*/
-#define MX1_SIM_INT_MASK	__REG(0x00211018)  /* Interrupt Mask Register		*/
-#define MX1_XMT_BUF	__REG(0x0021101C)  /* Port Transmit Buffer Register	*/
-#define MX1_RCV_BUF	__REG(0x00211020)  /* Receive Buffer Register		*/
-#define MX1_PORT_DETECT __REG(0x00211024)  /* Detect Register			*/
-#define MX1_XMT_THRESHOLD __REG(0x00211028)/* Transmit Threshold Register	*/
-#define MX1_GUARD_CNTL	__REG(0x0021102C)  /* Transmit Guard Control  Register	*/
-#define MX1_OD_CONFIG	__REG(0x00211030)  /* Open-Drain Configuration Control Register */
-#define MX1_RESET_CNTL	__REG(0x00211034)  /* Reset  Control Register		*/
-#define MX1_CHAR_WAIT	__REG(0x00211038)  /* Charactor Wait Timer Register	*/
-#define MX1_GPCNT	__REG(0x0021103C)  /* General Purpose Counter  Register */
-#define MX1_DIVISOR	__REG(0x00211040)  /* Divisor Register			*/
-
-/*
- *	MX1 USBD registers
- */
-
-#define MX1_USB_FRAME	__REG(0x00212000)  /* USB Frame Number and Match Register	*/
-#define MX1_USB_SPEC	__REG(0x00212004)  /* USB Spec & Release Number Register	*/
-#define MX1_USB_STAT	__REG(0x00212008)  /* USB Status Register		*/
-#define MX1_USB_CTRL	__REG(0x0021200C)  /* USB Control Register		*/
-#define MX1_USB_DADR	__REG(0x00212010)  /* USB Descriptor RAM Address Register	*/
-#define MX1_USB_DDAT	__REG(0x00212014)  /* USB Descriptor RAM/Endpoint buffer Data  Register */
-#define MX1_USB_INTR	__REG(0x00212018)  /* USB Interrupt Status Register	*/
-#define MX1_USB_MASK	__REG(0x0021201C)  /* USB Interrupt Mask Register	*/
-#define MX1_USB_ENAB	__REG(0x00212024)  /* USB Enable Register		*/
-
-/* Endpoint 0  */
-#define MX1_USB_EP0_STAT __REG(0x00212030) /* Endpoint 0 Status/Control Register	*/
-#define MX1_USB_EP0_INTR __REG(0x00212034) /* Endpoint 0 Interrupt Status  Register	*/
-#define MX1_USB_EP0_MASK __REG(0x00212038) /* Endpoint 0 Interrupt Mask	 Register	*/
-#define MX1_USB_EP0_FDAT __REG(0x0021203C) /* Endpoint 0 FIFO Data Register	*/
-#define MX1_USB_EP0_FSTAT __REG(0x00212040) /* Endpoint 0 FIFO Status Register	*/
-#define MX1_USB_EP0_FCTRL __REG(0x00212044) /* Endpoint 0 FIFO Control Register */
-#define MX1_USB_EP0_LRFP __REG(0x00212048) /* Endpoint 0 Last Read Frame Pointer Register	*/
-#define MX1_USB_EP0_LWFP __REG(0x0021204C) /* Endpoint 0 Last Write Frame Pointer Register	*/
-#define MX1_USB_EP0_FALRM __REG(0x00212050) /* Endpoint 0 FIFO Alarm  Register	*/
-#define MX1_USB_EP0_FRDP __REG(0x00212054) /* Endpoint 0 FIFO Read Pointer Register	*/
-#define MX1_USB_EP0_FWRP __REG(0x00212058) /* Endpoint 0 FIFO Write Pointer Register	*/
-
-/* Endpoint 1  */
-#define MX1_USB_EP1_STAT __REG(0x00212060) /* Endpoint 1 Status/Control Register	*/
-#define MX1_USB_EP1_INTR __REG(0x00212064) /* Endpoint 1 Interrupt Status  Register	*/
-#define MX1_USB_EP1_MASK __REG(0x00212068) /* Endpoint 1 Interrupt Mask	 Register	*/
-#define MX1_USB_EP1_FDAT __REG(0x0021206C) /* Endpoint 1 FIFO Data Register	*/
-#define MX1_USB_EP1_FSTAT __REG(0x00212070) /* Endpoint 1 FIFO Status Register	*/
-#define MX1_USB_EP1_FCTRL __REG(0x00212074) /* Endpoint 1 FIFO Control Register */
-#define MX1_USB_EP1_LRFP __REG(0x00212078) /* Endpoint 1 Last Read Frame Pointer Register	*/
-#define MX1_USB_EP1_LWFP __REG(0x0021207C) /* Endpoint 1 Last Write Frame Pointer Register	*/
-#define MX1_USB_EP1_FALRM __REG(0x00212080) /* Endpoint 1 FIFO Alarm  Register	*/
-#define MX1_USB_EP1_FRDP __REG(0x00212084) /* Endpoint 1 FIFO Read Pointer Register	*/
-#define MX1_USB_EP1_FWRP __REG(0x00212088) /* Endpoint 1 FIFO Write Pointer Register	*/
-
-/* Endpoint 2  */
-#define MX1_USB_EP2_STAT __REG(0x00212090) /* Endpoint 2 Status/Control Register	*/
-#define MX1_USB_EP2_INTR __REG(0x00212094) /* Endpoint 2 Interrupt Status  Register	*/
-#define MX1_USB_EP2_MASK __REG(0x00212098) /* Endpoint 2 Interrupt Mask	 Register	*/
-#define MX1_USB_EP2_FDAT __REG(0x0021209C) /* Endpoint 2 FIFO Data Register	*/
-#define MX1_USB_EP2_FSTAT __REG(0x002120A0) /* Endpoint 2 FIFO Status Register	*/
-#define MX1_USB_EP2_FCTRL __REG(0x002120A4) /* Endpoint 2 FIFO Control Register */
-#define MX1_USB_EP2_LRFP __REG(0x002120A8) /* Endpoint 2 Last Read Frame Pointer Register	*/
-#define MX1_USB_EP2_LWFP __REG(0x002120AC) /* Endpoint 2 Last Write Frame Pointer Register	*/
-#define MX1_USB_EP2_FALRM __REG(0x002120B0) /* Endpoint 2 FIFO Alarm  Register	*/
-#define MX1_USB_EP2_FRDP __REG(0x002120B4) /* Endpoint 2 FIFO Read Pointer Register	*/
-#define MX1_USB_EP2_FWRP __REG(0x002120B8) /* Endpoint 2 FIFO Write Pointer Register	*/
-
-/* Endpoint 3  */
-#define MX1_USB_EP3_STAT __REG(0x002120C0) /* Endpoint 3 Status/Control Register	*/
-#define MX1_USB_EP3_INTR __REG(0x002120C4) /* Endpoint 3 Interrupt Status  Register	*/
-#define MX1_USB_EP3_MASK __REG(0x002120C8) /* Endpoint 3 Interrupt Mask	 Register	*/
-#define MX1_USB_EP3_FDAT __REG(0x002120CC) /* Endpoint 3 FIFO Data Register	*/
-#define MX1_USB_EP3_FSTAT __REG(0x002120D0) /* Endpoint 3 FIFO Status Register	*/
-#define MX1_USB_EP3_FCTRL __REG(0x002120D4) /* Endpoint 3 FIFO Control Register */
-#define MX1_USB_EP3_LRFP __REG(0x002120D8) /* Endpoint 3 Last Read Frame Pointer Register	*/
-#define MX1_USB_EP3_LWFP __REG(0x002120DC) /* Endpoint 3 Last Write Frame Pointer Register	*/
-#define MX1_USB_EP3_FALRM __REG(0x002120E0) /* Endpoint 3 FIFO Alarm  Register	*/
-#define MX1_USB_EP3_FRDP __REG(0x002120E4) /* Endpoint 3 FIFO Read Pointer Register	*/
-#define MX1_USB_EP3_FWRP __REG(0x002120E8) /* Endpoint 3 FIFO Write Pointer Register	*/
-
-/* Endpoint 4  */
-#define MX1_USB_EP4_STAT __REG(0x002120F0) /* Endpoint 4 Status/Control Register	*/
-#define MX1_USB_EP4_INTR __REG(0x002120F4) /* Endpoint 4 Interrupt Status  Register	*/
-#define MX1_USB_EP4_MASK __REG(0x002120F8) /* Endpoint 4 Interrupt Mask	 Register	*/
-#define MX1_USB_EP4_FDAT __REG(0x002120FC) /* Endpoint 4 FIFO Data Register	*/
-#define MX1_USB_EP4_FSTAT __REG(0x00212100) /* Endpoint 4 FIFO Status Register	*/
-#define MX1_USB_EP4_FCTRL __REG(0x00212104) /* Endpoint 4 FIFO Control Register */
-#define MX1_USB_EP4_LRFP __REG(0x00212108) /* Endpoint 4 Last Read Frame Pointer Register	*/
-#define MX1_USB_EP4_LWFP __REG(0x0021210C) /* Endpoint 4 Last Write Frame Pointer Register	*/
-#define MX1_USB_EP4_FALRM __REG(0x00212110) /* Endpoint 4 FIFO Alarm  Register	*/
-#define MX1_USB_EP4_FRDP __REG(0x00212114) /* Endpoint 4 FIFO Read Pointer Register	*/
-#define MX1_USB_EP4_FWRP __REG(0x00212118) /* Endpoint 4 FIFO Write Pointer Register	*/
-
-/* Endpoint 5  */
-#define MX1_USB_EP5_STAT __REG(0x00212120) /* Endpoint 5 Status/Control Register	*/
-#define MX1_USB_EP5_INTR __REG(0x00212124) /* Endpoint 5 Interrupt Status  Register	*/
-#define MX1_USB_EP5_MASK __REG(0x00212128) /* Endpoint 5 Interrupt Mask	 Register	*/
-#define MX1_USB_EP5_FDAT __REG(0x0021212C) /* Endpoint 5 FIFO Data Register	*/
-#define MX1_USB_EP5_FSTAT __REG(0x00212130) /* Endpoint 5 FIFO Status Register	*/
-#define MX1_USB_EP5_FCTRL __REG(0x00212134) /* Endpoint 5 FIFO Control Register */
-#define MX1_USB_EP5_LRFP __REG(0x00212138) /* Endpoint 5 Last Read Frame Pointer Register	*/
-#define MX1_USB_EP5_LWFP __REG(0x0021213C) /* Endpoint 5 Last Write Frame Pointer Register	*/
-#define MX1_USB_EP5_FALRM __REG(0x00212140) /* Endpoint 5 FIFO Alarm  Register	*/
-#define MX1_USB_EP5_FRDP __REG(0x00212144) /* Endpoint 5 FIFO Read Pointer Register	*/
-#define MX1_USB_EP5_FWRP __REG(0x00212148) /* Endpoint 5 FIFO Write Pointer Register	*/
-
-/*
- *	MX1 SPI 1 registers
- */
-#define MX1_RXDATAREG1	__REG(0x00213000)  /* SPI 1 Rx Data Register		*/
-#define MX1_TXDATAREG1	__REG(0x00213004)  /* SPI 1 Tx Data Register		*/
-#define MX1_CONTROLREG1 __REG(0x00213008)  /* SPI 1 Control Register		*/
-#define MX1_INTREG1	__REG(0x0021300C)  /* SPI 1 Interrupt Control/Status Register	*/
-#define MX1_TESTREG1	__REG(0x00213010)  /* SPI 1 Test Register		*/
-#define MX1_PERIODREG1	__REG(0x00213014)  /* SPI 1 Sample Period Control Register	*/
-#define MX1_DMAREG1	__REG(0x00213018)  /* SPI 1 DMA Control	 Register	*/
-#define MX1_RESETREG1	__REG(0x00213018)  /* SPI 1 Soft Reset Register		*/
-
-/*
- *	MX1 MMC/SDHC registers
- */
-#define MX1_STR_STP_CLK __REG(0x00214000)  /* MMC/SD Clock Control Register	*/
-#define MX1_STATUS	__REG(0x00214004)  /* MMC/SD Status Register		*/
-#define MX1_CLK_RATE	__REG(0x00214008)  /* MMC/SD Clock Rate Register	*/
-#define MX1_CMD_DAT_CONT __REG(0x0021400C)  /* MMC/SD Command & Data Control Register	*/
-#define MX1_RES_TO	__REG(0x00214010)  /* MMC/SD Response Time Out Register */
-#define MX1_READ_TO	__REG(0x00214014)  /* MMC/SD Read Time Out Register	*/
-#define MX1_BLK_LEN	__REG(0x00214018)  /* MMC/SD Block Length Register	*/
-#define MX1_NOB		__REG(0x0021401C)  /* MMC/SD Number of Block Register	*/
-#define MX1_REV_NO	__REG(0x00214020)  /* MMC/SD Revision Number Register	*/
-#define MX1_MMC_INT_MASK	__REG(0x00214024)  /* MMC/SD Interrupt Mask Register	*/
-#define MX1_CMD		__REG(0x00214028)  /* MMC/SD Command Number Register	*/
-#define MX1_ARGH	__REG(0x0021402C)  /* MMC/SD Higher Argument Register	*/
-#define MX1_ARGL	__REG(0x00214030)  /* MMC/SD Lower Argument Register	*/
-#define MX1_RES_FIFO	__REG(0x00214034)  /* MMC/SD Response FIFO Register	*/
-#define MX1_BUFFER_ACCESS __REG(0x00214038)  /* MMC/SD Buffer Access Register	*/
-
-/*
- *	MX1 ASP registers
- */
-#define MX1_ASP_PADFIFO __REG(0x00215000)  /* Pen Sample FIFO			*/
-#define MX1_ASP_VADFIFO __REG(0x00215004)  /* Voice ADC Register		*/
-#define MX1_ASP_VDAFIFO __REG(0x00215008)  /* Voice DAC Register		*/
-#define MX1_ASP_VADCOEF __REG(0x0021500C)  /* Voice ADC FIR Coefficients RAM	*/
-#define MX1_ASP_ACNTLCR __REG(0x00215010)  /* Control Register			*/
-#define MX1_ASP_PSMPLRG __REG(0x00215014)  /* Pen A/D Sample Rate Control Register	*/
-#define MX1_ASP_ICNTLR	__REG(0x00215018)  /* Interrupt Control Register	*/
-#define MX1_ASP_ISTATR	__REG(0x0021501C)  /* Interrupt/Error Status Register	*/
-#define MX1_ASP_VADGAIN __REG(0x00215020)  /* Voice ADC Control Register	*/
-#define MX1_ASP_VDAGAIN __REG(0x00215024)  /* Voice DAC Control Register	*/
-#define MX1_ASP_VDACOEF __REG(0x00215028)  /* Voice DAC FIR Coefficients RAM	*/
-#define MX1_ASP_CLKDIV	__REG(0x0021502C)  /* Clock Divide Register		*/
-#define MX1_ASP_CMPCNTL __REG(0x0021502C)  /* Compare Control Register		*/
-
-/*
- *	MX1 BTA registers
- */
-
-/*
- *	MX1 I2C registers
- */
-#define MX1_IADR	__REG(0x00217000)  /* I2C Address Register		*/
-#define MX1_IFDR	__REG(0x00217004)  /* I2C Frequency Divider Register	*/
-#define MX1_I2CR	__REG(0x00217008)  /* I2C Control Register		*/
-#define MX1_I2CSR	__REG(0x0021700C)  /* I2C Status Register		*/
-#define MX1_I2DR	__REG(0x00217010)  /* I2C Data I/O Register		*/
-
-/*
- *	MX1 SSI registers
- */
-#define MX1_STX		__REG(0x00218000)  /* SSI Transmit Data Register	*/
-#define MX1_SRX		__REG(0x00218004)  /* SSI Receive Data Register		*/
-#define MX1_SCSR	__REG(0x00218008)  /* SSI Control/Status Register	*/
-#define MX1_STCR	__REG(0x0021800C)  /* SSI Transmit Configuration Register	*/
-#define MX1_SRCR	__REG(0x00218010)  /* SSI Recieve Configuration Register	*/
-#define MX1_STCCR	__REG(0x00218014)  /* SSI Transmit Clock Control Register	*/
-#define MX1_SRCCR	__REG(0x00218018)  /* SSI Receive Clock Control Register	*/
-#define MX1_STSR	__REG(0x0021801C)  /* SSI Time Slot Register		*/
-#define MX1_SFCSR	__REG(0x00218020)  /* SSI FIFO Control/Status Register	*/
-#define MX1_SOR		__REG(0x00218024)  /* SSI Option Register		*/
-
-/*
- *	MX1 SPI 2 registers
- */
-#define MX1_RXDATAREG2	__REG(0x00219000)  /* SPI 2 Rx Data Register		*/
-#define MX1_TXDATAREG2	__REG(0x00219004)  /* SPI 2 Tx Data Register		*/
-#define MX1_CONTROLREG2 __REG(0x00219008)  /* SPI 2 Control Register		*/
-#define MX1_INTREG2	__REG(0x0021900C)  /* SPI 2 Interrupt Control/Status Register	*/
-#define MX1_TESTREG2	__REG(0x00219010)  /* SPI 2 Test Register		*/
-#define MX1_PERIODREG2	__REG(0x00219014)  /* SPI 2 Sample Period Control Register	*/
-#define MX1_DMAREG2	__REG(0x00219018)  /* SPI 2 DMA Control	 Register	*/
-#define MX1_RESETREG2	__REG(0x00219018)  /* SPI 2 Soft Reset Register		*/
-
-/*
- *	MX1 MSHC registers
- */
-#define MX1_MSCMD	__REG(0x0021A000)  /* Memory Stick Command Register	*/
-#define MX1_MSCS	__REG(0x0021A002)  /* Memory Stick Control/Status Register	*/
-#define MX1_MSTDATA	__REG(0x0021A004)  /* Memory Stick Transmit FIFO Data Register	*/
-#define MX1_MSRDATA	__REG(0x0021A004)  /* Memory Stick Recieve FIFO Data Register	*/
-#define MX1_MSICS	__REG(0x0021A006)  /* Memory Stick Interrupt Control/Status Register	*/
-#define MX1_MSPPCD	__REG(0x0021A008)  /* Memory Stick Parallel Port Control/Data Register	*/
-#define MX1_MSC2	__REG(0x0021A00A)  /* Memory Stick Control 2 Register	*/
-#define MX1_MSACD	__REG(0x0021A00C)  /* Memory Stick Auto Command Register	*/
-#define MX1_MSFAECS	__REG(0x0021A00E)  /* Memory Stick FIFO Access Error Control/Status Register	*/
-#define MX1_MSCLKD	__REG(0x0021A010)  /* Memory Stick Serial Clock divider Register	*/
-#define MX1_MSDRQC	__REG(0x0021A012)  /* Memory Stick DMA Request Control Register */
-
-/*
- *	MX1 PLLCLK registers
- */
-#define MX1_CSCR	__REG(0x0021B000)  /* Clock Source Control Register	*/
-#define MX1_MPCTL0	__REG(0x0021B004)  /* MCU PLL Control Register 0	*/
-#define MX1_MPCTL1	__REG(0x0021B008)  /* MCU PLL & System Clock Control Register 1 */
-#define MX1_UPCTL0	__REG(0x0021B00C)  /* USB PLL Control Register 0	*/
-#define MX1_UPCTL1	__REG(0x0021B010)  /* USB PLL Control Register 1	*/
-#define MX1_PCDR	__REG(0x0021B020)  /* Peripheral Clock Divider Register */
-
-/*
- *	MX1 RESET registers
- */
-#define MX1_RSR		__REG(0x0021B800)  /* Reset Source Register		*/
-
-/*
- *	MX1 SYS CTRL registers
- */
-#define MX1_SIDR	__REG(0x0021B804)  /* Silicon ID Register		*/
-#define MX1_FMCR	__REG(0x0021B808)  /* Function MultiPlexing Control Register	*/
-#define MX1_GPCR	__REG(0x0021B80C)  /* Global Peripheral Control Register	*/
-
-/*
- *	MX1 GPIO registers
- */
-
-/* Port A */
-#define MX1_DDIR_A	__REG(0x0021C000)  /* Port A Data Direction Register	*/
-#define MX1_OCR1_A	__REG(0x0021C004)  /* Port A Output Configuration Register 1	*/
-#define MX1_OCR2_A	__REG(0x0021C008)  /* Port A Output Configuration Register 2	*/
-#define MX1_ICONFA1_A	__REG(0x0021C00C)  /* Port A Input Configuration Register A1	*/
-#define MX1_ICONFA2_A	__REG(0x0021C010)  /* Port A Input Configuration Register A2	*/
-#define MX1_ICONFB1_A	__REG(0x0021C014)  /* Port A Input Configuration Register B1	*/
-#define MX1_ICONFB2_A	__REG(0x0021C018)  /* Port A Input Configuration Register B2	*/
-#define MX1_DR_A	__REG(0x0021C01C)  /* Port A Data Register		*/
-#define MX1_GIUS_A	__REG(0x0021C020)  /* Port A GPIO In Use Register	*/
-#define MX1_SSR_A	__REG(0x0021C024)  /* Port A Sample Status Register	*/
-#define MX1_ICR1_A	__REG(0x0021C028)  /* Port A Interrupt Configuration Register 1 */
-#define MX1_ICR2_A	__REG(0x0021C02C)  /* Port A Interrupt Configuration Register 2 */
-#define MX1_IMR_A	__REG(0x0021C030)  /* Port A Interrupt Mask Register	*/
-#define MX1_ISR_A	__REG(0x0021C034)  /* Port A Interrupt Status Register	*/
-#define MX1_GPR_A	__REG(0x0021C038)  /* Port A General Purpose Register	*/
-#define MX1_SWR_A	__REG(0x0021C03C)  /* Port A Software Reset Register	*/
-#define MX1_PUEN_A	__REG(0x0021C040)  /* Port A Pull Up Enable Register	*/
-
-/* Port B */
-#define MX1_DDIR_B	__REG(0x0021C100)  /* Port B Data Direction Register	*/
-#define MX1_OCR1_B	__REG(0x0021C104)  /* Port B Output Configuration Register 1	*/
-#define MX1_OCR2_B	__REG(0x0021C108)  /* Port B Output Configuration Register 2	*/
-#define MX1_ICONFA1_B	__REG(0x0021C10C)  /* Port B Input Configuration Register A1	*/
-#define MX1_ICONFA2_B	__REG(0x0021C110)  /* Port B Input Configuration Register A2	*/
-#define MX1_ICONFB1_B	__REG(0x0021C114)  /* Port B Input Configuration Register B1	*/
-#define MX1_ICONFB2_B	__REG(0x0021C118)  /* Port B Input Configuration Register B2	*/
-#define MX1_DR_B	__REG(0x0021C11C)  /* Port B Data Register		*/
-#define MX1_GIUS_B	__REG(0x0021C120)  /* Port B GPIO In Use Register	*/
-#define MX1_SSR_B	__REG(0x0021C124)  /* Port B Sample Status Register	*/
-#define MX1_ICR1_B	__REG(0x0021C128)  /* Port B Interrupt Configuration Register 1 */
-#define MX1_ICR2_B	__REG(0x0021C12C)  /* Port B Interrupt Configuration Register 2 */
-#define MX1_IMR_B	__REG(0x0021C130)  /* Port B Interrupt Mask Register	*/
-#define MX1_ISR_B	__REG(0x0021C134)  /* Port B Interrupt Status Register	*/
-#define MX1_GPR_B	__REG(0x0021C138)  /* Port B General Purpose Register	*/
-#define MX1_SWR_B	__REG(0x0021C13C)  /* Port B Software Reset Register	*/
-#define MX1_PUEN_B	__REG(0x0021C140)  /* Port B Pull Up Enable Register	*/
-
-/* Port C */
-#define MX1_DDIR_C	__REG(0x0021C200)  /* Port C Data Direction Register	*/
-#define MX1_OCR1_C	__REG(0x0021C204)  /* Port C Output Configuration Register 1	*/
-#define MX1_OCR2_C	__REG(0x0021C208)  /* Port C Output Configuration Register 2	*/
-#define MX1_ICONFA1_C	__REG(0x0021C20C)  /* Port C Input Configuration Register A1	*/
-#define MX1_ICONFA2_C	__REG(0x0021C210)  /* Port C Input Configuration Register A2	*/
-#define MX1_ICONFB1_C	__REG(0x0021C214)  /* Port C Input Configuration Register B1	*/
-#define MX1_ICONFB2_C	__REG(0x0021C218)  /* Port C Input Configuration Register B2	*/
-#define MX1_DR_C	__REG(0x0021C21C)  /* Port C Data Register		*/
-#define MX1_GIUS_C	__REG(0x0021C220)  /* Port C GPIO In Use Register	*/
-#define MX1_SSR_C	__REG(0x0021C224)  /* Port C Sample Status Register	*/
-#define MX1_ICR1_C	__REG(0x0021C228)  /* Port C Interrupt Configuration Register 1 */
-#define MX1_ICR2_C	__REG(0x0021C22C)  /* Port C Interrupt Configuration Register 2 */
-#define MX1_IMR_C	__REG(0x0021C230)  /* Port C Interrupt Mask Register	*/
-#define MX1_ISR_C	__REG(0x0021C234)  /* Port C Interrupt Status Register	*/
-#define MX1_GPR_C	__REG(0x0021C238)  /* Port C General Purpose Register	*/
-#define MX1_SWR_C	__REG(0x0021C23C)  /* Port C Software Reset Register	*/
-#define MX1_PUEN_C	__REG(0x0021C240)  /* Port C Pull Up Enable Register	*/
-
-/* Port D */
-#define MX1_DDIR_D	__REG(0x0021C300)  /* Port D Data Direction Register	*/
-#define MX1_OCR1_D	__REG(0x0021C304)  /* Port D Output Configuration Register 1	*/
-#define MX1_OCR2_D	__REG(0x0021C308)  /* Port D Output Configuration Register 2	*/
-#define MX1_ICONFA1_D	__REG(0x0021C30C)  /* Port D Input Configuration Register A1	*/
-#define MX1_ICONFA2_D	__REG(0x0021C310)  /* Port D Input Configuration Register A2	*/
-#define MX1_ICONFB1_D	__REG(0x0021C314)  /* Port D Input Configuration Register B1	*/
-#define MX1_ICONFB2_D	__REG(0x0021C318)  /* Port D Input Configuration Register B2	*/
-#define MX1_DR_D	__REG(0x0021C31C)  /* Port D Data Register		*/
-#define MX1_GIUS_D	__REG(0x0021C320)  /* Port D GPIO In Use Register	*/
-#define MX1_SSR_D	__REG(0x0021C324)  /* Port D Sample Status Register	*/
-#define MX1_ICR1_D	__REG(0x0021C328)  /* Port D Interrupt Configuration Register 1 */
-#define MX1_ICR2_D	__REG(0x0021C32C)  /* Port D Interrupt Configuration Register 2 */
-#define MX1_IMR_D	__REG(0x0021C330)  /* Port D Interrupt Mask Register	*/
-#define MX1_ISR_D	__REG(0x0021C334)  /* Port D Interrupt Status Register	*/
-#define MX1_GPR_D	__REG(0x0021C338)  /* Port D General Purpose Register	*/
-#define MX1_SWR_D	__REG(0x0021C33C)  /* Port D Software Reset Register	*/
-#define MX1_PUEN_D	__REG(0x0021C340)  /* Port D Pull Up Enable Register	*/
-
-/*
- *	MX1 EIM registers
- */
-#define MX1_CS0U	__REG(0x00220000)  /* Chip Select 0 Upper Control Register	*/
-#define MX1_CS0L	__REG(0x00220004)  /* Chip Select 0 Lower Control Register	*/
-#define MX1_CS1U	__REG(0x00220008)  /* Chip Select 1 Upper Control Register	*/
-#define MX1_CS1L	__REG(0x0022000C)  /* Chip Select 1 Lower Control Register	*/
-#define MX1_CS2U	__REG(0x00220010)  /* Chip Select 2 Upper Control Register	*/
-#define MX1_CS2L	__REG(0x00220014)  /* Chip Select 2 Lower Control Register	*/
-#define MX1_CS3U	__REG(0x00220018)  /* Chip Select 3 Upper Control Register	*/
-#define MX1_CS3L	__REG(0x0022001C)  /* Chip Select 3 Lower Control Register	*/
-#define MX1_CS4U	__REG(0x00220020)  /* Chip Select 4 Upper Control Register	*/
-#define MX1_CS4L	__REG(0x00220024)  /* Chip Select 4 Lower Control Register	*/
-#define MX1_CS5U	__REG(0x00220028)  /* Chip Select 5 Upper Control Register	*/
-#define MX1_CS5L	__REG(0x0022002C)  /* Chip Select 5 Lower Control Register	*/
-#define MX1_WEIM	__REG(0x00220030)  /* weim cONFIGURATION Register	*/
-
-/*
- *	MX1 SDRAMC registers
- */
-#define MX1_SDCTL0	__REG(0x00221000)  /* SDRAM 0 Control Register		*/
-#define MX1_SDCTL1	__REG(0x00221004)  /* SDRAM 1 Control Register		*/
-#define MX1_MISCELLANEOUS __REG(0x00221014)  /* Miscellaneous Register		*/
-#define MX1_SDRST	__REG(0x00221018)  /* SDRAM Reset Register		*/
-
-/*
- *	MX1 MMA registers
- */
-#define MX1_MMA_MAC_MOD __REG(0x00222000)  /* MMA MAC Module Register		*/
-#define MX1_MMA_MAC_CTRL __REG(0x00222004)  /* MMA MAC Control Register		*/
-#define MX1_MMA_MAC_MULT __REG(0x00222008)  /* MMA MAC Multiply Counter Register	*/
-#define MX1_MMA_MAC_ACCU __REG(0x0022200C)  /* MMA MAC Accumulate Counter Register	*/
-#define MX1_MMA_MAC_INTR __REG(0x00222010)  /* MMA MAC Interrupt Register	*/
-#define MX1_MMA_MAC_INTR_MASK __REG(0x00222014)	 /* MMA MAC Interrupt Mask Register	*/
-#define MX1_MMA_MAC_FIFO __REG(0x00222018)  /* MMA MAC FIFO Register		*/
-#define MX1_MMA_MAC_FIFO_STAT __REG(0x0022201C)	 /* MMA MAC FIFO Status Register	*/
-#define MX1_MMA_MAC_BURST __REG(0x00222020)  /* MMA MAC Burst Count Register	*/
-#define MX1_MMA_MAC_BITSEL __REG(0x00222024)  /* MMA MAC Bit Select Register	*/
-
-#define MX1_MMA_MAC_XBASE __REG(0x00222200)  /* MMA MAC X Base Address Register */
-#define MX1_MMA_MAC_XINDEX __REG(0x00222204)  /* MMA MAC X Index Register	*/
-#define MX1_MMA_MAC_XLENGTH __REG(0x00222208)  /* MMA MAC X Length Register	*/
-#define MX1_MMA_MAC_XMODIFY __REG(0x0022220C)  /* MMA MAC X Modify Register	*/
-#define MX1_MMA_MAC_XINCR __REG(0x00222210)  /* MMA MAC X Increment Register	*/
-#define MX1_MMA_MAC_XCOUNT __REG(0x00222214)  /* MMA MAC X Count Register	*/
-
-#define MX1_MMA_MAC_YBASE __REG(0x00222300)  /* MMA MAC Y Base Address Register */
-#define MX1_MMA_MAC_YINDEX __REG(0x00222304)  /* MMA MAC Y Index Register	*/
-#define MX1_MMA_MAC_YLENGTH __REG(0x00222308)  /* MMA MAC Y Length Register	*/
-#define MX1_MMA_MAC_YMODIFY __REG(0x0022230C)  /* MMA MAC Y Modify Register	*/
-#define MX1_MMA_MAC_YINCR __REG(0x00222310)  /* MMA MAC Y Increment Register	*/
-#define MX1_MMA_MAC_YCOUNT __REG(0x00222314)  /* MMA MAC Y Count Register	*/
-
-#define MX1_MMA_DCTCTRL __REG(0x00222400)  /* DCT/iDCT Control Register		*/
-#define MX1_MMA_DCTVERSION __REG(0x00222404)  /* DCT/iDCT Version Register	*/
-#define MX1_MMA_DCTIRQENA __REG(0x00222408)  /* DCT/iDCT IRQ Enable Register	*/
-#define MX1_MMA_DCTIRQSTAT __REG(0x0022240C)  /* DCT/iDCT IRQ Status Register	*/
-#define MX1_MMA_DCTSRCDATA __REG(0x00222410)  /* DCT/iDCT Source Data Address	*/
-#define MX1_MMA_DCTDESDATA __REG(0x00222414)  /* DCT/iDCT Destination Data Address	*/
-#define MX1_MMA_DCTXOFF __REG(0x00222418)  /* DCT/iDCT X-Offset Address		*/
-#define MX1_MMA_DCTYOFF __REG(0x0022241C)  /* DCT/iDCT Y-Offset Address		*/
-#define MX1_MMA_DCTXYCNT __REG(0x00222420)  /* DCT/iDCT XY Count		*/
-#define MX1_MMA_DCTSKIP __REG(0x00222424)  /* DCT/iDCT Skip Address		*/
-#define MX1_MMA_DCTFIFO __REG(0x00222500)  /* DCT/iDCT Data FIFO		*/
-
-/*
- *	MX1 AITC registers
- */
-#define MX1_INTCNTL	__REG(0x00223000)  /* Interrupt Control Register	*/
-#define MX1_NIMASK	__REG(0x00223004)  /* Normal Interrupt Mask Register	*/
-#define MX1_INTENNUM	__REG(0x00223008)  /* Interrupt Enable Number Register	*/
-#define MX1_INTDISNUM	__REG(0x0022300C)  /* Interrupt Disable Number Register */
-#define MX1_INTENABLEH	__REG(0x00223010)  /* Interrupt Enable Register High	*/
-#define MX1_INTENABLEL	__REG(0x00223014)  /* Interrupt Enable Register Low	*/
-#define MX1_INTTYPEH	__REG(0x00223018)  /* Interrupt Type Register High	*/
-#define MX1_INTTYPEL	__REG(0x0022301C)  /* Interrupt Type Register Low	*/
-#define MX1_NIPRIORITY7 __REG(0x00223020)  /* Normal Interrupt Priority Level Register 7*/
-#define MX1_NIPRIORITY6 __REG(0x00223024)  /* Normal Interrupt Priority Level Register 6*/
-#define MX1_NIPRIORITY5 __REG(0x00223028)  /* Normal Interrupt Priority Level Register 5*/
-#define MX1_NIPRIORITY4 __REG(0x0022302C)  /* Normal Interrupt Priority Level Register 4*/
-#define MX1_NIPRIORITY3 __REG(0x00223030)  /* Normal Interrupt Priority Level Register 3*/
-#define MX1_NIPRIORITY2 __REG(0x00223034)  /* Normal Interrupt Priority Level Register 2*/
-#define MX1_NIPRIORITY1 __REG(0x00223038)  /* Normal Interrupt Priority Level Register 1*/
-#define MX1_NIPRIORITY0 __REG(0x0022303C)  /* Normal Interrupt Priority Level Register 0*/
-#define MX1_NIVECSR	__REG(0x00223040)  /* Normal Interrupt Vector & Status Register */
-#define MX1_FIVECSR	__REG(0x00223044)  /* Fast Interrupt Vector & Status Register	*/
-#define MX1_INTSRCH	__REG(0x00223048)  /* Interrupt Source Register High	*/
-#define MX1_INTSRCL	__REG(0x0022304C)  /* Interrupt Source Register Low	*/
-#define MX1_INTFRCH	__REG(0x00223050)  /* Interrupt Force Register High	*/
-#define MX1_INTFRCL	__REG(0x00223054)  /* Interrupt Force Register Low	*/
-#define MX1_NIPNDH	__REG(0x00223058)  /* Normal Interrupt Pending Register High	*/
-#define MX1_NIPNDL	__REG(0x0022305C)  /* Normal Interrupt Pending Register Low	*/
-#define MX1_FIPNDH	__REG(0x00223060)  /* Fast Interrupt Pending Register High	*/
-#define MX1_FIPNDL	__REG(0x00223064)  /* Fast Interrupt Pending Register Low	*/
-
-/*
- *	MX1 CSI registers
- */
-#define MX1_CSICR1	__REG(0x00224000)  /* CSI Control Register 1		*/
-#define MX1_CSICR2	__REG(0x00224004)  /* CSI Control Register 2		*/
-#define MX1_CSISR	__REG(0x00224008)  /* CSI Status Register 1		*/
-#define MX1_CSISTATR	__REG(0x0022400C)  /* CSI Statistic FIFO Register 1	*/
-#define MX1_CSIRXR	__REG(0x00224010)  /* CSI RxFIFO Register 1		*/
-
-#endif	/*  __MC9328_H__ */
-
-#if 0
-/*
-	MX1 dma definition
-*/
-
-#define MAX_DMA_ADDRESS		0xffffffff
-
-/*#define MAX_DMA_CHANNELS	0 */
-
-#define MAX_DMA_CHANNELS		11
-#define MAX_DMA_2D_REGSET		2
-
-/* MX1 DMA module registers' address */
-
-#define MX1_DMA_BASE		IO_ADDRESS(0x00209000)
-#define MX1_DMA_DCR		(MX1_DMA_BASE + 0x00)		/* DMA control register */
-#define MX1_DMA_DISR		(MX1_DMA_BASE + 0x04)		/* DMA interrupt status register */
-#define MX1_DMA_DIMR		(MX1_DMA_BASE + 0x08)		/* DMA interrupt mask register */
-#define MX1_DMA_DBTOSR		(MX1_DMA_BASE + 0x0C)		/* DMA burst time-out status register */
-#define MX1_DMA_DRTOSR		(MX1_DMA_BASE + 0x10)		/* DMA request time-out status register */
-#define MX1_DMA_DSESR		(MX1_DMA_BASE + 0x14)		/* DMA transfer error status register */
-#define MX1_DMA_DBOSR		(MX1_DMA_BASE + 0x18)		/* DMA buffer overflow status register */
-#define MX1_DMA_DBTOCR		(MX1_DMA_BASE + 0x1C)		/* DMA burst time-out control register */
-#define MX1_DMA_WSRA		(MX1_DMA_BASE + 0x40)		/* W-size register A */
-#define MX1_DMA_XSRA		(MX1_DMA_BASE + 0x44)		/* X-size register A */
-#define MX1_DMA_YSRA		(MX1_DMA_BASE + 0x48)		/* Y-size register A */
-#define MX1_DMA_WSRB		(MX1_DMA_BASE + 0x4C)		/* W-size register B */
-#define MX1_DMA_XSRB		(MX1_DMA_BASE + 0x50)		/* X-size register B */
-#define MX1_DMA_YSRB		(MX1_DMA_BASE + 0x54)		/* Y-size register B */
-
-#define MX1_DMA_SAR0		(MX1_DMA_BASE + 0x80)		/* source address register 0 */
-#define MX1_DMA_DAR0		(MX1_DMA_BASE + 0x84)		/* destination address register 0 */
-#define MX1_DMA_CNTR0		(MX1_DMA_BASE + 0x88)		/* count register 0 */
-#define MX1_DMA_CCR0		(MX1_DMA_BASE + 0x8C)		/* channel control register 0 */
-#define MX1_DMA_RSSR0		(MX1_DMA_BASE + 0x90)		/* request source select register 0 */
-#define MX1_DMA_BLR0		(MX1_DMA_BASE + 0x94)		/* burst length register 0 */
-#define MX1_DMA_RTOR0		(MX1_DMA_BASE + 0x98)		/* request time-out register 0 */
-#define MX1_DMA_BUCR0		(MX1_DMA_BASE + 0x98)		/* bus utilization control register 0 */
-
-/* register set 1 to 10 are offseted by 0x40 each = 0x10 pointers away */
-
-#define DMA_REG_SET_OFS		0x10
-
-/* MX1 DMA module registers */
-#define _reg_DMA_DCR		(*((P_VU32)MX1_DMA_DCR))
-#define _reg_DMA_DISR		(*((P_VU32)MX1_DMA_DISR))
-#define _reg_DMA_DIMR		(*((P_VU32)MX1_DMA_DIMR))
-#define _reg_DMA_DBTOSR		(*((P_VU32)MX1_DMA_DBTOSR))
-#define _reg_DMA_DRTOSR		(*((P_VU32)MX1_DMA_DRTOSR))
-#define _reg_DMA_DSESR		(*((P_VU32)MX1_DMA_DSESR))
-#define _reg_DMA_DBOSR		(*((P_VU32)MX1_DMA_DBOSR))
-#define _reg_DMA_DBTOCR		(*((P_VU32)MX1_DMA_DBTOCR))
-#define _reg_DMA_WSRA		(*((P_VU32)MX1_DMA_WSRA))
-#define _reg_DMA_XSRA		(*((P_VU32)MX1_DMA_XSRA))
-#define _reg_DMA_YSRA		(*((P_VU32)MX1_DMA_YSRA))
-#define _reg_DMA_WSRB		(*((P_VU32)MX1_DMA_WSRB))
-#define _reg_DMA_XSRB		(*((P_VU32)MX1_DMA_XSRB))
-#define _reg_DMA_YSRB		(*((P_VU32)MX1_DMA_YSRB))
-#define _reg_DMA_SAR0		(*((P_VU32)MX1_DMA_SAR0))
-#define _reg_DMA_DAR0		(*((P_VU32)MX1_DMA_DAR0))
-#define _reg_DMA_CNTR0		(*((P_VU32)MX1_DMA_CNTR0))
-#define _reg_DMA_CCR0		(*((P_VU32)MX1_DMA_CCR0))
-#define _reg_DMA_RSSR0		(*((P_VU32)MX1_DMA_RSSR0))
-#define _reg_DMA_BLR0		(*((P_VU32)MX1_DMA_BLR0))
-#define _reg_DMA_RTOR0		(*((P_VU32)MX1_DMA_RTOR0))
-#define _reg_DMA_BUCR0		(*((P_VU32)MX1_DMA_BUCR0))
-
-/*  DMA error type definition */
-#define MX1_DMA_ERR_BTO		0	/* burst time-out */
-#define MX1_DMA_ERR_RTO		1	/* request time-out */
-#define MX1_DMA_ERR_TE		2	/* transfer error */
-#define MX1_DMA_ERR_BO		3	/* buffer overflow */
-
-/* Embedded SRAM */
-
-#define MX1_SRAM_BASE		0x00300000
-#define MX1_SRAM_SIZE		0x00020000
-
-#define
-
-#define MX1ADS_SFLASH_BASE	0x0C000000
-#define MX1ADS_SFLASH_SIZE	SZ_16M
-
-#define MX1ADS_IO_BASE		0x00200000
-#define MX1ADS_IO_SIZE		SZ_256K
-
-#define MX1ADS_VID_BASE		0x00300000
-#define MX1ADS_VID_SIZE		0x26000
-
-#define MX1ADS_VID_START	IO_ADDRESS(MX1ADS_VID_BASE)
-
-#define MX1_GPIO_BASE		0x0021C000	/* GPIO */
-#define MX1_EXT_UART_BASE	0x15000000	/* external UART */
-#define MX1_TMR1_BASE		0x00202000	/* Timer1 */
-#define MX1ADS_FLASH_BASE	0x0C000000	/* sync FLASH */
-#define MX1_ESRAM_BASE		0x00300000	/* embedded SRAM */
-#define MX1ADS_SDRAM_DISK_BASE	0x0B000000	/* SDRAM disk base (last 16M of SDRAM) */
-
-/* ------------------------------------------------------------------------
- *  Motorola MX1 system registers
- * ------------------------------------------------------------------------
- *
- */
-
-/*
- *  Register offests.
- *
- */
-
-#define MX1ADS_AIPI1_OFFSET		0x00000
-#define MX1ADS_WDT_OFFSET		0x01000
-#define MX1ADS_TIM1_OFFSET		0x02000
-#define MX1ADS_TIM2_OFFSET		0x03000
-#define MX1ADS_RTC_OFFSET		0x04000
-#define MX1ADS_LCDC_OFFSET		0x05000
-#define MX1ADS_UART1_OFFSET		0x06000
-#define MX1ADS_UART2_OFFSET		0x07000
-#define MX1ADS_PWM_OFFSET		0x08000
-#define MX1ADS_DMAC_OFFSET		0x09000
-#define MX1ADS_AIPI2_OFFSET		0x10000
-#define MX1ADS_SIM_OFFSET		0x11000
-#define MX1ADS_USBD_OFFSET		0x12000
-#define MX1ADS_SPI1_OFFSET		0x13000
-#define MX1ADS_MMC_OFFSET		0x14000
-#define MX1ADS_ASP_OFFSET		0x15000
-#define MX1ADS_BTA_OFFSET		0x16000
-#define MX1ADS_I2C_OFFSET		0x17000
-#define MX1ADS_SSI_OFFSET		0x18000
-#define MX1ADS_SPI2_OFFSET		0x19000
-#define MX1ADS_MSHC_OFFSET		0x1A000
-#define MX1ADS_PLL_OFFSET		0x1B000
-#define MX1ADS_GPIO_OFFSET		0x1C000
-#define MX1ADS_EIM_OFFSET		0x20000
-#define MX1ADS_SDRAMC_OFFSET		0x21000
-#define MX1ADS_MMA_OFFSET		0x22000
-#define MX1ADS_AITC_OFFSET		0x23000
-#define MX1ADS_CSI_OFFSET		0x24000
-
-/*
- *  Register BASEs, based on OFFSETs
- *
- */
-
-#define MX1ADS_AIPI1_BASE		(MX1ADS_AIPI1_OFFSET + MX1ADS_IO_BASE)
-#define MX1ADS_WDT_BASE			(MX1ADS_WDT_OFFSET + MX1ADS_IO_BASE)
-#define MX1ADS_TIM1_BASE		(MX1ADS_TIM1_OFFSET + MX1ADS_IO_BASE)
-#define MX1ADS_TIM2_BASE		(MX1ADS_TIM2_OFFSET + MX1ADS_IO_BASE)
-#define MX1ADS_RTC_BASE			(MX1ADS_RTC_OFFSET + MX1ADS_IO_BASE)
-#define MX1ADS_LCDC_BASE		(MX1ADS_LCDC_OFFSET + MX1ADS_IO_BASE)
-#define MX1ADS_UART1_BASE		(MX1ADS_UART1_OFFSET + MX1ADS_IO_BASE)
-#define MX1ADS_UART2_BASE		(MX1ADS_UART2_OFFSET + MX1ADS_IO_BASE)
-#define MX1ADS_PWM_BASE			(MX1ADS_PWM_OFFSET + MX1ADS_IO_BASE)
-#define MX1ADS_DMAC_BASE		(MX1ADS_DMAC_OFFSET + MX1ADS_IO_BASE)
-#define MX1ADS_AIPI2_BASE		(MX1ADS_AIPI2_OFFSET + MX1ADS_IO_BASE)
-#define MX1ADS_SIM_BASE			(MX1ADS_SIM_OFFSET + MX1ADS_IO_BASE)
-#define MX1ADS_USBD_BASE		(MX1ADS_USBD_OFFSET + MX1ADS_IO_BASE)
-#define MX1ADS_SPI1_BASE		(MX1ADS_SPI1_OFFSET + MX1ADS_IO_BASE)
-#define MX1ADS_MMC_BASE			(MX1ADS_MMC_OFFSET + MX1ADS_IO_BASE)
-#define MX1ADS_ASP_BASE			(MX1ADS_ASP_OFFSET + MX1ADS_IO_BASE)
-#define MX1ADS_BTA_BASE			(MX1ADS_BTA_OFFSET + MX1ADS_IO_BASE)
-#define MX1ADS_I2C_BASE			(MX1ADS_I2C_OFFSET + MX1ADS_IO_BASE)
-#define MX1ADS_SSI_BASE			(MX1ADS_SSI_OFFSET + MX1ADS_IO_BASE)
-#define MX1ADS_SPI2_BASE		(MX1ADS_SPI2_OFFSET + MX1ADS_IO_BASE)
-#define MX1ADS_MSHC_BASE		(MX1ADS_MSHC_OFFSET + MX1ADS_IO_BASE)
-#define MX1ADS_PLL_BASE			(MX1ADS_PLL_OFFSET + MX1ADS_IO_BASE)
-#define MX1ADS_GPIO_BASE		(MX1ADS_GPIO_OFFSET + MX1ADS_IO_BASE)
-#define MX1ADS_EIM_BASE			(MX1ADS_EIM_OFFSET + MX1ADS_IO_BASE)
-#define MX1ADS_SDRAMC_BASE		(MX1ADS_SDRAMC_OFFSET + MX1ADS_IO_BASE)
-#define MX1ADS_MMA_BASE			(MX1ADS_MMA_OFFSET + MX1ADS_IO_BASE)
-#define MX1ADS_AITC_BASE		(MX1ADS_AITC_OFFSET + MX1ADS_IO_BASE)
-#define MX1ADS_CSI_BASE			(MX1ADS_CSI_OFFSET + MX1ADS_IO_BASE)
-
-/*
- *  MX1 Interrupt numbers
- *
- */
-#define INT_SOFTINT			0
-#define CSI_INT				6
-#define DSPA_MAC_INT			7
-#define DSPA_INT			8
-#define COMP_INT			9
-#define MSHC_XINT			10
-#define GPIO_INT_PORTA			11
-#define GPIO_INT_PORTB			12
-#define GPIO_INT_PORTC			13
-#define LCDC_INT			14
-#define SIM_INT				15
-#define SIM_DATA_INT			16
-#define RTC_INT				17
-#define RTC_SAMINT			18
-#define UART2_MINT_PFERR		19
-#define UART2_MINT_RTS			20
-#define UART2_MINT_DTR			21
-#define UART2_MINT_UARTC		22
-#define UART2_MINT_TX			23
-#define UART2_MINT_RX			24
-#define UART1_MINT_PFERR		25
-#define UART1_MINT_RTS			26
-#define UART1_MINT_DTR			27
-#define UART1_MINT_UARTC		28
-#define UART1_MINT_TX			29
-#define UART1_MINT_RX			30
-#define VOICE_DAC_INT			31
-#define VOICE_ADC_INT			32
-#define PEN_DATA_INT			33
-#define PWM_INT				34
-#define SDHC_INT			35
-#define I2C_INT				39
-#define CSPI_INT			41
-#define SSI_TX_INT			42
-#define SSI_TX_ERR_INT			43
-#define SSI_RX_INT			44
-#define SSI_RX_ERR_INT			45
-#define TOUCH_INT			46
-#define USBD_INT0			47
-#define USBD_INT1			48
-#define USBD_INT2			49
-#define USBD_INT3			50
-#define USBD_INT4			51
-#define USBD_INT5			52
-#define USBD_INT6			53
-#define BTSYS_INT			55
-#define BTTIM_INT			56
-#define BTWUI_INT			57
-#define TIMER2_INT			58
-#define TIMER1_INT			59
-#define DMA_ERR				60
-#define DMA_INT				61
-#define GPIO_INT_PORTD			62
-
-#define MAXIRQNUM			62
-#define MAXFIQNUM			62
-#define MAXSWINUM			62
-
-#define TICKS_PER_uSEC			24
-
-/*
- *  These are useconds NOT ticks.
- *
- */
-#define mSEC_1				1000
-#define mSEC_5				(mSEC_1 * 5)
-#define mSEC_10				(mSEC_1 * 10)
-#define mSEC_25				(mSEC_1 * 25)
-#define SEC_1				(mSEC_1 * 1000)
-
-#endif
diff --git a/include/mpc824x.h b/include/mpc824x.h
index 0cd7898e139..30fc795382f 100644
--- a/include/mpc824x.h
+++ b/include/mpc824x.h
@@ -297,6 +297,7 @@
 #define PBESR		0x800000c7  /* PCI Bus Error Status Register */
 #define PBEAR		0x800000c8  /* Processor/PCI Bus Error Status Register */
 #define AMBOR		0x800000e0  /* Address Map B Options Register */
+#define PCMBCR		0x800000e1  /* PCI/Memory Buffer Configuration */
 #define MCCR1		0x800000f0  /* Memory Control Configuration Register 1 */
 #define MCCR2		0x800000f4  /* Memory Control Configuration Register 2 */
 #define MCCR3		0x800000f8  /* Memory Control Configuration Register 3 */
diff --git a/include/serial.h b/include/serial.h
new file mode 100644
index 00000000000..c206540cc65
--- /dev/null
+++ b/include/serial.h
@@ -0,0 +1,30 @@
+#ifndef __SERIAL_H__
+#define __SERIAL_H__
+
+#define NAMESIZE 16
+#define CTLRSIZE 8
+
+struct serial_device {
+	char name[NAMESIZE];
+	char ctlr[CTLRSIZE];
+
+	int  (*init) (void);
+	void (*setbrg) (void);
+	int (*getc) (void);
+	int (*tstc) (void);
+	void (*putc) (const char c);
+	void (*puts) (const char *s);
+
+	struct serial_device *next;
+};
+
+extern struct serial_device serial_smc_device;
+extern struct serial_device serial_scc_device;
+extern struct serial_device * default_serial_console (void);
+
+extern void serial_initialize(void);
+extern void serial_devices_init(void);
+extern int serial_assign(char * name);
+extern void serial_reinit_all(void);
+
+#endif