diff options
| author | David Wu | 2017-09-20 14:28:18 +0800 |
|---|---|---|
| committer | Philipp Tomsich | 2017-10-01 00:33:29 +0200 |
| commit | 2e4ce50d1aca35d13944f48a7e15d0b63e86eb38 (patch) | |
| tree | 1aca6576b715876b47853f4aab24c0f353464676 /include | |
| parent | ae3ed042ed31d1acbdd56938b45bd6c5076bebe3 (diff) | |
rockchip: clk: Add rv1108 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/rv1108-cru.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/rv1108-cru.h b/include/dt-bindings/clock/rv1108-cru.h index d2ad3bb52dc..7defc6b282c 100644 --- a/include/dt-bindings/clock/rv1108-cru.h +++ b/include/dt-bindings/clock/rv1108-cru.h @@ -39,6 +39,7 @@ #define SCLK_MAC_TX 88 #define SCLK_MACREF 89 #define SCLK_MACREF_OUT 90 +#define SCLK_SARADC 91 /* aclk gates */ @@ -67,6 +68,7 @@ #define PCLK_TIMER 270 #define PCLK_PERI 271 #define PCLK_GMAC 272 +#define PCLK_SARADC 273 /* hclk gates */ #define HCLK_I2S0_8CH 320 |