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authorTom Rini2022-10-11 09:57:08 -0400
committerTom Rini2022-10-11 09:57:08 -0400
commit300077cf8cfe6875f3f0a919ec1d0dd32c42b178 (patch)
treeb2298def2119bcb893965610b4b8575d89a4cc15 /include
parent20be7c19a2d6d4a994c40c014ae53b39bdcfacf1 (diff)
parent63c46e028c14254f28332b3bd57fc3202e26b10a (diff)
Merge tag 'xilinx-for-v2023.01-rc1-v3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2023.01-rc1 (round 3) fpga: - Create new uclass - Get rid of FPGA_DEBUG and use logging infrastructure zynq: - Enable early EEPROM decoding - Some DT updates zynqmp: - Use OCM_BANK_0 to check config loading permission - Change config object loading in SPL - Some DT updates net: - emaclite: Enable driver for RISC-V xilinx: - Fix static checker warnings - Fix GCC12 warning sdhci: - Read PD id from DT
Diffstat (limited to 'include')
-rw-r--r--include/dm/uclass-id.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index a432e438716..c2b15881ba7 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -56,6 +56,7 @@ enum uclass_id {
UCLASS_ETH, /* Ethernet device */
UCLASS_ETH_PHY, /* Ethernet PHY device */
UCLASS_FIRMWARE, /* Firmware */
+ UCLASS_FPGA, /* FPGA device */
UCLASS_FUZZING_ENGINE, /* Fuzzing engine */
UCLASS_FS_FIRMWARE_LOADER, /* Generic loader */
UCLASS_GPIO, /* Bank of general-purpose I/O pins */