diff options
| author | Andre Przywara | 2022-09-06 12:12:50 +0100 |
|---|---|---|
| committer | Andre Przywara | 2023-10-22 23:40:57 +0100 |
| commit | 452369cd0c636123321d021298b4bc35a34f4941 (patch) | |
| tree | 01f0f7a988e220f3e025a3811144a2c00f468cde /include | |
| parent | 1da48c99de18490a69c467df6c4a71701ac47fb1 (diff) | |
pinctrl: sunxi: add new D1 pinctrl support
For the first time since at least the Allwinner A10 SoCs, the D1 (and
related cores) use a new pincontroller MMIO register layout, so we
cannot use our hardcoded, fixed offsets anymore.
Ideally this would all be handled by devicetree and DM drivers, but for
the DT-less SPL we still need the legacy interfaces.
Add a new Kconfig symbol to differenciate between the two generations of
pincontrollers, and just use that to just switch some basic symbols.
The rest is already abstracted enough, so works out of the box.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Sam Edwards <CFSworks@gmail.com>
Tested-by: Sam Edwards <CFSworks@gmail.com>
Tested-by: Samuel Holland <samuel@sholland.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/sunxi_gpio.h | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h index c1fdf7ea1d7..30d8879dbd3 100644 --- a/include/sunxi_gpio.h +++ b/include/sunxi_gpio.h @@ -62,7 +62,6 @@ #define SUN50I_H6_GPIO_POW_MOD_VAL 0x348 #define SUNXI_GPIOS_PER_BANK 32 -#define SUNXI_PINCTRL_BANK_SIZE 0x24 #define SUNXI_GPIO_NEXT(__gpio) \ ((__gpio##_START) + SUNXI_GPIOS_PER_BANK) @@ -102,7 +101,6 @@ enum sunxi_gpio_number { /* GPIO pin function config */ #define SUNXI_GPIO_INPUT 0 #define SUNXI_GPIO_OUTPUT 1 -#define SUNXI_GPIO_DISABLE 7 #define SUN8I_H3_GPA_UART0 2 #define SUN8I_H3_GPA_UART2 2 @@ -171,6 +169,14 @@ enum sunxi_gpio_number { #define SUN9I_GPN_R_RSB 3 +#ifdef CONFIG_SUNXI_NEW_PINCTRL + #define SUNXI_PINCTRL_BANK_SIZE 0x30 + #define SUNXI_GPIO_DISABLE 0xf +#else + #define SUNXI_PINCTRL_BANK_SIZE 0x24 + #define SUNXI_GPIO_DISABLE 0x7 +#endif + /* GPIO pin pull-up/down config */ #define SUNXI_GPIO_PULL_DISABLE 0 #define SUNXI_GPIO_PULL_UP 1 |