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authorTom Rini2015-04-28 20:48:43 -0400
committerTom Rini2015-04-28 20:48:43 -0400
commit536266231a340c0c5e571e1012bf3f8fc835b251 (patch)
tree0b0284f73aa8f9f5608fdbc74a238efc4f8d1d23 /include
parent4842c58990ac065c2d33b71e1a7fde48f336dac2 (diff)
parente5c57eea4f4ac8c27343bde137b069ef816e69d7 (diff)
Merge branch 'master' of git://www.denx.de/git/u-boot-socfpga
Diffstat (limited to 'include')
-rw-r--r--include/configs/socfpga_common.h8
1 files changed, 7 insertions, 1 deletions
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 1ecd56f42a6..41bb52bc8c0 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -40,7 +40,7 @@
#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
-#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100)
+#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - CONFIG_SYS_SPL_MALLOC_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
@@ -292,6 +292,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
#define CONFIG_SYS_SPL_MALLOC_START CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SYS_SPL_MALLOC_SIZE (5 * 1024)
+#define CONFIG_SPL_MAX_SIZE (64 * 1024)
#define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */
#define CONFIG_CRC32_VERIFY
@@ -304,6 +305,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#define CONFIG_SPL_WATCHDOG_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
+/*
+ * Stack setup
+ */
+#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
+
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_PARTITIONS
#endif