diff options
| author | Stefan Roese | 2006-03-17 10:28:24 +0100 |
|---|---|---|
| committer | Stefan Roese | 2006-03-31 14:32:07 +0200 |
| commit | 62534beb2fdd67490c3723f22b8982e7d64fc104 (patch) | |
| tree | 3843bdce63bfeb6b9df290121b2650533397ed7f /include | |
| parent | 05d8dce9d07cf4073ea15fbc448c1ce22b6baf0f (diff) | |
Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440)
405 SDRAM: - The SDRAM parameters can now be defined in the board
config file and the 405 SDRAM controller values will
be calculated upon bootup (see PPChameleonEVB).
When those settings are not defined in the board
config file, the register setup will be as it is now,
so this implementation should not break any current
design using this code.
Thanks to Andrea Marson from DAVE for this patch.
440 DDR: - Added function sdram_tr1_set to auto calculate the
TR1 value for the DDR.
- Added ECC support (see p3p440).
Patch by Stefan Roese, 17 Mar 2006
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/PPChameleonEVB.h | 10 | ||||
| -rw-r--r-- | include/configs/p3p440.h | 12 |
2 files changed, 18 insertions, 4 deletions
diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index e1155e2e438..16e2cc6d648 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -139,8 +139,18 @@ #define CFG_I2C_RTC_ADDR 0x68 #define CFG_M41T11_BASE_YEAR 1900 +/* + * SDRAM configuration (please see cpu/ppc/sdram.[ch]) + */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ +/* SDRAM timings used in datasheet */ +#define CFG_SDRAM_CL 2 +#define CFG_SDRAM_tRP 20 +#define CFG_SDRAM_tRC 65 +#define CFG_SDRAM_tRCD 20 +#undef CFG_SDRAM_tRFC + /* * Miscellaneous configurable options */ diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h index 831d018e2d4..0662544aed2 100644 --- a/include/configs/p3p440.h +++ b/include/configs/p3p440.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2005 + * (C) Copyright 2005-2006 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> @@ -71,9 +71,10 @@ * DDR SDRAM *----------------------------------------------------------------------*/ #define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0*/ -#define CFG_SDRAM_TABLE { \ - {(256 << 20), 0x000C4001}, /* 256MB mode 3, 13x10(4) */ \ - {(64 << 20), 0x00082001}} /* 64MB mode 2, 12x9(4) */ +#define CONFIG_SDRAM_ECC /* enable ECC support */ +#define CFG_SDRAM_TABLE { \ + {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \ + {(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */ /*----------------------------------------------------------------------- * Serial Port @@ -275,6 +276,9 @@ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */ + #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ |