diff options
| author | Marek Vasut | 2018-05-08 20:32:01 +0200 |
|---|---|---|
| committer | Marek Vasut | 2019-03-09 17:59:13 +0100 |
| commit | 7544ad0303013e625c9500a4d87d4e5bfe369ee4 (patch) | |
| tree | 154edeedce6b844c79ee7aaa325f5f51d6e03b0e /include | |
| parent | dc3249b91b0c5dffdbd42426a3535bea5e14448f (diff) | |
ARM: socfpga: Disable D cache in SPL
The bootrom seems to leave the D-cache in messed up state, make sure
the SPL disables it so it can not interfere with operation.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/socfpga_arria10_socdk.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h index 58e446b60a9..0f116fbf2d9 100644 --- a/include/configs/socfpga_arria10_socdk.h +++ b/include/configs/socfpga_arria10_socdk.h @@ -15,8 +15,6 @@ /* * U-Boot general configurations */ -/* Cache options */ -#define CONFIG_SYS_DCACHE_OFF /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 |