diff options
| author | Marek Vasut | 2018-05-08 18:44:43 +0200 |
|---|---|---|
| committer | Marek Vasut | 2019-03-09 17:59:14 +0100 |
| commit | bd6363a7b77f0a5737b736f80179b6f53ef2cf7c (patch) | |
| tree | 1da56b2c374dbf3a72806923ffcd040b510ca95b /include | |
| parent | 60082d3b3ff17fc0c5ae6c1cdd176219554ed61f (diff) | |
ARM: socfpga: Fix Arria10 SPI and NAND U-Boot offset
The SPL size on Gen5 is 4*64kiB, but on A10 it is 4*256kiB.
Handle the difference.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/socfpga_common.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index f182e9e71b4..181af9b646a 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -275,12 +275,20 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /* SPL QSPI boot support */ #ifdef CONFIG_SPL_SPI_SUPPORT +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000 +#endif #endif /* SPL NAND boot support */ #ifdef CONFIG_SPL_NAND_SUPPORT +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000 +#endif #endif /* |