Merge tag 'for-master-20190201' of git://git.denx.de/u-boot-rockchip

u-boot-rockchip changes for 2019.04-rc1:
  * support for Chromebook Bob
  * full pinctrl driver using DTS properties
  * documentation improvements
  * I2S support for some Rockchip SoCs

3 files changed, 85 insertions, 0 deletions

diff --git a/include/configs/gru.h b/include/configs/gru.h
new file mode 100644
index 00000000000..a0d27b6d51a
--- /dev/null
+++ b/include/configs/gru.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Google, Inc
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+		"stdin=serial,cros-ec-keyb\0" \
+		"stdout=serial,vidconsole\0" \
+		"stderr=serial,vidconsole\0"
+
+#include <configs/rk3399_common.h>
+
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index 9a4da395f92..b977b1faa73 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -49,11 +49,16 @@
 	"kernel_addr_r=0x02080000\0" \
 	"ramdisk_addr_r=0x04000000\0"
 
+#ifndef ROCKCHIP_DEVICE_SETTINGS
+#define ROCKCHIP_DEVICE_SETTINGS
+#endif
+
 #include <config_distro_bootcmd.h>
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	ENV_MEM_LAYOUT_SETTINGS \
 	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
 	"partitions=" PARTS_DEFAULT \
+	ROCKCHIP_DEVICE_SETTINGS \
 	BOOTENV
 
 #endif
diff --git a/include/spl_gpio.h b/include/spl_gpio.h
new file mode 100644
index 00000000000..e410e62914d
--- /dev/null
+++ b/include/spl_gpio.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Simple GPIO access from SPL. This only supports a single GPIO space,
+ * typically the SoC GPIO banks.
+ *
+ * Copyright 2018 Google LLC
+ */
+
+#ifndef __SPL_GPIO_H
+#define __SPL_GPIO_H
+
+#include <asm/gpio.h>
+
+/*
+ * The functions listed here should be implemented in the SoC GPIO driver.
+ * They correspond to the normal GPIO API (asm-generic/gpio.h). The GPIO
+ * number is encoded in an unsigned int by an SoC-specific means. Pull
+ * values are also SoC-specific.
+ *
+ * This API should only be used in TPL/SPL where GPIO access is needed but
+ * driver model is not available (yet) or adds too much overhead.
+ *
+ * The caller must supply the GPIO register base since this information is
+ * often specific to a particular SoC generation. This allows the GPIO
+ * code to be fairly generic.
+ *
+ * Only a single implementation of each of these functions can be provided.
+ *
+ * The 'gpio' value can include both a bank and a GPIO number, if desired. The
+ * encoding is SoC-specific.
+ */
+
+/**
+ * spl_gpio_set_pull() - Set the pull up/down state of a GPIO
+ *
+ * @regs: Pointer to GPIO registers
+ * @gpio: GPIO to adjust (SoC-specific)
+ * @pull: Pull value (SoC-specific)
+ * @return return 0 if OK, -ve on error
+ */
+int spl_gpio_set_pull(void *regs, uint gpio, int pull);
+
+/**
+ * spl_gpio_output() - Set a GPIO as an output
+ *
+ * @regs: Pointer to GPIO registers
+ * @gpio: GPIO to adjust (SoC-specific)
+ * @value: 0 to set the output low, 1 to set it high
+ * @return return 0 if OK, -ve on error
+ */
+int spl_gpio_output(void *regs, uint gpio, int value);
+
+/**
+ * spl_gpio_input() - Set a GPIO as an input
+ *
+ * @regs: Pointer to GPIO registers
+ * @gpio: GPIO to adjust (SoC-specific)
+ * @return return 0 if OK, -ve on error
+ */
+int spl_gpio_input(void *regs, uint gpio);
+
+#endif /* __SPL_GPIO_H */