Merge tag 'ti-v2021.07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-ti

- Initial support for AM64 EVM and SK
- K3 DDR driver unification for J7 and AM64 platforms.
- Minor fixes for TI clock driver

5 files changed, 147 insertions, 31 deletions

diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index e1a5f4b1d18..47921d27b13 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -184,12 +184,6 @@ struct global_data {
 
 #ifdef CONFIG_DM
 	/**
-	 * @dm_flags: additional flags for Driver Model
-	 *
-	 * See &enum gd_dm_flags
-	 */
-	unsigned long dm_flags;
-	/**
 	 * @dm_root: root instance for Driver Model
 	 */
 	struct udevice *dm_root;
@@ -519,12 +513,6 @@ struct global_data {
 #define gd_acpi_ctx()		NULL
 #endif
 
-#if CONFIG_IS_ENABLED(DM)
-#define gd_size_cells_0()	(gd->dm_flags & GD_DM_FLG_SIZE_CELLS_0)
-#else
-#define gd_size_cells_0()	(0)
-#endif
-
 /**
  * enum gd_flags - global data flags
  *
@@ -609,18 +597,6 @@ enum gd_flags {
 	GD_FLG_SMP_READY = 0x40000,
 };
 
-/**
- * enum gd_dm_flags - global data flags for Driver Model
- *
- * See field dm_flags of &struct global_data.
- */
-enum gd_dm_flags {
-	/**
-	 * @GD_DM_FLG_SIZE_CELLS_0: Enable #size-cells=<0> translation
-	 */
-	GD_DM_FLG_SIZE_CELLS_0 = 0x00001,
-};
-
 #endif /* __ASSEMBLY__ */
 
 #endif /* __ASM_GENERIC_GBL_DATA_H */
diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h
new file mode 100644
index 00000000000..7c30e50c5f1
--- /dev/null
+++ b/include/configs/am64x_evm.h
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration header file for K3 AM642 SoC family
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ *	Keerthy <j-keerthy@ti.com>
+ */
+
+#ifndef __CONFIG_AM642_EVM_H
+#define __CONFIG_AM642_EVM_H
+
+#include <linux/sizes.h>
+#include <config_distro_bootcmd.h>
+#include <environment/ti/mmc.h>
+
+/* DDR Configuration */
+#define CONFIG_SYS_SDRAM_BASE1		0x880000000
+
+#ifdef CONFIG_SYS_K3_SPL_ATF
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"tispl.bin"
+#endif
+
+#ifndef CONFIG_CPU_V7R
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
+#if defined(CONFIG_TARGET_AM642_A53_EVM)
+#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SPL_TEXT_BASE +	\
+					CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE - 4)
+#else
+/*
+ * Maximum size in memory allocated to the SPL BSS. Keep it as tight as
+ * possible (to allow the build to go through), as this directly affects
+ * our memory footprint. The less we use for BSS the more we have available
+ * for everything else.
+ */
+#define CONFIG_SPL_BSS_MAX_SIZE		0x1000
+/*
+ * Link BSS to be within SPL in a dedicated region located near the top of
+ * the MCU SRAM, this way making it available also before relocation. Note
+ * that we are not using the actual top of the MCU SRAM as there is a memory
+ * location filled in by the boot ROM that we want to read out without any
+ * interference from the C context.
+ */
+#define CONFIG_SPL_BSS_START_ADDR	(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX -\
+					 CONFIG_SPL_BSS_MAX_SIZE)
+/* Set the stack right below the SPL BSS section */
+#define CONFIG_SYS_INIT_SP_ADDR         CONFIG_SPL_BSS_START_ADDR
+/* Configure R5 SPL post-relocation malloc pool in DDR */
+#define CONFIG_SYS_SPL_MALLOC_START    0x84000000
+#define CONFIG_SYS_SPL_MALLOC_SIZE     SZ_16M
+#endif
+
+#define PARTS_DEFAULT \
+	/* Linux partitions */ \
+	"name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0"
+
+/* U-Boot general configuration */
+#define EXTRA_ENV_AM642_BOARD_SETTINGS					\
+	"findfdt="							\
+		"if test $board_name = am64x_gpevm; then " \
+			"setenv fdtfile k3-am642-evm.dtb; fi; " \
+		"if test $board_name = am64x_skevm; then " \
+			"setenv fdtfile k3-am642-sk.dtb; fi;" \
+		"if test $fdtfile = undefined; then " \
+			"echo WARNING: Could not determine device tree to use; fi; \0" \
+	"name_kern=Image\0"						\
+	"console=ttyS2,115200n8\0"					\
+	"args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000 "	\
+		"${mtdparts}\0"						\
+	"run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0"
+
+/* U-Boot MMC-specific configuration */
+#define EXTRA_ENV_AM642_BOARD_SETTINGS_MMC				\
+	"boot=mmc\0"							\
+	"mmcdev=1\0"							\
+	"bootpart=1:2\0"						\
+	"bootdir=/boot\0"						\
+	"rd_spec=-\0"							\
+	"init_mmc=run args_all args_mmc\0"				\
+	"get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+	"get_overlay_mmc="						\
+		"fdt address ${fdtaddr};"				\
+		"fdt resize 0x100000;"					\
+		"for overlay in $name_overlays;"			\
+		"do;"							\
+		"load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && "	\
+		"fdt apply ${dtboaddr};"				\
+		"done;\0"						\
+	"get_kern_mmc=load mmc ${bootpart} ${loadaddr} "		\
+		"${bootdir}/${name_kern}\0"				\
+	"get_fit_mmc=load mmc ${bootpart} ${addr_fit} "			\
+		"${bootdir}/${name_fit}\0"				\
+	"partitions=" PARTS_DEFAULT
+
+/* Incorporate settings into the U-Boot environment */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	DEFAULT_LINUX_BOOT_ENV						\
+	DEFAULT_MMC_TI_ARGS						\
+	EXTRA_ENV_AM642_BOARD_SETTINGS					\
+	EXTRA_ENV_AM642_BOARD_SETTINGS_MMC
+
+/* Now for the remaining common defines */
+#include <configs/ti_armv7_common.h>
+
+/* MMC ENV related defines */
+#ifdef CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART	1
+#endif
+
+#endif /* __CONFIG_AM642_EVM_H */
diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h
index ce0cd38f56e..e6cb1d0540e 100644
--- a/include/dt-bindings/pinctrl/k3.h
+++ b/include/dt-bindings/pinctrl/k3.h
@@ -2,7 +2,7 @@
 /*
  * This header provides constants for TI K3-AM65 pinctrl bindings.
  *
- * Copyright (C) 2018 Texas Instruments
+ * Copyright (C) 2018-2021 Texas Instruments
  */
 #ifndef _DT_BINDINGS_PINCTRL_TI_K3_AM65_H
 #define _DT_BINDINGS_PINCTRL_TI_K3_AM65_H
@@ -38,4 +38,7 @@
 #define J721E_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
 #define J721E_WKUP_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
 
+#define AM64X_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
+#define AM64X_MCU_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
+
 #endif
diff --git a/include/linux/soc/ti/k3-navss-ringacc.h b/include/linux/soc/ti/k3-navss-ringacc.h
index 9176277ff0b..0ad8f203da1 100644
--- a/include/linux/soc/ti/k3-navss-ringacc.h
+++ b/include/linux/soc/ti/k3-navss-ringacc.h
@@ -83,22 +83,17 @@ struct k3_nav_ring_cfg {
 };
 
 #define K3_NAV_RINGACC_RING_ID_ANY (-1)
-#define K3_NAV_RINGACC_RING_USE_PROXY BIT(1)
 
 /**
  * k3_nav_ringacc_request_ring - request ring from ringacc
  * @ringacc: pointer on ringacc
  * @id: ring id or K3_NAV_RINGACC_RING_ID_ANY for any general purpose ring
- * @flags:
- *	@K3_NAV_RINGACC_RING_USE_PROXY: if set - proxy will be allocated and
- *		used to access ring memory. Sopported only for rings in
- *		Message/Credentials/Queue mode.
  *
  * Returns pointer on the Ring - struct k3_nav_ring
  * or NULL in case of failure.
  */
 struct k3_nav_ring *k3_nav_ringacc_request_ring(struct k3_nav_ringacc *ringacc,
-						int id, u32 flags);
+						int id);
 
 int k3_nav_ringacc_request_rings_pair(struct k3_nav_ringacc *ringacc,
 				      int fwd_id, int compl_id,
@@ -238,4 +233,19 @@ int k3_nav_ringacc_ring_push_head(struct k3_nav_ring *ring, void *elem);
  */
 int k3_nav_ringacc_ring_pop_tail(struct k3_nav_ring *ring, void *elem);
 
+/* DMA ring support */
+struct ti_sci_handle;
+
+/**
+ * struct struct k3_ringacc_init_data - Initialization data for DMA rings
+ */
+struct k3_ringacc_init_data {
+	const struct ti_sci_handle *tisci;
+	u32 tisci_dev_id;
+	u32 num_rings;
+};
+
+struct k3_nav_ringacc *k3_ringacc_dmarings_init(struct udevice *dev,
+						struct k3_ringacc_init_data *data);
+
 #endif /* __SOC_TI_K3_NAVSS_RINGACC_API_H_ */
diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h
index eb916ba1019..794737923cf 100644
--- a/include/linux/soc/ti/ti_sci_protocol.h
+++ b/include/linux/soc/ti/ti_sci_protocol.h
@@ -379,6 +379,13 @@ struct ti_sci_rm_psil_ops {
 #define TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST		0
 #define TI_SCI_RM_UDMAP_RX_FLOW_DESC_MONO		2
 
+#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES	1
+#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES	2
+#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES	3
+
+#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_TCHAN		0
+#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_BCHAN		1
+
 /* UDMAP TX/RX channel valid_params common declarations */
 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID		BIT(0)
 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID                BIT(1)
@@ -389,6 +396,7 @@ struct ti_sci_rm_psil_ops {
 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID                  BIT(6)
 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID             BIT(7)
 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID       BIT(8)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_VALID		BIT(14)
 
 /**
  * Configures a Navigator Subsystem UDMAP transmit channel
@@ -403,6 +411,8 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg {
 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID        BIT(11)
 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID      BIT(12)
 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID            BIT(13)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID            BIT(15)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_EXTENDED_CH_TYPE_VALID	BIT(16)
 	u16 nav_id;
 	u16 index;
 	u8 tx_pause_on_err;
@@ -419,6 +429,9 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg {
 	u8 tx_orderid;
 	u16 fdepth;
 	u8 tx_sched_priority;
+	u8 tx_burst_size;
+	u8 tx_tdtype;
+	u8 extended_ch_type;
 };
 
 /**
@@ -448,6 +461,7 @@ struct ti_sci_msg_rm_udmap_rx_ch_cfg {
 	u8 rx_chan_type;
 	u8 rx_ignore_short;
 	u8 rx_ignore_long;
+	u8 rx_burst_size;
 };
 
 /**