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authorAndre Schwarz2008-04-29 19:18:32 +0200
committerWolfgang Denk2008-05-03 23:27:04 +0200
commit9acde129cc3f9c1b3bc11a821480dd446774d618 (patch)
tree408342b2cea52b5b979c0ca86bb5c4af95027076 /lib_m68k/board.c
parent27c38689d0cfde0e444239345f97b5eecc9f4067 (diff)
TSEC: add config options for VSC8601 RGMII PHY
The Vitesse VSC8601 RGMII PHY has internal delay for both Rx and Tx clock lines. They are configured using 2 bits in extended register 0x17. Therefore CFG_VSC8601_SKEW_TX and CFG_VSC8601_SKEW_RX have been introduced with valid values 0-3 giving 0.0, 1.4,1.7 and 2.0ns delay. Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Acked-by: Andy Fleming <afleming@freescale.com> Acked-by: Ben Warren <biggerbadderben@gmail.com> -- drivers/net/tsec.c | 6 ++++++ drivers/net/tsec.h | 3 +++ 2 files changed, 9 insertions(+), 0 deletions(-)
Diffstat (limited to 'lib_m68k/board.c')
0 files changed, 0 insertions, 0 deletions