ppc4xx: Change Kilauea to use the common DDR2 init function

This patch changes the kilauea and kilauea_nand (for NAND booting)
board port to not use a board specific DDR2 init routine anymore. Now
the common code from cpu/ppc4xx is used.

Thanks to Grant Erickson for all his basic work on this 405EX early
bootup.

Signed-off-by: Stefan Roese <sr@denx.de>

3 files changed, 13 insertions, 14 deletions

diff --git a/nand_spl/board/amcc/kilauea/Makefile b/nand_spl/board/amcc/kilauea/Makefile
index 84bd29824d8..a0293ee2b58 100644
--- a/nand_spl/board/amcc/kilauea/Makefile
+++ b/nand_spl/board/amcc/kilauea/Makefile
@@ -29,8 +29,8 @@ LDFLAGS	= -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
 AFLAGS	+= -DCONFIG_NAND_SPL
 CFLAGS	+= -DCONFIG_NAND_SPL
 
-SOBJS	= start.o init.o resetvec.o cache.o
-COBJS	= memory.o nand_boot.o nand_ecc.o ndfc.o
+SOBJS	= start.o resetvec.o cache.o
+COBJS	= 44x_spd_ddr2.o nand_boot.o nand_ecc.o ndfc.o
 
 SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
@@ -57,10 +57,18 @@ $(nandobj)u-boot-spl:	$(OBJS)
 # create symbolic links for common files
 
 # from cpu directory
+$(obj)44x_spd_ddr2.c: ecc.h
+	@rm -f $(obj)44x_spd_ddr2.c
+	ln -s $(SRCTREE)/cpu/ppc4xx/44x_spd_ddr2.c $(obj)44x_spd_ddr2.c
+
 $(obj)cache.S:
 	@rm -f $(obj)cache.S
 	ln -s $(SRCTREE)/cpu/ppc4xx/cache.S $(obj)cache.S
 
+$(obj)ecc.h:
+	@rm -f $(obj)ecc.h
+	ln -s $(SRCTREE)/cpu/ppc4xx/ecc.h $(obj)ecc.h
+
 $(obj)ndfc.c:
 	@rm -f $(obj)ndfc.c
 	ln -s $(SRCTREE)/cpu/ppc4xx/ndfc.c $(obj)ndfc.c
@@ -73,15 +81,6 @@ $(obj)start.S:
 	@rm -f $(obj)start.S
 	ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S
 
-# from board directory
-$(obj)init.S:
-	@rm -f $(obj)init.S
-	ln -s $(SRCTREE)/board/amcc/kilauea/init.S $(obj)init.S
-
-$(obj)memory.c:
-	@rm -f $(obj)memory.c
-	ln -s $(SRCTREE)/board/amcc/kilauea/memory.c $(obj)memory.c
-
 # from nand_spl directory
 $(obj)nand_boot.c:
 	@rm -f $(obj)nand_boot.c
diff --git a/nand_spl/board/amcc/kilauea/config.mk b/nand_spl/board/amcc/kilauea/config.mk
index 22490918d07..d89ed3f0478 100644
--- a/nand_spl/board/amcc/kilauea/config.mk
+++ b/nand_spl/board/amcc/kilauea/config.mk
@@ -29,8 +29,9 @@
 #
 # On 4xx platforms the SPL is located at 0xfffff000...0xffffffff,
 # in the last 4kBytes of memory space in cache.
-# We will copy this SPL into instruction-cache in start.S. So we set
-# TEXT_BASE to starting address in i-cache here.
+# We will copy this SPL into SDRAM since we can't access the NAND
+# controller at CS0 while running from this location. So we set
+# TEXT_BASE to starting address in SDRAM here.
 #
 TEXT_BASE = 0x00800000
 
diff --git a/nand_spl/board/amcc/kilauea/u-boot.lds b/nand_spl/board/amcc/kilauea/u-boot.lds
index 084db08dd6a..03e0b798f93 100644
--- a/nand_spl/board/amcc/kilauea/u-boot.lds
+++ b/nand_spl/board/amcc/kilauea/u-boot.lds
@@ -32,7 +32,6 @@ SECTIONS
   .text      :
   {
     start.o	(.text)
-    init.o	(.text)
     nand_boot.o	(.text)
     ndfc.o	(.text)