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| author | Patrick Delaunay | 2019-01-30 13:07:05 +0100 |
|---|---|---|
| committer | Tom Rini | 2019-02-09 07:50:57 -0500 |
| commit | e74b74c52876d776dda7a7ee5e2a8d555eaa5c4f (patch) | |
| tree | 960fda40cbbcddb03270d37572a4bfa42b13e71d /post | |
| parent | 8d6310aa0ba2bee92e14c0702c5ceec64943383a (diff) | |
dts: stm32mp1: clock tree update
- Add st,digbypass on clk_hse node (needed for board rev.C)
- MLAHB/AHB max frequency increased from 200 to 209MHz, with:
- PLL3P set to 208.8MHz for MCU sub-system
- PLL3Q set to 24.57MHz for 48kHz SAI/SPI2S
- PLL3R set to 11.29MHz for 44.1kHz SAI/SPI2S
- PLL4P set to 99MHz for SDMMC and SPDIFRX
- PLL4Q set to 74.25MHz for EVAL board
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Diffstat (limited to 'post')
0 files changed, 0 insertions, 0 deletions